阅读说明：本技术 用于多芯片封装（mcp）的可旋转架构 (Rotatable architecture for multi-chip package (MCP) ) 是由 A·侯赛因 A·那拉马尔普 S·苏巴雷迪 于 2019-05-29 设计创作，主要内容包括：本发明公开了一种多芯片封装器件,其可以包括具有第一集成电路的第一集成电路管芯,使得第一集成电路可以包括设置在第一集成电路管芯的第一侧上的第一多个端口和设置在第一集成电路管芯的第二侧上的第二多个端口。多芯片封装器件还可以包括第二集成电路管芯,使得第二集成电路可以包括设置在第二集成电路管芯的第三侧上的第三多个端口。当第一集成电路与第一集成电路管芯的第一侧相邻放置时,第一集成电路可以与第二集成电路的第一侧通信,并且当第一集成电路与第二侧相邻放置时,第一集成电路可以与第一集成电路管芯的第二侧通信。(A multi-chip package device may include a first integrated circuit die having a first integrated circuit such that the first integrated circuit may include a first plurality of ports disposed on a first side of the first integrated circuit die and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip package device may also include a second integrated circuit die such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with a first side of the second integrated circuit when the first integrated circuit is positioned adjacent to the first side of the first integrated circuit die, and the first integrated circuit may communicate with a second side of the first integrated circuit die when the first integrated circuit is positioned adjacent to the second side.)

1. A multi-chip package device for providing a first integrated circuit die that is compatible for communication with either side of a second integrated die when rotated, the multi-chip package device comprising:

a first integrated circuit die, comprising:

a first plurality of ports disposed on a first side of the first integrated circuit die; and

a second plurality of ports disposed on a second side of the first integrated circuit die; and

a second integrated circuit die comprising a third plurality of ports disposed on a first side of the second integrated circuit die, wherein the second integrated circuit die is configured to communicate with the first integrated circuit die via the third plurality of ports and the first plurality of ports when the first side of the first integrated circuit die is positioned adjacent to the first side of the second integrated circuit die, and wherein the second integrated circuit die is configured to communicate with the first integrated circuit die via the third plurality of ports and the second plurality of ports when the second side of the first integrated circuit die is positioned adjacent to the first side of the second integrated circuit die.

2. The multi-chip package device of claim 1, wherein the third plurality of ports is configured to enable the second integrated circuit die to communicate with the first plurality of ports of the first integrated circuit die or the second plurality of ports of the first integrated circuit die.

3. The multi-chip package device of any preceding claim, wherein the first integrated circuit die comprises a Field Programmable Gate Array (FPGA).

4. The multi-chip package device of claim 3, wherein the second integrated circuit die comprises a transceiver.

5. The multi-chip package device of claim 4, wherein the first plurality of ports of the first integrated circuit die, the second plurality of ports of the first integrated circuit die, and the third plurality of ports of the second integrated circuit die are configured to communicate via one or more data lanes and one or more auxiliary lanes.

6. The multi-chip package device of any preceding claim, wherein the one or more auxiliary channels are configured to transmit and receive data between the FPGA and the transceiver, between the transceiver and a different transceiver, or between the FPGA and the transceiver and between the transceiver and a different transceiver.

7. The multi-chip package device of any preceding claim, wherein each of the first, second, and third pluralities of ports is configured to communicate via one or more data channels and one or more auxiliary channels, and wherein the one or more data channels and the one or more auxiliary channels are configured to enable the second integrated circuit die to communicate with the first integrated circuit die via each of the first plurality of ports or each of the second plurality of ports.

8. The multi-chip package device of any preceding claim, wherein the first, second, and third pluralities of ports are configured to communicate via a first, second, and third set of auxiliary channels, respectively, and wherein the third set of auxiliary channels is configured to enable the second integrated circuit die to communicate with the first integrated circuit die via one or more intermediate ports of the first or second pluralities of ports.

9. The multi-chip package device of claim 8, wherein the one or more middle ports comprise a first even port, and wherein the first plurality of ports comprises a second even port.

10. The multi-chip package device of any preceding claim, wherein the first, second, and third pluralities of ports are configured to communicate via first, second, and third sets of auxiliary channels, respectively, and wherein the third set of auxiliary channels is configured to enable the second integrated circuit die to communicate with the first integrated circuit die via top and bottom ports of the first, second, and third pluralities of ports.

11. An integrated circuit die that is compatible for communication with either side of an additional integrated die when rotated, the integrated circuit die comprising:

a first plurality of ports disposed on a first side of the integrated circuit die, wherein the first side of the integrated circuit die is configured to communicate with an additional integrated circuit die via a second side of the additional integrated circuit die or a third side of the additional integrated circuit die, wherein the additional integrated circuit die includes a second plurality of ports disposed on the second side of the additional integrated circuit die and a third plurality of ports disposed on the third side of the additional integrated circuit die, and wherein a portion of each of the first, second, and third plurality of ports is configured to communicate via one or more auxiliary channels when the integrated circuit die is oriented in a first direction or when the integrated circuit die is oriented in a second direction corresponding to a 180 degree rotation of the integrated circuit die relative to the first direction, and positioned such that the first plurality of ports can interface with the second plurality of ports and the third plurality of ports.

12. The integrated circuit die of claim 11, wherein the portion of each of the first, second, and third pluralities of ports is located intermediate the first, second, and third pluralities of ports.

13. The integrated circuit die of claim 11 or 12, wherein the portion of each of the first, second, and third pluralities of ports is located on at least two outer ends of the first, second, and third pluralities of ports.

14. The integrated circuit die of claim 11, 12 or 13, wherein additional portions of the first, second and third pluralities of ports are configured to communicate via one or more data lanes.

15. The integrated circuit die of claim 11, 12, 13, or 14, wherein each of the first, second, and third pluralities of ports comprises an odd number of ports, and wherein the portion of the first, second, and third pluralities of ports comprises one port, and wherein the one or more auxiliary channels correspond to communications from the middle of the first, second, and third pluralities of ports.

Technical Field

The present disclosure relates to an appropriate channel block on an integrated circuit die for supporting different dies including programmable logic.

Background

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present disclosure that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. It should be understood, therefore, that these written descriptions are to be read in this sense and not as admissions of prior art.

Integrated circuit devices are used in many electronic systems. Computers, hand-held devices, cellular phones, televisions, industrial control systems, robots, and telecommunications networks, to name a few, all use integrated circuit devices. Integrated circuit devices can be formed using photolithographic techniques that pattern circuits onto a substrate wafer that is diced to form a plurality of (typically identical) individual integrated circuit dies. Each integrated circuit die may include many different components, such as programmable logic fabrics, digital or analog signal transmission circuitry, digital signal processing circuitry, dedicated data processing circuitry, memory, and so forth.

In general, different components may be based on different underlying technologies. Thus, a different die may be used for each group of different components. For example, a programmable logic fabric such as a Field Programmable Gate Array (FPGA) fabric may be provided on a main die, while a high-speed transceiver in communication with the FPGA may be moved off-chip to one or more secondary dies. However, when multiple second dies are connected on different sides of the main die, there may be different second die configurations depending on which side of the main die these second dies are connected to. For example, a second die connected on the right side of the main die may not be connected to the left side of the main die. Furthermore, if a second die having a "right side" configuration is inadvertently placed on the left side of the primary die (or vice versa), the second die may not be operable with the primary die.

Drawings

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a block diagram of a multi-die integrated circuit system having an interface bridge for facilitating efficient communication between dies, according to an embodiment;

FIG. 2 is a schematic cross-sectional view of a portion of the integrated circuit system of FIG. 1, in accordance with an embodiment;

figure 3 is a block diagram illustrating a conventional architecture of a transceiver tile of the integrated circuit system of figure 1, according to an embodiment;

FIG. 4 is a block diagram illustrating rotatable transceiver tiles including data and auxiliary capabilities for all channels according to an embodiment;

FIG. 5 is a block diagram illustrating a rotatable transceiver tile including auxiliary capabilities for an intermediate channel, according to an embodiment;

FIG. 6 is a block diagram illustrating rotatable transceiver tiles including auxiliary capabilities for top and bottom channels, according to an embodiment;

FIG. 7 is a block diagram illustrating a rotatable transceiver tile that allows a right side tile to rotate and function as a left side transceiver tile, according to an embodiment; and

figure 8 is a block diagram illustrating a multi-die integrated circuit system utilizing rotatable transceiver tiles assembled on a package substrate, according to an embodiment.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Multichip systems can be represented as 2.5D systems of independent integrated circuit dies, which can transfer signals between each other in an efficient manner. In a 2.5D arrangement, the number of connections available between dies may be less than the number of connections available if multiple dies are part of a single monolithic integrated circuit die. However, there are many reasons for separating integrated circuit dies rather than combining them into a single monolithic integrated circuit die. In particular, some techniques, such as analog techniques used in high-speed transceivers, may not scale as easily to newer photolithographic techniques as other circuits, such as programmable fabrics of Programmable Logic Devices (PLDs), e.g., Field Programmable Gate Array (FPGA) fabrics. With this in mind, a high-speed multi-chip-package FPGA device may include a high-speed transceiver in communication with the FPGA fabric, and the transceiver includes a left transceiver tile (e.g., oriented to connect to the left side of the FPGA die) for communicating with the left edge of the FPGA fabric and/or a right transceiver tile (e.g., oriented to connect to the right side of the FPGA die) for communicating with the right edge of the FPGA fabric. Although the present disclosure will primarily use the example of an FPGA die and a transceiver die, the systems and methods of the present disclosure may be applied to any suitable integrated circuit device. Indeed, the systems and methods of the present disclosure may include any suitable first die that may accept right and/or left side connections to a second die that may be rotated to interface with either the right side connections or the left side connections. The first die and/or the second die may represent, for example, a processor, a memory, a transceiver, a programmable logic device such as an FPGA, or a peripheral device, to name a few examples, but not limited to a particular type of die.

Utilizing the example of separate dies for the FPGA fabric and the transceiver to facilitate communication between the FPGA fabric on one die and the transceiver on a second die, the FPGA may include a left edge and a right edge that interface with high speed transceiver tiles of the transceiver block containing the channels. In some architectural arrangements where an FPGA on one die communicates with transceiver tiles on a different die, a particular transceiver tile having a certain arrangement or orientation is used to communicate with the left edge of the FPGA fabric, and another transceiver tile is used to communicate with the right edge of the FPGA fabric. Thus, because the transceiver tiles are oriented for the left and right edges, a separate tape-out is used for each side of the transceiver tile. Since the common elements on the FPGA fabric die and the transceiver tiles are not positioned in the same manner, the flow sheets of the left and right transceiver tiles are not rotatable. Since the tiles are not rotatable and separate flowsheets are used for each side of the transceiver tile, each flowsheet has its own corresponding photomask cost. As used herein, a channel may also be described as a port that facilitates communication across FPGA fabric dies, transceiver tiles, and the like. In some embodiments, the auxiliary channels and data channels used herein should be understood to be auxiliary ports and data ports that also form communication channels when transmitting or receiving between ports.

In view of the above, transceiver tiles may contain transceiver chunks, and transceiver channels may be grouped into these transceiver chunks. Each chunk may have some (e.g., X) number of lanes, and may include various lane types, such as data lanes and/or auxiliary lanes. The auxiliary channel may be used to enable communication between the FPGA and the transceiver through a Security Device Manager (SDM) of the FPGA that may be used for device configuration, a subsystem manager (SSM) of the transceiver that may be used to configure the transceiver path to conform to various input and output protocols, and the like. For example, the 16 transceiver lanes may be configured as 16 lanes for various functions, such as a peripheral component interconnect express (PCIe) x16 endpoint, a 4-lane ethernet endpoint, or a serial (e.g., JESD204b standard) interface connection. In this case, if the secondary channel terminates at SSM, there may be no transceiver channel corresponding to the secondary channel. However, by adding an auxiliary channel in the manner described herein, the auxiliary channel can provide communication between the FPGA and the transceiver, as well as enable communication between two or more transceivers. The data channel may be used to transmit data received on the transceiver channel for transmission to the corresponding configurable FPGA fabric. Thus, the data channels may correspond one-to-one with transceiver channels in a transceiver tile.

When separating dies, the left die or transceiver tile may contain a channel configuration oriented to interface with the left side of the FPGA, while the right die or transceiver tile may contain a channel configuration that is uniquely compatible with the right side. The compatibility of the left or right transceiver tiles may be determined based on the channel configuration within the channel group block, such that if the right tile is rotated to be used for the left tile, the location of the channel type in the right tile may not be in the same location, and thus, the location of the channel type in the right tile may not be able to communicate with a different edge of the same FPGA that may communicate with the transceiver tiles if positioned or oriented differently. In this regard, the rotatable transceiver tiles may allow the same tiles to be used for both the right and left edges of the FPGA.

For example, the ability to use a left transceiver tile as a right transceiver tile may be accomplished by using a rotatable transceiver tile, which may be implemented by adding channel capabilities or changing the channel position within the transceiver block of the transceiver tile. It may be desirable to maintain rotatable transceiver tiles that can be used for multiple edges of the FPGA because the same flow sheet and photomask of the transceiver tile can be used for both sides. Tape-out is the final result of the design process of an integrated circuit or printed circuit board before it is sent for manufacture. Specifically, tape-out is the point at which the pattern design of the photomask of the circuit is sent to the manufacturing facility. A photolithographic photomask is used to create a layer pattern for an integrated circuit. As described above, some types of circuit architectures use separate flowsheets for each of the left and right transceiver tiles, and thus use separate photomasks with separate respective costs. Given these types of architectures, the right transceiver tile cannot be rotated and used for the left transceiver tile because there is a channel type mismatch. .

To enable efficient use of the transceiver tiles, the transceiver tiles may be configured such that they may be rotated and used to communicate with different edges (e.g., right, left, top, and bottom) of the FPGA fabric on the individual die. For example, in one embodiment, modifying the channel position or capability may allow the transceiver tile to be rotatable and interface with different types of transceivers. As a result, the cost of the photomask used to manufacture one tile design, rather than the cost of manufacturing two separate designs for each left and right transceiver tile.

By way of introduction, fig. 1 illustrates an exemplary Integrated Circuit (IC) system 10 that includes a first Integrated Circuit (IC) die 12 connected to any suitable number of second IC dies 14. First IC die 12 and second IC die 14 may be connected by any suitable conductive bridge, such as silicon bridge 34 or a bridge structure disposed in a substrate (e.g., intel's embedded multi-die interconnect bridge (EMIB)), or by a direct connection between first IC die 12 and second IC die 14. First IC die 12 and second IC die 14 may be any suitable integrated circuit devices. In one example, the first IC die 12 may be an integrated circuit device including a programmable logic fabric such as a Field Programmable Gate Array (FPGA), and the second IC die 14 may be a high-speed transceiver. While the examples provided below may refer to first IC die 12 as an FPGA and second IC die 14 as a high-speed transceiver tile, other types of integrated circuit devices may benefit from the present disclosure. These may include digital processing circuits, Central Processing Unit (CPU) subsystems, parallel input/output (I/O) offload, Digital Signal Processing (DSP) arrays, and so forth.

IC system 10 may benefit from efficiently using the same transceiver tile (e.g., second IC die 14) for left and right transceiver tiles coupled to corresponding edges of an FPGA (e.g., first IC die 12 of fig. 1), as shown in fig. 3. As such, the transceiver tiles may be developed in a rotatable manner that may be efficient and compatible to be used interchangeably for the left and right edges of the FPGA.

The FPGA may be connected to the transceiver tiles through the physical chip-to-chip interconnect of silicon bridge 34 via logical Interface Bridge (IB)32, which logical Interface Bridge (IB)32 controls the manner in which signals are sent and received. That is, as used herein, interface bridge 32 represents the logical connections between the FPGA and the transceiver tiles. Interface bridge 32 handles the transfer of signals between the physical chip-to-chip interconnects of silicon bridge 34.

Referring now to fig. 2, fig. 2 illustrates a schematic cross-sectional view of the IC system 10 of fig. 1 along cut line 1-1. As shown in fig. 2, the silicon bridge 34 may be an interposer (as shown), or may be any other suitable silicon bridge disposed on a substrate (e.g., an interconnect bridge such as the embedded multi-die interconnect bridge (EMIB) of intel corporation). In other examples, the first IC die 12 and the second IC die 14 may be directly connected to each other in a stacked fashion. In the example shown in fig. 2, silicon bridge 34 represents a Ball Grid Array (BGA) interposer using solder balls 38 that may be electrically connected to other circuitry, such as a Printed Circuit Board (PCB) (not shown). Physical interconnections between the first IC die 12 and the second IC die 14 occur through corresponding respective interconnection points 32 (here in the form of micro-bumps) that are coupled to one another by chip-to-chip interconnections 40 within the silicon bridge 34.

It should be understood that fig. 2 represents a 2.5D arrangement using silicon bridge 34 to connect first IC die 12 and second IC die 14. In other embodiments, the first IC die 12 and the second IC die 14 may be connected in a 3D arrangement, where the interconnect points 32 may be directly connected to the other IC. For example, the second IC die 14 may be stacked on top of the first IC die 12, and the interconnect points 32 may be directly connected to corresponding interconnect structures on the first IC die 12.

As previously described, the right transceiver tile (e.g., second IC die 14) may include at least one transceiver block having a plurality of channels oriented at 180 degrees, including various channels (e.g., data channels and auxiliary channels), and the channels are positioned such that the transceiver tile may be coupled to a corresponding edge of an FPGA (e.g., first IC die 12). To use the same design for the left transceiver tile, a new flit and photomask are created to allow compatibility with the right edge of the FGPA. By adding multiple channel capabilities to different transceiver block channels, the channel blocks and transceiver tiles become rotatable. Rotatable tiles may be used to communicate with the right and left edges of the FPGA. The configuration of the transceiver block lanes may include adding an auxiliary lane to all data lanes for an even or odd number of lane configurations, adding an auxiliary lane to top and bottom data lanes for an even or odd number of lane configurations, or adding an auxiliary lane to an intermediate data lane for an even or odd number of lane configurations. Adding supplemental channel capabilities to the data channel in these design configurations may allow transceiver tile adaptability such that the same design may be used for both left and right transceiver tiles. Further, while some of the following description describes transceiver blocks of left and right transceiver tiles, which represent particular embodiments, it should be noted that the devices described herein may be used on a single transceiver tile and have matching transceiver block channel configurations on either side of the transceiver tile so that the tile may be used to communicate with either side (e.g., right and left edges) of the FPGA fabric without rotation.

To aid illustration, a block diagram 50 of a detailed view of a non-rotatable architecture of transceiver block channels of left side transceiver tile 19 and right side transceiver tile 18 is shown in FIG. 3. In particular, block diagram 50 shows the orientation of right transceiver tile 18 and left transceiver tile 19 (which may be part of second IC die 14, for example) positioned to communicate with respective edges of FPGA 16. In some embodiments, transceiver blocks 20, 22 of right transceiver tile 18 and left transceiver tile 19 may contain multiple data channels and one auxiliary channel. As shown, in one particular embodiment, one auxiliary channel may be positioned as a bottom channel of transceiver blocks 20, 22 of right and left transceiver tiles 18, 19. Although the design and configuration appears the same, the right and left transceiver tiles 18, 19 communicate with opposite edges of the FPGA 16.

For example, as shown, right transceiver tile 18 containing right transceiver block 20 to be used for left edge 26 of FPGA16 is rotated, positioning the auxiliary channel of right transceiver tile 18 on top of right transceiver block 20. Thus, simply rotating right transceiver tile 18 does not allow compatible communication with left edge 26 of FPGA16 because there is a mismatch in channel compatibility 30. As shown in fig. 4, modifying the type and positioning of channels in transceiver tiles such as right transceiver tile 20 of right transceiver tile 18, and modifying corresponding edges (e.g., right edge 24 and left edge 26) of FPGA16 to correspond to modified transceiver tile 15, may allow transceiver tile 15 to rotate and function as either left transceiver tile 19 or right transceiver tile 18, and allow communication between the two dies regardless of the position of FPGA16 and transceiver tile 15.

With the above in mind, block diagram 55 of FIG. 4 illustrates a rotatable transceiver tile 15 incorporating auxiliary capabilities into all data channels in accordance with an embodiment of the present disclosure. Regardless of the number of lanes (e.g., even or odd) in the transceiver blocks 20, 22, each data lane may include auxiliary capabilities. Similarly, the FPGA16 channel configuration may also be modified to correspond to the second IC circuit die 14 containing the transceiver blocks 20, 22.

Since each channel includes auxiliary and data capabilities, the right transceiver tile 20 contained in the rotatable transceiver tile 15 located on the right side of the FPGA16 may be rotated for use on the left side of the FPGA 16. Thus, rotatable transceiver tiles 15 with data and auxiliary channel capabilities in all channels may be rotated to the left and allow compatible communication with the left edge 26 of the FPGA16 because there is a channel compatibility 30 match to allow communication between the two dies.

Furthermore, incorporating auxiliary channels or auxiliary capabilities into the top and bottom channels may be another embodiment for facilitating rotatable transceiver tiles 15, as shown in block diagram 60 of FIG. 5. As depicted in this embodiment, the top and bottom channels of the rotatable transceiver tile 15 disposed on the right side of the FPGA16 may include auxiliary channels or include auxiliary capabilities, while the remaining intermediate channels may be data channels. The number of channels in this configuration may be incorporated into the even or odd number of channels in the transceiver blocks 20, 22.

Since the top and bottom channels may be or include auxiliary capabilities and the middle channel is a data channel, rotatable transceiver tiles 15 disposed on the right side of FPGA16 may be rotated for use on the left side of FPGA 16. Thus, a rotatable transceiver tile 15 having this configuration may be rotated to the left and allow compatible communication with the left edge 26 of the FPGA16 because there is a channel compatibility 30 match.

Further, block diagram 65 of fig. 6 depicts a rotatable transceiver tile 15 that includes an intermediate channel that has auxiliary channels or includes auxiliary capabilities, while the remaining channels may be data channels, according to an embodiment of the present disclosure. Similarly, the channel configuration of the FPGA16 may be modified to correspond to the transceiver tile 15 containing the transceiver blocks 20, 22 to allow communication between the two dies. Thus, the number of channels in this configuration may exemplify an odd number of channels in the transceiver block of the rotatable transceiver tile 15. However, this configuration may also be implemented in transceiver blocks having an even number of channels of rotatable transceiver tiles 15. That is, transceiver tiles 15 and FPGAs 16 that include an even number of channels may use intermediate channels (e.g., an appropriate even number) as auxiliary channels or include auxiliary capabilities, while using top and bottom channels as data channels, thereby making transceiver tiles 15 and FPGAs 16 rotatable. As such, the intermediate channel(s) (e.g., one or more) may be auxiliary channels or include auxiliary capabilities to facilitate rotatability of the die.

Since the middle channel may be an auxiliary channel or include auxiliary capabilities, the transceiver blocks of transceiver tiles 15 may be rotated from the right side of FPGA16 for use on the left side of FPGA 16. Thus, transceiver tile 15 with the auxiliary intermediate channels may be rotated to the left and allow compatible communication with left edge 26 of FPGA16 because there is a channel compatibility 30 match to allow communication between the two dies.

Considering the discussed implementation of rotatable transceiver tile 15, a block diagram of integrated system 10 of fig. 1 is shown in fig. 7, which illustrates FPGA16 (e.g., first IC die 12 of fig. 1) and rotatable transceiver tile 15 (e.g., second IC die 14 of fig. 1) according to one embodiment of the present disclosure. As previously described and illustrated, the first IC die 12 and the second IC die 14 may be connected by a bridge structure, such as an EMIB 34, disposed on the substrate.

As disclosed, the rotatable second IC die 14 (e.g., transceiver tile 15) may allow the same tile to be used to communicate with a different edge of the first IC die 12 (e.g., FPGA 16). In some embodiments, first IC die 12 may be FPGA16 and second IC die 14 may be transceiver tiles 15, and relocating or adding channel capabilities (e.g., supplemental channels) may allow the same transceiver tiles 15 to be efficiently used to communicate with different edges of FPGA 16. Since the same transceiver tile 15 may be rotated and used to communicate with both edges of the FPGA16, only one design or photomask of the transceiver tile may be transmitted for manufacturing to facilitate communication between the various FPGAs 16.

Thus, the block diagram of the integrated system 10 in fig. 8 shows a first IC die 12 and a rotatable second IC die 14 assembled on a package substrate. As shown, the left and right second IC dies 14 are identical. According to embodiments of the present disclosure, integrated system 10 may be a high speed multi-chip packaged FPGA device. Thus, rotatable transceiver tile 15 may be adapted to different textured edges of FPGA 16. Furthermore, the corresponding cost of an efficient and adaptive rotatable transceiver tile and the entire package substrate may be reduced.

Accordingly, one or more of the disclosed embodiments may provide, alone or in combination, one or more technical effects, including improving the efficiency of implementing high-speed multi-chip packaged FPGA devices. In particular, the disclosed embodiments may allow for rotatable transceiver tiles 15 that may be used on either side of the FPGA16 fabric. For example, transceiver tile 15 may contain transceiver blocks 20, 22 having multiple lanes, such as auxiliary and data lanes, and may relocate or add auxiliary lanes or auxiliary capabilities. The rotatable function may be achieved by using all channels as data and auxiliary channels, orienting the auxiliary channels or auxiliary capabilities in the top and bottom channels and the middle channel may be a data channel, or orienting the auxiliary channels or capabilities in the middle channel and all other channels may be data channels. In this manner, the techniques described herein enable transceiver tile 15 to be rotatable. The rotatable functionality allows transceiver tile 15 to be compatible and used for both edges of FPGA16 fabric, thus increasing the efficiency of the overall high speed multi-chip packaged FPGA device while reducing the associated production costs.

The methods and devices of the present disclosure may be incorporated into any suitable circuit. For example, the methods and devices may be incorporated into many types of devices, such as microprocessors or other integrated circuits. Exemplary integrated circuits include Programmable Array Logic (PAL), Programmable Logic Array (PLA), Field Programmable Logic Array (FPLA), Electrically Programmable Logic Device (EPLD), Electrically Erasable Programmable Logic Device (EEPLD), Logic Cell Array (LCA), Field Programmable Gate Array (FPGA), Application Specific Standard Product (ASSP), Application Specific Integrated Circuit (ASIC), and microprocessor, to name a few.

The technology presented and claimed herein is cited and applied to material objects and concrete examples of a practical nature, which obviously improve the technical field and are therefore not abstract, intangible or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "[ means for [ perform ] [ function ] … …" or "step for [ perform ] [ function ] … …", then such elements are intended to be construed in accordance with 35u.s.c.112 (f). However, for any claim that contains elements specified in any other way, such elements should not be construed according to 35u.s.c.112 (f).

While the embodiments set forth in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.

Exemplary embodiments of the present disclosure

The following numbered clauses define certain exemplary embodiments of the present disclosure.

Clause 1,

A multi-chip package device comprising:

a first integrated circuit die, comprising:

a first plurality of ports disposed on a first side of the first integrated circuit die; and a second plurality of ports disposed on a second side of the first integrated circuit die; and

a second integrated circuit die comprising a third plurality of ports disposed on a first side of the second integrated circuit die, wherein the second integrated circuit die is configured to communicate with the first integrated circuit die via the third plurality of ports and the first plurality of ports when the first side of the first integrated circuit die is positioned adjacent to the first side of the second integrated circuit die, and wherein the second integrated circuit die is configured to communicate with the first integrated circuit die via the third plurality of ports and the second plurality of ports when the second side of the first integrated circuit die is positioned adjacent to the first side of the second integrated circuit die.

Clause 2,

The multi-chip package device of clause 1, wherein the third plurality of ports is configured to enable the second integrated circuit die to communicate with the first plurality of ports of the first integrated circuit die or the second plurality of ports of the first integrated circuit die.

Clause 3,

The multi-chip package device of clause 1, wherein the first integrated circuit die comprises a Field Programmable Gate Array (FPGA).

Clause 4,

The multi-chip package device of clause 3, wherein the second integrated circuit die comprises a transceiver.

Clause 5,

The multi-chip package device of clause 4, wherein the first plurality of ports of the first integrated circuit die, the second plurality of ports of the first integrated circuit die, and the third plurality of ports of the second integrated circuit die are configured to communicate via one or more data lanes and one or more auxiliary lanes.

Clause 6,

The multi-chip package device of clause 5, wherein the one or more auxiliary channels are configured to transmit and receive data between the FPGA and the transceiver, transmit and receive data between the transceiver and a different transceiver, or transmit and receive data between the FPGA and the transceiver and between the transceiver and a different transceiver.

Clause 7,

The multi-chip package device of clause 1, wherein each of the first, second, and third pluralities of ports is configured to communicate via one or more data channels and one or more auxiliary channels, and wherein the one or more data channels and the one or more auxiliary channels are configured to enable the second integrated circuit die to communicate with the first integrated circuit die via each of the first plurality of ports or each of the second plurality of ports.

Clause 8,

The multi-chip package device of clause 1, wherein the first, second, and third pluralities of ports are configured to communicate via a first, second, and third set of auxiliary channels, respectively, and wherein the third set of auxiliary channels is configured to enable the second integrated circuit die to communicate with the first integrated circuit die via one or more intermediate ports of the first or second pluralities of ports.

Clause 9,

The multi-chip package device of clause 8, wherein the one or more intermediate ports comprises a first even port, and wherein the first plurality of ports comprises a second even port.

Clause 10,

The multi-chip package device of clause 1, wherein the first, second, and third pluralities of ports are configured to communicate via a first, second, and third set of auxiliary channels, respectively, and wherein the third set of auxiliary channels is configured to enable the second integrated circuit die to communicate with the first integrated circuit die via top and bottom ports of the first, second, and third pluralities of ports.

Clause 11,

An integrated circuit die, comprising:

a first plurality of ports disposed on a first side of the integrated circuit die, wherein the first side of the integrated circuit die is configured to communicate with an additional integrated circuit die via a second side of the additional integrated circuit die or a third side of the additional integrated circuit die, wherein the additional integrated circuit die includes a second plurality of ports disposed on the second side of the additional integrated circuit die and a third plurality of ports disposed on the third side of the additional integrated circuit die, and wherein a portion of each of the first, second, and third plurality of ports is configured to communicate via one or more auxiliary channels when the integrated circuit die is oriented in a first direction or when the integrated circuit die is oriented in a second direction corresponding to a 180 degree rotation of the integrated circuit die relative to the first direction, and positioned such that the first plurality of ports can interface with the second plurality of ports and the third plurality of ports.

Clause 12,

The integrated circuit die of clause 11, wherein the portion of each of the first, second, and third pluralities of ports is positioned intermediate the first, second, and third pluralities of ports.

Clause 13,

The integrated circuit die of clause 11, wherein the portion of each of the first, second, and third pluralities of ports is positioned on at least two outer ends of the first, second, and third pluralities of ports.

Clause 14,

The integrated circuit die of clause 11, wherein additional portions of the first, second, and third pluralities of ports are configured to communicate via one or more data lanes.

Clause 15,

The integrated circuit die of clause 11, wherein each of the first, second, and third pluralities of ports comprises an odd number of ports, and wherein the portion of the first, second, and third pluralities of ports comprises one port, and wherein the one or more auxiliary channels correspond to communications from the middle of the first, second, and third pluralities of ports.

Clause 16,

The integrated circuit die of clause 11, wherein each of the first, second, and third pluralities of ports comprises a first even port, and wherein communication via the one or more auxiliary channels comprises a second even port.

Clause 17,

The integrated circuit die of clause 11, wherein the integrated circuit die is physically connected to the additional integrated circuit die via one or more interconnect points, and wherein the one or more interconnect points comprise one or more microbumps.

Clause 18,

A multi-chip package device comprising:

a first integrated circuit die comprising a first plurality of ports disposed on a first side of the first integrated circuit die and a second plurality of ports disposed on a second side of the first integrated circuit die, or both; and

a second integrated circuit die comprising a third plurality of ports disposed on a first side of the second integrated circuit die, wherein the first integrated circuit die is configured to communicate with the first side of the second integrated circuit die via the first side or a second side of the first integrated circuit die, wherein each of the first, second, and third plurality of ports is configured to communicate via at least one auxiliary channel formed via top and bottom ports of the first, second, and third plurality of ports.

Clause 19,

The multi-chip package device of clause 16, wherein each of the first, second, and third pluralities of ports is configured to communicate via one or more data lanes via a portion of the first, second, and third pluralities of ports, wherein the portion is positioned between the top and bottom ports of the first, second, and third pluralities of ports.

Clause 20,

The multi-chip package device of clause 16, wherein the first side and the second side are disposed on opposite sides of the first integrated circuit die.