阅读说明：本技术 包含分支存储器裸芯模块的堆叠半导体装置 (Stacked semiconductor device including bifurcated memory die module ) 是由 邱进添 S.巴加思 张聪 杨旭一 张亚舟 于 2018-06-28 设计创作，主要内容包括：公开了一种半导体装置,其包含一个或多个集成存储器模块。每个集成存储器模块可以包含一对半导体裸芯,其一起作为单个的、集成的闪速存储器操作。在一个示例中,第一裸芯可以包含存储器单元阵列,并且第二裸芯可以包含诸如CMOS集成电路的逻辑电路。在一个示例中,第二裸芯可以在第一裸芯的边缘处或在第一裸芯的中央部分处倒装芯片地接合到第一裸芯。多个集成存储器模块可以堆叠在衬底上以形成半导体装置。(A semiconductor device is disclosed that includes one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die that operate together as a single, integrated flash memory. In one example, a first die may include an array of memory cells and a second die may include logic circuitry such as a CMOS integrated circuit. In one example, the second die may be flip chip bonded to the first die at an edge of the first die or at a central portion of the first die. A plurality of integrated memory modules may be stacked on a substrate to form a semiconductor device.)

1. An integrated memory module, comprising:

a first semiconductor die;

a second semiconductor die flip chip bonded to a primary planar surface of the first semiconductor die at an edge of the primary planar surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;

wherein the first and second coupled semiconductor die are configured together as an integrated flash memory.

2. The integrated memory module of claim 1, wherein the first semiconductor die includes a plurality of memory cells.

3. The integrated memory module of claim 2, wherein the second semiconductor die includes control circuitry to control access of the plurality of memory cells.

4. The integrated memory module of claim 3, wherein the control circuitry comprises a complementary metal oxide semiconductor integrated circuit.

5. The integrated memory module of claim 1, wherein the first semiconductor die includes a plurality of bond pads configured to wire bond the first semiconductor die.

6. The integrated memory module of claim 1, wherein the first semiconductor die includes a plurality of bond pads configured to bond the first semiconductor die to the second semiconductor die.

7. The integrated memory module of claim 6, wherein the second semiconductor die includes a plurality of bumps configured to mate with a plurality of bond pads on the first semiconductor die.

8. The integrated memory module of claim 7, wherein the plurality of bumps are tapered.

9. The integrated memory module of claim 1, wherein the second semiconductor die is smaller than the first semiconductor die.

10. A semiconductor device, comprising:

a substrate;

a first integrated memory module secured to the substrate, comprising:

a first semiconductor die comprising a surface having a plurality of bond pads adjacent a first edge of the first semiconductor die and a second edge adjacent the first edge;

a second semiconductor die bonded to the surface of the first semiconductor die at the second edge;

wherein the first and second coupled semiconductor die are configured together as an integrated flash memory; and

a third semiconductor die mounted on the surface of the first semiconductor die adjacent to the second semiconductor die.

11. The semiconductor device of claim 10, wherein the third semiconductor die is offset along a first axis relative to the first semiconductor die, and wherein the third semiconductor die is offset along a second axis relative to the first semiconductor die, the second axis being orthogonal to the first axis.

12. The semiconductor device of claim 10, wherein the third semiconductor die comprises a plurality of memory units, the semiconductor device further comprising a fourth semiconductor die bonded to a surface of the third semiconductor, wherein the third and fourth coupled semiconductor die together comprise a second integrated flash memory.

13. The semiconductor device of claim 12, wherein the fourth semiconductor die is flip-chip bonded to the third semiconductor die.

14. The semiconductor device of claim 12, wherein the fourth semiconductor die is electrically connected to the third semiconductor die using through silicon vias.

15. The semiconductor device of claim 10, further comprising wire bonds extending between contact pads on the substrate and die bond pads on the first semiconductor die.

16. The semiconductor device of claim 10, wherein the plurality of bond pads on the first semiconductor die comprises a first plurality of bond pads, and wherein the third semiconductor die comprises a second plurality of bond pads.

17. The semiconductor device of claim 16, wherein the first plurality of bond pads are wire bonded to a first set of contact pads on a first edge of the substrate, and wherein the second plurality of bond pads are wire bonded to a second set of contact pads on a second edge of the substrate, the second edge of the substrate being opposite the first edge of the substrate.

18. The semiconductor device of claim 10, wherein the third semiconductor die comprises:

a surface having a plurality of die bond pads adjacent a first edge of the first semiconductor die, and a second edge adjacent the first edge, an

A plurality of memory cells within an interior of the third semiconductor die;

the semiconductor device also includes a fourth semiconductor die bonded to the surface of the third semiconductor die at a second edge of the third semiconductor die, the third and fourth coupled semiconductor die together comprising a second integrated memory module;

the semiconductor device also includes a fifth semiconductor die mounted on the surface of the third semiconductor die adjacent to the fourth semiconductor die.

19. The semiconductor device of claim 18, wherein the fifth semiconductor die is offset relative to the third semiconductor die along a first axis, and wherein the fifth semiconductor die is offset relative to the third semiconductor die along a second axis, the second axis being orthogonal to the first axis.

20. The semiconductor device of claim 18, wherein the fifth semiconductor die is aligned directly over the first semiconductor die.

21. A semiconductor device, comprising:

a substrate;

a first integrated memory module secured to the substrate, comprising:

a first semiconductor die including a surface having a plurality of bond pads adjacent a first edge of the first semiconductor die;

a second semiconductor die bonded to the surface of the first semiconductor die at a central portion of the surface of the first semiconductor die;

wherein the first and second coupled semiconductor die are configured together as an integrated flash memory; and

a third semiconductor die comprising a film layer on a surface of the third semiconductor die, the third semiconductor die mounted to the surface of the first semiconductor die, and the second semiconductor die embedded within the film layer.

22. The semiconductor device of claim 21, wherein the third semiconductor die comprises a plurality of memory units, the semiconductor device further comprising a fourth semiconductor die bonded to the surface of the third semiconductor, wherein the third and fourth coupled semiconductor die together comprise a second flash memory.

23. The semiconductor device of claim 22, wherein the fourth semiconductor die is flip-chip bonded to the third semiconductor die.

24. The semiconductor device of claim 22, wherein the fourth semiconductor die is electrically connected to the third semiconductor die using through silicon vias.

25. The semiconductor device of claim 21, further comprising wire bonds extending between contact pads on the substrate and die bond pads on the first semiconductor die.

26. The semiconductor device of claim 21, wherein the third semiconductor die comprises:

a surface having a plurality of die bond pads adjacent a first edge of the first semiconductor die, an

A plurality of memory cells within an interior of the third semiconductor die;

the semiconductor device also includes a fourth semiconductor die bonded to the surface of the third semiconductor die at a central portion of the surface of the third semiconductor die, the third and fourth coupled semiconductor die together comprising a second integrated memory module;

the semiconductor device also includes a fifth semiconductor die including a film layer on a surface of the fifth semiconductor die, the fifth semiconductor die mounted to the surface of the third semiconductor die, and the fourth semiconductor die embedded within the film layer.

27. The semiconductor device of claim 26, wherein the fourth semiconductor die is aligned directly over the second semiconductor die.

28. The semiconductor device of claim 21, wherein the third semiconductor die comprises a plurality of memory units, the semiconductor device further comprising a fourth semiconductor die bonded to a central portion of the surface of the third semiconductor, wherein the third and fourth coupled semiconductor die are together configured as an integrated flash memory.

29. The semiconductor device of claim 28, wherein the fourth semiconductor die is flip-chip bonded to the third semiconductor die.

30. An integrated memory module, comprising:

a first semiconductor die comprising a memory component;

a second semiconductor die comprising a control component, the second semiconductor die flip chip bonded to a primary planar surface of the first semiconductor die at an edge of the primary planar surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;

wherein the first and second coupled semiconductor die are configured together as an integrated flash memory.

Technical Field

The present invention relates to a memory module and a semiconductor device including the memory module.

Background

The strong growth in demand for portable consumer electronic devices is driving the demand for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are widely used to meet the increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs and cellular telephones.

Recently, ultra-high density memory devices have been proposed that use a 3D stacked memory structure with strings of memory cells formed as layers. One such storage device is sometimes referred to as a Bit cost scalable (BiCS) architecture. In addition to the hierarchical memory cells, the 3D memory device includes logic circuits to control reading/writing of the memory cells. Logic circuits, which are often fabricated using Complementary Metal Oxide Semiconductor (CMOS) technology, may typically be formed beneath stacked memory layers within a semiconductor wafer.

As the number of memory layers in a 3D memory structure increases to meet the increasing memory demands, it becomes more difficult to place logic circuitry underneath the 3D memory cell structure. Furthermore, the process parameters optimized for memory array formation may not be optimized for logic circuit formation. For example, annealing 3D memory cell structures with heat is known. While advantageous for memory cell structures, heat may adversely affect the operation of logic circuits.

Disclosure of Invention

In summary, examples of the present technology relate to an integrated memory module comprising: a first semiconductor die; a second semiconductor die flip chip bonded to the primary planar surface of the first semiconductor die at an edge of the primary planar surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die; wherein the first and second coupled semiconductor die are configured together as an integrated flash memory.

In another example, the present technology relates to a semiconductor device comprising: a substrate; a first integrated memory module secured to a substrate, comprising: a first semiconductor die including a surface having a plurality of die bond pads; a second semiconductor die bonded to a surface of the first semiconductor die adjacent to the plurality of die bond pads; wherein the first and second coupled semiconductor die are configured together as an integrated flash memory; and a third semiconductor die mounted on a surface of the first semiconductor die adjacent to the second semiconductor die.

In other examples, the present technology relates to a semiconductor device comprising: a substrate; a first integrated memory module secured to a substrate, comprising: a first semiconductor die including a surface having a plurality of bond pads adjacent a first edge of the first semiconductor die and a second edge adjacent the first edge; a second semiconductor die bonded to a surface of the first semiconductor die at a second edge; wherein the first and second coupled semiconductor die are configured together as an integrated flash memory; and a third semiconductor die mounted on a surface of the first semiconductor die adjacent to the second semiconductor die.

In another example, the present technology relates to an integrated memory module comprising: a substrate; a first integrated memory module secured to a substrate, comprising: a first semiconductor die including a surface having a plurality of bond pads adjacent a first edge of the first semiconductor die; a second semiconductor die bonded to a surface of the first semiconductor die at a central portion of the surface of the first semiconductor die; wherein the first and second coupled semiconductor die are configured together as an integrated flash memory; and a third semiconductor die including a film layer on a surface of the third semiconductor die, the third semiconductor die mounted to the surface of the first semiconductor die, and the second semiconductor die embedded within the film layer.

In other examples, the present technology relates to an integrated memory module comprising: a first semiconductor die comprising a memory component; a second semiconductor die comprising a control component, the second semiconductor die flip chip bonded to the primary planar surface of the first semiconductor die at an edge of the primary planar surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die; wherein the first and second coupled semiconductor die are configured together as an integrated flash memory.

Drawings

Fig. 1 is a flow chart of forming a semiconductor device in accordance with embodiments of the present technique.

Fig. 2 is a top view of a first major surface of a first semiconductor wafer and a first semiconductor die therefrom in accordance with embodiments of the present technology.

Fig. 3 is a top view of a first major surface of a second semiconductor wafer and a second semiconductor die therefrom in accordance with embodiments of the present technique.

Fig. 4-6 are edge views of a second semiconductor die during fabrication in accordance with embodiments of the present technology.

Fig. 7 and 7A are edge views of a second semiconductor die including connective metal bumps in accordance with an alternative embodiment of the present technology.

Fig. 8 is a top view illustrating assembly of a first semiconductor die and a second semiconductor die into an integrated memory module, in accordance with embodiments of the present technology.

Figure 9 is a top view of a completed integrated memory module, in accordance with embodiments of the present technique.

Fig. 10 and 11 are cross-sectional edge and edge views illustrating an integrated memory module in accordance with embodiments of the present technology.

FIG. 12 is a functional block diagram of an integrated memory module coupled to a host device via a controller, in accordance with embodiments of the present technique.

Figures 13-21 are perspective, top, and edge views of a semiconductor device including a number of stacked integrated memory modules during fabrication, in accordance with embodiments of the present technique.

Figures 22-25 are perspective and edge views of a semiconductor device including several stacked integrated memory modules during fabrication, in accordance with an alternative embodiment of the present technique.

Figure 26 is an edge view of a semiconductor device including several stacked integrated memory modules during fabrication, in accordance with other alternative embodiments of the present technique.

Figure 27 is an edge view of a semiconductor device including a number of stacked integrated memory modules during fabrication, in accordance with another alternative embodiment of the present technique.

Figure 28 is an edge view during fabrication of a semiconductor device including several stacked integrated memory modules in accordance with other alternative embodiments of the present technique.

Detailed Description

The present technology will now be described with reference to the accompanying drawings, which in embodiments relate to a semiconductor device including a stacked integrated memory module. Each integrated memory module may include a pair of semiconductor die that operate together as a single, integrated flash memory. The division of flash memory functions between the pair of die in the module may vary in embodiments, but in one example, a first die may include an array of memory cells and a second die may include logic circuitry such as a CMOS integrated circuit.

In an embodiment, the second semiconductor die of the integrated memory module may be smaller than the first semiconductor die and may be flip-chip bonded to a surface of the first semiconductor die. In one embodiment, a second semiconductor die can be bonded to a first semiconductor die along an edge of the first die. In such embodiments, the integrated memory modules may be stacked in an offset, staggered configuration such that the first die may be directly stacked on top of each other, leaving the second die exposed on the edges of the first die. In another embodiment, the second die can be bonded to a central portion of the first die. In such embodiments, the first die may include a FOD (film on die) on a bottom surface of the first die such that the second die is embedded within a film of the first die in the next higher integrated memory module.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without such specific details.

The terms "top" and "bottom", "upper" and "lower" and "vertical" and "horizontal" and forms thereof as may be used herein are exemplary only and for purposes of illustration only and are not intended to limit the description of the technology as the listed items may be interchanged in position and orientation. Further, as used herein, the terms "substantially" and/or "about" mean that the specified dimensions or parameters may vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ± 0.25% of a given dimension.

Embodiments of the present technique will now be explained with reference to the flowchart of fig. 1 and the views of fig. 2-28. In step 200, the first semiconductor wafer 100 may be processed into a number of first semiconductor die 102, as shown in fig. 2. The first semiconductor wafer 100 may start with an ingot of wafer material, which may be single crystal silicon grown according to the czochralski (cz) method or the zone-melting (FZ) process. However, the first wafer 100 may be formed of other materials and by other processes in other embodiments.

The semiconductor wafer 100 may be cut from an ingot and polished on a first major surface 104 and a second major surface (not shown) opposite the surface 104 to provide a smooth surface. The first major surface 104 can be subjected to various processing steps to divide the wafer 100 into the respective first semiconductor die 102 and form integrated circuits of the respective first semiconductor die 102 on and/or in the first major surface 104. These various processing steps may include a metallization step that deposits metal contacts including die bond pads 106 and flip chip bond pads 108 exposed on the first major surface 104. The metallization step may also include depositing metal interconnect layers and vias within the wafer. These metal interconnect layers and vias may be provided to transmit signals to and from the integrated circuit and to provide structural support to the integrated circuit, as explained below with respect to fig. 10.

The number of first semiconductor die 102 shown on the wafer 100 in fig. 2 is for illustration purposes, and the wafer 100 may include more first semiconductor die 102 than shown in other embodiments. Similarly, the number of bond pads 106, 108 on the first semiconductor die 102 is shown for illustration purposes, and each first die 102 may include more bond pads 106, 108 than shown in other embodiments.

In one embodiment, the first semiconductor die 102 may be processed to include integrated circuit memory cells, such as one or more 3D stacked memory cell arrays having strings of NAND memory. The first semiconductor die 102 may include other and/or additional circuitry in other embodiments, as explained below.

Before, after, or in parallel with the formation of the first semiconductor die on the wafer 100, the second semiconductor wafer 110 may be processed into a number of second semiconductor die 112 in steps 202 and 204, as shown in fig. 3. The semiconductor wafer 110 may start with an ingot of single crystal silicon grown according to a CZ, FZ or other process. The second semiconductor wafer 110 may be diced and polished on a first major surface 114 and a second major surface (not shown) opposite the surface 114 to provide a smooth surface. The first major surface 114 can be subjected to various processing steps to divide the second wafer 110 into the respective second semiconductor die 112 and form integrated circuits of the respective second semiconductor die 112 on and/or in the first major surface 114. In that

The number of second semiconductor die 112 shown on the wafer 110 in fig. 3 is for illustration purposes, and the wafer 110 may include more second semiconductor die 112 than shown in other embodiments.

In one embodiment, the second semiconductor die 112 may be processed to include integrated logic 115 (fig. 4) configured to control read/write operations of one or more integrated memory cell arrays. The logic circuit may be fabricated using CMOS technology, but in other embodiments the logic circuit may be fabricated using other technologies. As explained below, the second semiconductor die 112 may include other and/or additional circuitry in other embodiments. Each logic circuit 115 may be electrically coupled to a metal pad 116 on the upper surface of die 112 by a metal interconnect layer and/or via.

As described below, metal pads 116 of logic circuit 115 are electrically coupled to bond pads 108 on first die 102. In an embodiment, this is done in step 204 using a redistribution layer to reposition or redistribute the position of the metal pads 116 on the second die 112 to a pattern that matches the pattern of the bond pads 108 on the first die 102. Such a redistribution layer (RDL)117 is shown in fig. 5. The pattern of the RDL 117 shown in fig. 5 is by way of example only and may vary in other embodiments. It is contemplated that the metal pads 116 on the second semiconductor die 116 are arranged in a pattern that needs to match the contact pads 108 on the first semiconductor die 102. In this case, RDL 117 may be omitted.

The pattern of bumps 118 may be formed on pads on the upper surface of RDL 117, as shown in fig. 6. Bumps 118 may be formed by various techniques including, for example, by stud bumping or using micro bumps on second wafer 110. Bumps 118 may be formed from a variety of materials including, for example, Cu-Sn, Pb-Sn, Au, alloys thereof, or other solder materials and relatively high melting point metals. Bumps 118 are provided in a pattern that matches the pattern of bond pads 108 on first die 102. In embodiments, the spacing between bumps 118 may vary between 5 microns (μm) and 50 μm, although in other embodiments the spacing may be smaller or larger.

In embodiments, the tab 118 may be a cylindrical post or a spherical ball. However, in other embodiments, the tab 118 may be tapered, as shown in fig. 7 and the enlarged view of fig. 7A. The tapered projections 118 may have straight sidewalls to form a true cone, or as shown, sidewalls with a concave portion at the base transitioning to a convex portion at the tip. The tapered bumps 118 may be deposited on the RDL pads by first depositing a Ti/Cu seed layer on the pads on the upper surface of the RDL 117. Next, an undercut hole may be formed by photolithography using a resist pattern over the seed layer. The undercut hole in the resist film may then be filled with a bump material, for example, in an electroplating process. The photoresist and seed layer may then be removed using one or more solvents to leave the tapered bumps 118.

In an embodiment, the tapered bumps 118 may have a base diameter d of 8-10 μm₁Tip diameter d of 2-3 μm₂And a height h of 8-9 μm. However, each of these dimensions may vary proportionally and disproportionately from one another in other embodiments. The spacing between the tapered bumps may be about 20 μm, but this spacing may vary in other embodiments. As explained below, the tapered bumps 118 have certain advantages with respect to shear strength when the tapered bumps of the die 112 are ultrasonically bonded to the pads 108 of the die 102. However, as mentioned, the tab 118 may be post, spherical, or otherwise shaped in other embodiments. The number of bumps 118 on the second semiconductor die 112 shown in fig. 3, 6, and 7 is for illustration purposes, and each second die 112 may include more bumps 118 than shown in other embodiments.

In step 206, the first semiconductor die 102 diced from the wafer 100 and the second semiconductor die diced from the wafer 110 may be physically and electrically coupled to each other, as shown in fig. 8 and 9. In an embodiment, the second semiconductor die 112 can be mounted to the primary planar surface of the first semiconductor die 102 at an edge of the primary planar surface. As mentioned, in one embodiment, the pattern of the flip chip bond pads 108 on the first semiconductor die 102 can match the pattern of the bumps 118 on the second semiconductor die 112, as shown in fig. 8. The particular pattern of bond pads 108 and bumps 118 shown in fig. 8 is by way of example only and may vary in other embodiments.

To is coming toWith the first die 102 and the second die 102 secured together, the second semiconductor die 112 can be flipped over and heat and pressure can be used to reflow the bumps 118 at each pad interface, thereby physically and electrically coupling the respective bumps 118 to the respective bond pads 108. In particular, in embodiments, the bump 118 may be electrically and physically coupled to the bond pad 108 using a thermo-compression technique, in which case the bump 118 is pressed against the bond pad 108 at an elevated temperature for a period of time to reflow the bump, which is diffused or otherwise bonded to the bond pad 108. In other embodiments, ultrasonic vibrations may be applied to the bumps 118 in addition to or in lieu of the elevated temperature to facilitate bonding of the bumps 118 to the pads 108. In an embodiment, the tapered bumps 118 may bond better than other types of bumps 118 (i.e., better resistance to shear forces between the bumps 118 and the pads 108) because the ultrasonic welding and/or pressure is concentrated at the small diameter (d in fig. 7A)₂) Above the tip of (a). However, as mentioned, the bumps 118 may have various shapes in different embodiments.

As mentioned, the first semiconductor die 102 and the second semiconductor die 112 may be coupled together after they are diced from their respective wafers 100 and 110. However, in other embodiments, the second semiconductor die 112 may be affixed to the first semiconductor die 102 prior to dicing the first semiconductor die 102 from the wafer 100. After coupling the first die 102 and the second die 102, the first die 102 is diced from the wafer 100.

Once coupled to each other, the first semiconductor die 102 and the second semiconductor die 112 together form an integrated memory module 120, as shown in fig. 9. In accordance with aspects of the present technique, the integrated memory module 120 is a single, complete integrated flash memory, such as a BiCS flash memory. Forming the integrated memory module 120 from two separate semiconductor die has several advantages over conventional memory die formed on a single die. For example, where the first die 102 includes an array of memory cells, removing logic from the first die frees up valuable space for additional memory cells. For example, where the memory cells are configured as a hierarchical 3D memory stack, removing the logic circuitry allows for additional layers to be provided in the memory stack.

Furthermore, separating the memory cells and logic circuits into two separate wafers allows the manufacturing process of the two wafers to be customized and optimized for the particular integrated circuits formed on the respective wafers. For example, conventional processes for forming flash memory integrated circuits involve heating steps, which can be detrimental to CMOS logic circuits. This problem can be alleviated by fabricating the logic circuits on their own wafer.

Referring again to fig. 9, the second semiconductor die 112 of the integrated memory module 120 may be significantly smaller than the first semiconductor die 102. As such, the overall footprint of integrated memory module 120 may be uniquely determined by the footprint of first semiconductor die 102. That is, the size of the second semiconductor die 112 does not increase the footprint of the integrated memory module 120 or otherwise affect the footprint of the integrated memory module 120.

In the embodiment shown in fig. 8-9, the first semiconductor die 102 and the second semiconductor die 112 include a pattern of bond pads for flip chip bonding of the dies. It should be understood that the first semiconductor die 102 and the second semiconductor die 112 may be electrically coupled to each other using other schemes in other embodiments. In one such other embodiment, the first semiconductor die 102 and the second semiconductor die 112 can be electrically coupled to each other using through-silicon vias (TSVs). In another such embodiment, the first semiconductor die 102 and the second semiconductor die 112 can be wire bonded to each other. The flip chip bond pads 108 and bumps 118 may be omitted in such alternative embodiments.

Additional details related to the physical and electrical coupling of the first semiconductor die 102 and the second semiconductor die 112 will now be explained with reference to the cross-sectional edge view of fig. 10 and the edge view of fig. 11. The first semiconductor die 102 can include an array of integrated circuit memory cells 122 formed in and/or on a backing layer 124 within a chip area of the first semiconductor die 102. As mentioned, the memory cell array 122 may be formed as a 3D stacked memory structure having strings of memory cells formed as multiple layers. After forming memory cell array 122, multiple layers of metal interconnects 126 and vias 128 may be sequentially formed in a layer of dielectric film 130. The metal interconnects 126, vias 128, and dielectric film layer 130 may be formed one layer at a time using photolithography and thin film deposition processes, as are known in the art. The photolithography process may include, for example, pattern definition, plasma, chemical or dry etching, and polishing. The thin film deposition process may include, for example, sputtering and/or chemical vapor deposition. The metal interconnects 126 may be formed of various conductive metals including, for example, copper and copper alloys as are known in the art, and the vias 128 may be lined and/or filled with various conductive metals including, for example, tungsten, copper, and copper alloys as are known in the art.

A passivation layer 132 may be formed on top of the upper dielectric film layer 130. The passivation layer 132 may be etched to form the bond pads 106, 108. Each bond pad 106, 108 may include a contact layer 134 formed over a pad 136. Contact layer 134 may be formed, for example, of copper, aluminum, and alloys thereof, and liner 136 may be formed, for example, of a titanium/titanium nitride stack (such as Ti/TiN/Ti), as is known in the art, although these materials may vary in other embodiments. The bond pads 106, 108 (contact layer plus liner) may have a thickness of 720nm, although in other embodiments this thickness may be greater or less.

Metal interconnects 126 and vias 128 may be used to form conductive nodes 140 within the chip area as known in the art to transmit signals and voltages between die bond pads 108 and integrated circuit 122. The metal interconnects 126 may also be used to transmit signals between the contact pads 106 and the integrated circuit 122 and/or the second die 112. Thus, as explained below, signals, for example, from a memory controller, can be transmitted to/from the second semiconductor die 112 via the die bond pads 106, the metal interconnects 126, and the bond pads 108 on the first die 102. Signals may also be transmitted between the first die 102 and the second die 112 via the metal interconnects 126 and the bond pads 108 on the first die 102.

The metal interconnects 126 and vias 128 may also be used to form a seal ring 142 in the seal ring area as is known in the art. Seal ring 142 may surround integrated circuit 122 and conductive node 140 and provide mechanical support to avoid damage to integrated circuit 122 and conductive node 140, for example, during dicing of wafer 100.

As mentioned above, the second semiconductor die 112 may be formed in a similar manner to include an integrated circuit such as CMOS logic circuit 115. For the first die 102, the integrated circuit in the second die 112 may be electrically interconnected with the bumps 118 of the second die 112 via a frame of metal interconnects and vias, and the RDL 117 described above. The embodiment shown in fig. 10 includes tapered bumps 118, but other types of bumps may be used, including posts and spherical bumps.

Fig. 11 shows a more general edge view of an integrated memory module 120 including a second die 112 secured to a first die 102 by bumps 118. The number of bumps 118 shown in fig. 10 and 11 is for illustration purposes and will vary in other embodiments. Once the second die 112 is secured to the first die 102, the space between the first die and the second die may be underfilled with an epoxy or other resin or polymer 144. The underfill material 144 may be applied as a liquid, which then hardens into a solid layer. This underfill step protects the electrical connections between the first die 102 and the second die 112 and further secures the second die 112 to the first die 102. Various materials may be used as underfill material 144, but in an embodiment, it may be Hysol epoxy from Henkel corporation (which has offices in california, usa).

As mentioned, in an embodiment, the first semiconductor die 102 may include an array of memory cells and the second semiconductor die 112 may include control logic circuitry such that the integrated memory module 120 may function as a single, complete flash memory. In accordance with aspects of the present technique, the flash memory is bifurcated into two separate semiconductor die assembled together. Fig. 12 is a functional block diagram illustrating further details of an embodiment in which the first die includes an array of memory cells and the second die 112 includes logic circuitry.

The first die 102 of the integrated memory module 120 may include a memory structure 160 of memory cells, such as an array of memory cells, and read/write circuits 168. The second die 112 may include control logic 150. The memory structure 160 is addressable by word lines via a row decoder 164 and by bit lines via a column decoder 166. The read/write circuits 168 may include multiple sense blocks (sense circuits) that allow a page of memory cells to be read or programmed in parallel.

The plurality of memory elements in memory structure 160 may be configured such that they are connected in series or such that each element is individually accessible. As a non-limiting example, a flash memory system of NAND configuration (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a set of series-connected transistors including memory cells and select gate transistors.

A NAND memory array can be configured such that the array is made up of multiple strings of memory, where a string is made up of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, the memory elements of memory structure 160 may be configured such that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and the memory elements may be configured in other ways.

Memory structure 160 may be two-dimensional (2D) or three-dimensional (3D). Memory structure 160 may include one or more arrays of memory elements (also referred to as memory cells). The 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in x, y, and z directions, where the z direction is substantially perpendicular to a major surface of substrate 124, and the x and y directions are substantially parallel to the major surface of substrate 124, fig. 10).

The memory structure 160 on the first die 102 may be controlled by the control logic 150 on the second die 112. The control logic circuit 150 may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. Control circuitry 150 cooperates with the read/write circuits 168 to perform memory operations on the memory structure 160. In an embodiment, the control circuit 150 may include a state machine 152, an on-chip address decoder 154, and a power control module 156. The state machine 152 provides chip-level control of memory operations. Storage areas 153 may be provided to operate memory structure 160, such as different rows or other sets of programming parameters of memory cells. These programming parameters may include bit line voltages and verify voltages.

The on-chip address decoder 154 provides an address interface between that used by the host device or a memory controller (explained below) to the hardware address used by the decoders 164 and 166. The power control module 156 controls the power and voltages supplied to the word lines and bit lines during memory operations. Which may include drivers for 3D configured word line layers, source side select gates, drain side select gates, and source lines. The source side select gate is the gate transistor at the source end of the NAND string, and the drain side select gate is the transistor at the drain end of the NAND string.

In accordance with aspects of the present technique, the above-described components of the integrated memory module 120 branch into two separate semiconductor die 102 and 112, an example of which is shown in fig. 12. It should be understood, however, that the division of the above-described components between two different die 102, 112 may be different than that shown in fig. 12. Some or all of the components shown and described above as part of die 102 may be provided on die 112, while some or all of the components shown and described above as part of die 112 may be provided on die 102. In other embodiments, components of the attachment may be added to die 102 or die 112. In an embodiment, the control logic 150 may include the components shown in fig. 12 and described above. In other embodiments, all components except memory unit 160 may be considered one or more control logic circuits configured to perform the actions described herein. For example, one or more control logic circuits may include any one or combination of control circuit 150, state machine 152, decoder 154/164/166, power control module 156, sense blocks for read/write circuits, and the like.

Data and commands may be transferred to and from the integrated memory module 120 through the memory controller 170. Memory controller 170 may comprise, for example, an ASIC, and may be fabricated on a semiconductor die separate from die 102 and 112. In other embodiments, the memory controller 170 may be integrated into one of the die 102, 112, such as on the second semiconductor die 112. The memory controller 170 may include a processor, such as a microprocessor 170c, and storage devices (memory), such as a Read Only Memory (ROM)170a and a RAM 170 b. The RAM 170b may be, but is not limited to, SRAM and DRAM. The storage device includes code, such as an instruction set, and the processor is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, the processor may access code from a storage device region of the memory structure 160, such as a reserved region of memory cells in one or more word lines.

The code is used by the memory controller 170 to access the memory structure 160 for operations such as programming, reading, and erasing. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes the memory controller 170 and enables the memory controller to access the memory fabric 160 during boot or startup. Upon power up, the processor 170c retrieves boot code from the ROM 170a or storage area of the memory structure 160 for execution, and the boot code initializes system components and loads control code into the RAM 170 b. Once the control code is loaded into RAM 170b, it is executed by processor 170 c. The control code contains drivers to perform basic tasks such as controlling and allocating memory, prioritizing (prioritizing) instructions, and controlling input and output ports.

The memory controller 170 controls communication between the integrated memory module 120 and the host device 174. The host device may be, for example, a printed circuit board to which the integrated memory module 120 and/or the memory controller 162 is mounted. The host device may alternatively be a computing system. Commands and data are transferred between the host device 174 and the memory controller 170 via an interface (e.g., a data bus) 172 and between the memory controller and the integrated memory module 120 via lines 158. The interface 172 between the host device 174 and the memory controller 170 may include a peripheral component interconnect express (PCIe) bus, but the interface 172 is not limited to a PCIe bus.

Referring again to fig. 1, after the first die 102 and the second die 112 are formed and coupled to one another to form the integrated memory module 120, the memory module 120 may be tested in step 208 as is known, for example, with read/write and burn-in operations.

At step 212, two or more integrated memory modules 120 may be stacked on the substrate 180, as shown in the perspective views of fig. 13 and 14. The substrate may be any of a variety of chip carrier media containing conductive pads 182, 184, electrical traces, and vias to transfer data and commands between the stacked integrated memory module 120 and a host device, such as host device 174, as described above. Such chip carrier media may include, but is not limited to, a Printed Circuit Board (PCB), a lead frame, or a Tape Automated Bonding (TAB) tape. Passive components (not shown) may be mounted to the substrate before or after integrating the memory module 120. The passive components may include, for example, one or more capacitors, resistors, and/or inductors, although other components are contemplated.

As mentioned above with respect to fig. 10, a memory controller die 170, such as an ASIC, may also be mounted to the substrate 180 to control the exchange of information between the integrated memory module 120 and a host device. In an embodiment, the controller die 170 may be wire bonded to the substrate 180, although in other embodiments it may be connected by other methods.

In step 212, the first integrated memory module 120 may be mounted on the substrate 180, such as by a Die Attach Film (DAF) on a lower surface of the first die 102. Electrical connections in the form of wire bonds 185 may then be formed in step 214 between the contact pads 106 on the first die 102 and the first set of pads 182 on the substrate 180. The wirebonds 185 can be formed in a conventional manner, such as using ball bonds (ball bonds), although other types of bonds are contemplated. The wire bonds 185 may be formed of gold, a gold alloy, or other materials. The substrate 180 and the one or more wire-bonded integrated memory modules 120 may together form a semiconductor device 190. As shown in fig. 13 and described above, the second semiconductor die 112 can be mounted along an edge of the first semiconductor die 102 in the semiconductor device 190.

Steps 212 and 214 may be repeated (as indicated by the dashed lines in fig. 1) to add additional integrated circuit memory modules 120 to the semiconductor device 190. As shown in fig. 14 and 15, the second integrated memory module 120 may be mounted on top of the first integrated memory module 120, again using the DAF layer on the lower surface of the die 102 of the second integrated memory module 120. In accordance with aspects of the present technique, the second integrated memory modules 120 are mounted in a staggered, offset configuration.

In particular, the second integrated memory module 120 may be offset along the y-axis by a distance y' (fig. 15) relative to the first integrated memory module 120 to leave room for the wire bonds 185 on the bond pads 106. In embodiments, the distance y' may be in the range of 50 to 100 μm, although this distance may be smaller or larger in other embodiments. The second integrated memory module 120 can also be offset along the x-axis by a distance x' relative to the first integrated memory module 120 to leave space on the first semiconductor die 102 for the second semiconductor die 112 of the first integrated memory module 120. Thus, the first die 102 of the second integrated memory module 120 may be mounted directly on a surface of the first die 102 of the first integrated memory module 120, next to the second die 112 of the first integrated memory module 120. In embodiments, the distance x' may be in the range of 100 to 500 μm, although this distance may be smaller or larger in other embodiments.

The second integrated memory module 120 can be rotated 180 ° relative to the first integrated memory module 120 such that the die bond pads 106 of the second integrated memory module are positioned adjacent to the second set of pads 184 at the second edge of the substrate 180. Die bond pads 106 may be wire bonded to the second set of pads 184 using a second set of wire bonds 185. As shown in fig. 15, for example, the second semiconductor die 112 of the second integrated memory module 120 is also located on an opposite edge of the semiconductor device 190 from the second semiconductor die 112 of the first integrated memory module 120.

As shown in fig. 16 and 17, a third integrated memory module 120 may then be added to the semiconductor device 190. The third integrated memory module 120 may be mounted on top of the second integrated memory module 120, again using the DAF layer on the lower surface of the die 102 of the third integrated memory module 120. The third integrated memory module 120 may be offset along the y-axis by a distance y "(fig. 17) relative to the second integrated memory module 120 to leave room for the wire bonds 185 on the bond pads 106 of the second integrated memory module 120. The third integrated memory module 120 can also be offset along the x-axis by a distance x "relative to the second integrated memory module 120 to leave room for the second semiconductor die 112 at the edge of the second integrated memory module 120.

In an embodiment, the third integrated memory module 120 may be aligned directly over the first integrated memory module 120. That is, in an embodiment, distance y "may be the same as y 'but in the opposite direction, and distance x" may be the same as x' but in the opposite direction. It should be understood that the distances y 'and y "need not be the same as each other in other embodiments, and the distances x' and x" need not be the same as each other in other embodiments.

The first and third integrated memory modules 120 may be spaced apart from each other by a thickness of the DAF layer of the first semiconductor die and the second memory module 120. This spacing is large enough to leave room for the second semiconductor die 112 under the third integrated memory module 120. The third integrated memory module 120 may be wirebonded to the substrate 180 using wirebonds 185 between the bond pads 106 on the third integrated memory module and the first set of pads 182 on the substrate 180.

As shown in fig. 18 and 19, a fourth integrated memory module 120 may then be added to the semiconductor device 190. The fourth integrated memory module 120 may be mounted on top of the third integrated memory module 120, again using the DAF layer on the lower surface of the die 102 of the fourth integrated memory module 120. The fourth integrated memory module 120 can be offset staggered relative to the third integrated memory module 120 so as to be directly over the second integrated memory module, leaving room for the second semiconductor die 112 at the edge of the third integrated memory module 120. The fourth integrated memory module 120 may be wirebonded to the substrate 180 using wirebonds 185 between the bond pads 106 on the fourth integrated memory module and the second set of pads 184 on the substrate 180.

The integrated memory modules 120 may be mounted on top of each other in the z-direction in the above-described alternating offset configuration to form a die stack 186 on the substrate 180, as shown in the side view of fig. 20. Although 4 memory modules 120 are shown, in different embodiments there may be 1, 2, 4, 8, 16, 32, 64, or other numbers of memory modules 120 in the stack 186.

In accordance with aspects of the present technique, the integrated memory modules 120 may be stacked one on top of the other in a manner such that the second die 112 of each module 120 does not add or otherwise affect the overall height required in the semiconductor device 190 of the die stack 186. In particular, the integrated memory modules 120 can be mounted in the stack 186 on top of each other in a staggered, offset configuration such that the first semiconductor die 102 of the memory module 120 can be secured directly underneath to the first semiconductor die 102 of the memory module 120.

The thickness of the second die 112 can be less than or equal to the thickness of the first die 102. Thus, the second die 112 of each module 120 does not increase the overall height required in the semiconductor device 190 of the die stack 186.

To prevent excessive stress on the overhang portion of each of the first die 102 (except for the die 102 directly on the substrate 180), spacers or solder posts 192 (as shown in fig. 20) may be provided under the overhang portion to provide support for the overhang portion. A single solder post 192 may be provided on each level. Alternatively, several such solder pillars 192 may be provided on each level (into the page of the figure), or one long spacer may be provided. The solder post 192 may be omitted in other embodiments.

After all integrated memory modules are added to the stack 186 and wire bonded, the semiconductor device 190 may be encapsulated in a molding compound 196 in step 216, and as shown in fig. 21. The molding compound 196 may comprise, for example, a solid epoxy resin, a phenolic resin, fused silica, crystalline silica, carbon black, and/or a metal hydroxide. Such molding materials are available, for example, from Sumitomo and Nitto-Denko (both headquarters in Japan). Other molding compounds from other manufacturers are contemplated. The molding compound may be applied by an FFT (Free Flow Thin) process or by other known processes, including by transfer molding or injection molding techniques.

In step 220, solder balls 198 (fig. 21) may optionally be secured to the contact pads 194 on the lower surface of the substrate 180 of the semiconductor device 190. Solder balls 198 may be used to electrically and mechanically couple semiconductor device 190 to host device 174 (fig. 12), such as a printed circuit board. In the case where semiconductor device 190 is to be used as an LGA package, solder balls 198 may be omitted.

In order to take advantage of economies of scale, a plurality of semiconductor devices 190 may be formed simultaneously on a panel of substrate 180. After forming and encapsulating the devices 190 on the panel, the devices 190 may be singulated from each other in step 224 to form a completed semiconductor device 190, as shown in fig. 21. The semiconductor devices 190 may be singulated by various cutting methods including sawing, water jet cutting, laser cutting, water guided laser cutting, dry media cutting, and diamond coated wire cutting. While a straight wire cut will define a generally rectangular or square shaped semiconductor device 190, it should be understood that the semiconductor device 190 may have shapes other than rectangular and square in other embodiments of the present technology.

In the above-described embodiment, the second semiconductor die 112 is mounted at the edge of the first semiconductor die 102 such that the integrated memory module 120 can be stacked one on top of the other without interference from the second semiconductor die 112. In other embodiments, the second semiconductor die 112 may be mounted centrally on top of the first semiconductor die 102. Such an embodiment will now be described with reference to fig. 22-25.

Fig. 22 is a perspective view of a semiconductor device 290 including an integrated memory module 120 mounted on a substrate 280. The integrated memory module 120 may include the first die 102 and the second die 112, which may be fabricated and secured to each other in accordance with any of the embodiments described above. However, in the embodiment of fig. 22, the second semiconductor die 112 may be mounted on a central portion (off edge) of the upper surface of the first semiconductor die 102. In an embodiment, the central portion of the die can be any position spaced at least the width of the second semiconductor die 112 from the edge of the first semiconductor die 102 and at least the width of the second semiconductor die 112 from the die bond pad 106. In other embodiments, the central portion may be the central 20% to 50% of the area of the first semiconductor die 102.

The substrate 280 in the embodiment of fig. 22 may be similar to the substrate 180 described above, but may include a single row of contact pads 182 (the contact pads 184 of the substrate 180 may be omitted). The substrate 280 may include a first row and a second row of contact pads 182, 184 in other embodiments. As described above, the integrated memory module 120 may be electrically interconnected to the substrate 280 described above, e.g., via wire bonds 185 between the pads 106 on the first die 102 and the pads 182 on the substrate 280.

According to this embodiment, the second integrated memory module 120 may be mounted directly on top of the first integrated memory module 120, as shown in fig. 23. To accommodate the second semiconductor die 112 and the wire bonds 185 on the first integrated memory module 120, a FOD (film on die) layer 250 may be provided on a lower surface of the first semiconductor die 102 of the second integrated memory module 120.

The FOD layer 250 may be an a-stage or B-stage thermoset resin (or some viscosity therebetween) that is stacked on the lower surface of the first semiconductor die 102 of the second integrated memory module 120. The second semiconductor die 112 and wire bonds 185 of the first integrated memory module 120 replace portions of the (display) FOD layer 250 when the second integrated memory module 120 is placed on top of the first integrated memory module 120. Thus, the second semiconductor die 112 and the wire bonds 25 of the first integrated memory module 120 are embedded within the FOD layer 250 of the second integrated memory module 120, and the second integrated memory module 120 may lie flat on top of the first integrated memory module 120, as shown in fig. 23.

In an embodiment, the FOD layer 250 may be a DAF layer formed on the lower surface of the first die 102 during wafer fabrication. In other embodiments, the FOD layer 250 may be applied to the lower surface of the first die 102 in addition to or instead of the DAF layer. Although not shown, the lower surface of the first semiconductor die 102 of the bottommost integrated memory module 120 shown in fig. 22 may also include a FOD layer 250.

The thickness of the FOD layer 250 can be slightly greater than the thickness of the second semiconductor die 112 and/or the height of the wire bonds 185 above the upper surface of the first die 102. In embodiments, the thickness of the FOD layer 250 may be in the range of 30 to 100 μm, although in other embodiments it may be thinner or thicker.

Upon mounting the second integrated memory module 120 on top of the first integrated memory module 120, the second integrated memory module 120 may be electrically interconnected to the substrate 280, e.g., via wire bonds 185 between the pads 106 on the first die 102 and the pads 182 on the substrate 280, as shown in fig. 23.

Additional integrated memory modules 120 (with FOD layers 250 on the lower surfaces of the first semiconductor die 102) may be added to the semiconductor device 290 and wire bonded as described above. Fig. 24 is a side view of a semiconductor device 290 including four integrated memory modules 120 stacked one on top of the other. As shown, the second semiconductor die 112 and the wire bonds 185 are embedded within the FOD layer 250 of the integrated memory module 120 mounted above. Although four layers are shown, it should be understood that the semiconductor device 290 may contain various numbers of stacked integrated memory modules 120, including, for example, 1, 2, 4, 8, 16, 32, and 64 integrated memory modules 120. Other numbers of integrated memory modules 120 may be provided in other embodiments.

After stacking and wire bonding all of the integrated memory modules one on top of the other, semiconductor device 290 may be encapsulated in a molding compound 196, as described above and shown in fig. 25. As mentioned, the molding compound 196 may comprise, for example, solid epoxy, phenolic, fused silica, crystalline silica, carbon black, and/or metal hydroxides. Additionally, solder balls 198 may optionally be secured to contact pads 194 on the lower surface of the substrate 280 of the semiconductor device 290.

Fig. 26 illustrates other embodiments of the present technology. The semiconductor device 290 of fig. 26 is the same as that shown in fig. 24, except that the integrated circuit modules are offset from each other in a stepped configuration so that the pads 106 remain uncovered by the above-mounted integrated memory module 120. As in fig. 24, the second semiconductor die 112 is embedded within the FOD layer 250 of the integrated memory module 120 mounted above. In this embodiment, all of the integrated memory modules 120 may be stacked on the substrate 280 and then wire bonded down the stack using wire bonds 185.

Fig. 27 illustrates other embodiments of the present technology, including a first group of stacked integrated memory modules 120 that are offset stepwise in a first direction, and a second group of stacked integrated memory modules 120 that are mounted on the first group and offset stepwise in a second direction opposite the first direction. The FOD layer 250 may be provided on the bottom of each integrated memory module 120 in the first and second sets of stacked offset integrated memory modules 120. To electrically connect the second (top) group of stacked integrated memory modules 120 with the substrate 280, an interposer layer 260 may be provided between the first and second groups of integrated memory modules 120. In this embodiment, the integrated memory modules 120 and interposer layer 260 in the first group may be stacked on a substrate 280 and then wire bonded down the stack using a wire bond 185. A second group of integrated memory modules 120 may then be stacked on the interposer layer 260 and then wire bonded down the stack using wire bonds 185. As shown, the wire bonds 185 between the interposer layer 260 and the topmost integrated memory module 120 in the first group may be embedded within the FOD layer 250 of the bottommost integrated memory module 120 of the second group. Alternatively, the portion of the FOD layer 250 on the interposer layer 260 (in the dashed line) may be omitted from under the interposer layer 250.

FIG. 27 shows four integrated memory modules 120 in each of the first and second groups. It should be understood that the number of integrated memory modules 120 in the first and/or second groups may vary in other embodiments.

Fig. 28 is an edge view of other embodiments of the present technology, including one or more spacers 270 around one or more edges of the second semiconductor die 112 of at least some of the integrated memory modules 120 in the semiconductor device 290. In particular, upon installation of the next higher integrated memory module 120, shear or other stresses may develop on the second semiconductor die 112 when embedded within the FOD layer 250. Spacers 270 may be provided to reduce and/or alleviate these stresses. As mentioned, the spacers 270 can be provided around a single edge, two edges, three edges, or all four edges of the second semiconductor die 112. The thickness of the spacers 270 can be slightly less than, equal to, or greater than the thickness of the second semiconductor die 112. The spacers 270 may be formed of an inert material, such as silicon dioxide, although other materials are possible.

Although not shown, the device 290 shown in the embodiment of fig. 26-28 may be encased in the molding compound 196 described above. Additionally, solder balls 198 may optionally be secured to the contact pads 194 on the lower surface of the substrate 280 of the semiconductor device 290 of fig. 26-28.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.