阅读说明：本技术 3d存储阵列中的改良浮栅和电介质层几何结构 (Improved floating gate and dielectric layer geometry in 3D memory arrays ) 是由 R·科瓦尔 S·贾扬提 H·桑达 M-W·郭 S·高达 K·帕拉特 于 2019-05-28 设计创作，主要内容包括：本发明描述了一种包括改良浮栅和电介质层几何结构的3D存储结构。在实施例中,存储单元包括沟道区和浮栅,其中,所述浮栅沿所述沟道区的方向的长度显著长于所述浮栅沿所述沟道区的正交方向的长度。与所述浮栅相邻的控制栅沿所述沟道区的所述方向延伸的长度至少与所述控制栅沿所述沟道区的所述方向延伸的长度一样长,并且包括朝向所述控制栅延伸离开所述沟道区的锥形边缘。在实施例中,设置在所述控制栅和所述浮栅之间的电介质层可以沿所述浮栅跟随所述锥形边缘,并且在靠近所述浮栅处形成分立区,以至少部分地使所述浮栅与相邻存储单元绝缘。还公开并要求保护了其它实施例。(A3D memory structure including improved floating gate and dielectric layer geometries is described. In an embodiment, a memory cell includes a channel region and a floating gate, wherein a length of the floating gate in a direction of the channel region is substantially longer than a length of the floating gate in an orthogonal direction of the channel region. A control gate adjacent to the floating gate extends in the direction of the channel region for a length at least as long as the control gate extends in the direction of the channel region and includes a tapered edge extending away from the channel region toward the control gate. In an embodiment, a dielectric layer disposed between the control gate and the floating gate may follow the tapered edge along the floating gate and form discrete regions proximate to the floating gate to at least partially insulate the floating gate from adjacent memory cells. Other embodiments are also disclosed and claimed.)

1. A memory device comprising a plurality of memory cells, wherein at least one of the memory cells comprises:

a channel region;

a floating gate adjacent to the channel region along a first side, wherein a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction of the channel region;

a control gate adjacent to the floating gate along a second, opposite side of the floating gate, wherein a length of the floating gate extending in the direction of the channel region is at least as long as a length of the control gate extending in the direction of the channel region, and the floating gate comprises a tapered edge extending away from the channel region towards the control gate; and

a dielectric layer disposed between the control gate and the floating gate, wherein the dielectric layer follows the tapered edge along the floating gate and forms discrete regions proximate to the floating gate to at least partially insulate the floating gate from adjacent memory cells.

2. The memory device of claim 1, wherein the plurality of memory cells comprise vertical 3D NAND strings of coupled memory cells in the direction of the channel region, and the dielectric layer forms a separate region for each memory cell.

3. The memory device of claim 1, wherein the dielectric layer comprises an intermediate dielectric layer of a multi-layer inter-poly dielectric (IPD) region that follows the tapered edge and is proximate to the floating gate.

4. The storage device of claim 3, wherein the intermediate dielectric layer comprises a material having a higher dielectric constant than silicon oxide and the IPD region comprises two oxide films, each oxide film disposed on opposite sides of the intermediate dielectric layer.

5. The memory device of claim 4, wherein the intermediate dielectric layer comprises silicon nitride.

6. The storage device of claim 3, further comprising a barrier layer comprising an insulator material disposed between the IPD region and the floating gate.

7. The memory device of claim 6, wherein the blocking layer is in direct contact with the floating gate and comprises silicon nitride.

8. The memory device of claim 1, wherein the channel region comprises a semiconductor pillar comprising silicon oxide and comprising a polysilicon liner along a length of the semiconductor pillar.

9. The memory device of claim 1, wherein the tapered edge narrows the floating gate toward the control gate.

10. A system, comprising:

a processor; and

a memory coupled with the processor, wherein the memory comprises a 3D stacked memory array, the 3D stacked memory array comprising a plurality of memory cells, wherein the plurality of memory cells comprises:

a plurality of floating gates adjacent to a channel region, wherein a length of one or more of the floating gates in a direction of the channel region is substantially longer than a length in an orthogonal direction of the channel region;

a plurality of control gates, each control gate adjacent to a corresponding floating gate of the plurality of floating gates, wherein a length that an adjacent control gate extends in the direction of the channel region is at least as long as a length that the corresponding floating gate extends in the direction of the channel region, and the corresponding floating gate comprises a tapered edge that extends away from the channel region towards the adjacent control gate; and

a dielectric layer disposed between one or more of the plurality of control gates and one or more of the corresponding floating gates and following the tapered edge along the one or more corresponding floating gates and forming a discrete region proximate the one or more corresponding floating gates to assist in insulating the one or more corresponding floating gates from adjacent memory cells.

11. The system of claim 10, wherein the dielectric layer comprises an intermediate dielectric layer of a multi-layer inter-poly dielectric (IPD) region proximate to the one or more corresponding floating gates.

12. The system of claim 11, further comprising a barrier layer film disposed between the multi-layer IPD region and the one or more corresponding floating gates and forming a discrete barrier layer for a corresponding memory cell.

13. The system of claim 10, wherein the plurality of memory cells comprises vertical 3D NAND strings and the dielectric layer insulates a memory cell of the plurality of memory cells from a next memory cell of the vertical 3D NAND strings.

14. The system of claim 10, wherein the channel region comprises a portion of a polysilicon pillar having a substantially circular cross-section.

15. The system of claim 13, wherein the system comprises a mobile computing device and further comprises at least one of:

a display communicatively coupled to the processor; or

A battery coupled to the processor.

16. A method of manufacturing a memory device, comprising:

forming a channel region in a substrate;

forming a plurality of control gates adjacent to the channel region;

forming a corresponding plurality of floating gates adjacent to the plurality of control gates, each floating gate extending in a direction of the channel region as long as the corresponding control gate extends in the direction of the channel region; and

forming a dielectric layer disposed between the plurality of control gates and the plurality of floating gates, wherein the dielectric layer follows tapered edges along one or more of the floating gates and forms discrete regions proximate to the one or more floating gates to assist in insulating a memory cell including the one or more floating gates and the corresponding control gate, and wherein a length of the floating gate in a direction of the channel region is substantially longer than a length of the floating gate in an orthogonal direction of the channel region.

17. The method of claim 16, further comprising forming the substrate by depositing alternating layers of conductors and insulators to form a stack of alternating conductor and insulator layers.

18. The method of claim 17, wherein forming the channel region in the substrate comprises anisotropically etching a cylindrical hole through the stack of alternating conductor and insulator layers.

19. The method of claim 18, wherein forming the plurality of control gates adjacent to the channel region comprises: isotropically etching the conductor layers in the stack of alternating conductor and insulator layers to create a plurality of pocket regions.

20. The method of claim 19, wherein forming the dielectric layer comprises forming a multi-layer dielectric over the plurality of pocket regions.

21. The method of claim 20, wherein forming the multi-layer dielectric comprises:

growing or depositing a first layer of the multi-layer dielectric comprising an oxide over a bottom region of each of the plurality of pocket regions;

growing or depositing a second layer of the multilayer dielectric comprising silicon nitride over a surface of the substrate comprising each of the plurality of pocket regions;

growing or depositing a sacrificial protective layer over the second layer; and

the sacrificial protective layer is subjected to an etching process to leave a portion of the sacrificial protective layer in a bottom of the cavity region.

22. The method of claim 21, further comprising selectively oxidizing or etching portions of the silicon nitride layer to form the tapered edges.

23. The method of claim 21, further comprising substantially isolating each of one or more control gates and the multilayer dielectric of a corresponding floating gate from adjacent control gates and floating gates.

24. The method of claim 23, wherein substantially isolating each of one or more control gates and the multilayer dielectric of a corresponding floating gate from each of the other plurality of control gates and floating gates comprises:

removing the sacrificial protection layer;

removing portions of the second layer of the multi-layer dielectric covering the insulator layer between each of one or more of the plurality of control gates; and

growing a third layer of the multi-layer dielectric to substantially insulate the silicon nitride layer.

25. The method of claim 23, further comprising depositing additional layers over the multilayer dielectric and over alternating layers of both conductors and insulators, and wherein the additional layers comprise atomic layer deposition of silicon nitride.

Technical Field

Embodiments of the present disclosure relate generally to the field of Integrated Circuits (ICs) and, more particularly, to techniques for fabricating non-volatile memory devices.

Background

A typical flash memory storage device may include a memory array comprising a large number of non-volatile memory cells arranged in rows and columns. In recent years, various forms (e.g., NAND, cross-point, etc.) of vertical memories, such as three-dimensional (3D) memories, have been developed. A 3D flash memory storage array may include a plurality of memory cells stacked on top of each other to form a vertical NAND string. In a floating gate flash memory cell, a conductive floating gate may be placed between the control gate and the channel of the transistor. The individual memory cells of a vertical NAND string may be on different layers arranged around a body extending outward from the substrate, with a conductive floating gate (charge storage region) lying on a plane similar or identical to the control gate extending horizontally outward from the body.

Drawings

The embodiments can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. For ease of description, like reference numerals designate like structural elements. Embodiments are shown by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Fig. 1A-1F are side and top cross-sectional views of one or more memory cells with improved floating gate and dielectric layer geometries according to embodiments of the present disclosure.

FIG. 2 is a flow chart describing a process associated with forming one or more of the memory cells of FIGS. 1A-1F according to an embodiment of the present disclosure.

Fig. 3A-3O schematically illustrate exemplary perspective and cross-sectional side views showing different stages of forming one or more memory cells as described in fig. 2, according to an embodiment of the disclosure.

Fig. 4A and 4B illustrate side and top cross-sectional views of a memory cell having improved floating gate and dielectric layer geometries, according to another embodiment of the present disclosure.

Fig. 4C-4C5 schematically illustrate exemplary cross-sectional side views of a memory structure showing different stages of forming one or more memory cells as described in connection with fig. 4A and 4B, according to various embodiments of the disclosure.

Figures 5A-5C illustrate additional embodiments of memory structures including one or more memory cells having a plano-concave curvature of a floating gate according to another embodiment of the present disclosure.

Fig. 6A-6C illustrate an embodiment of a memory structure including one or more memory cells having a concave curvature of a control gate in accordance with another embodiment of the present disclosure.

7A-7C2 illustrate embodiments of a memory structure including one or more memory cells in which the length of the floating gate can be greater than the length of the control gate in accordance with another embodiment of the present disclosure.

Fig. 8 illustrates an exemplary computing device including a memory structure with one or more memory cells having a modified floating gate and dielectric geometry in accordance with various embodiments of the present disclosure.

Detailed Description

In a memory device, a memory structure or array is described that includes one or more memory cells having a modified floating gate and dielectric layer geometry, according to an embodiment. In an embodiment, a memory cell includes a channel region, a floating gate, and an adjacent control gate. In an embodiment, the length of the floating gate in the direction of the channel region is significantly longer than the length of the floating gate in the orthogonal direction of the channel region. In an embodiment, the floating gate includes tapered edges extending away from the channel region towards the control gate. In an embodiment, the memory cell further comprises a dielectric layer disposed between the floating gate and the adjacent control gate. Further, in embodiments, the dielectric layer may follow the tapered edges along the floating gate, and may form discrete regions proximate to the floating gate to at least partially insulate the floating gate from adjacent memory cells. In an embodiment, the memory array may comprise, for example, a 3D NAND vertical memory array.

In the following description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. It will be apparent, however, to one skilled in the art that embodiments of the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that the embodiments of the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

For the purposes of this disclosure, the phrase "a and/or B" means (a), (B), (a) or (B) or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

The description may use perspective-based descriptions, e.g., top/bottom, inside/outside, above/below, etc. Such descriptions are merely used to facilitate the discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

The description may use the phrase "in an embodiment," which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with … …" may be used herein along with its derivatives. "coupled" may mean one or more of the following meanings. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.

Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some instances, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, it is not necessary that these operations be performed in the order presented.

Fig. 1A and 1B show a side cross-sectional view and a top cross-sectional view, respectively, of a memory cell 100 having improved floating gate and dielectric layer geometries, according to an embodiment. Line 150A of fig. 1A shows the location of the cross-sectional view of fig. 1B, and line 150B of fig. 1B shows the location of the cross-sectional view of fig. 1A. In embodiments, a channel including a channel region extends from a substrate, which may include a base wafer or another structure, onto which various materials may be deposited, grown, or otherwise disposed in various patterns, layers, and thicknesses using various processes to create circuitry for a memory device. Accordingly, the memory cell 100 may be formed of a columnar structure ("pillar") having a substantially circular cross-section as shown in fig. 1B. In embodiments, the pillars may be formed of a semiconductor material, which may be a polysilicon material in some embodiments. In various embodiments, the pillars may be formed from materials such as doped crystalline silicon, gallium arsenide, germanium, or other semiconductors. In an embodiment, a polysilicon liner may be included along the length of the pillar. In an embodiment, the channel or channel region may be shared among multiple memory cells, where an individual memory cell 100 uses a portion of the pillar for its channel region.

Accordingly, fig. 1A shows a memory cell 100 comprising a channel region 103, a floating gate 105, and a control gate 108, the floating gate 105 being adjacent to the channel region 103 along a first side 105a of the floating gate 105, the control gate 108 being along an opposite second side 105b of the floating gate 105. In an embodiment, the floating gate 105 and the control gate 108 may comprise a conductive material, such as polysilicon. In an embodiment, a multi-layer dielectric or inter-poly dielectric (IPD) region 109 is disposed between floating gate 105 and control gate 108. In an embodiment, the IPD region 109 may include a first IPD layer 109a, a second IPD layer 109b and a third IPD layer 109 c. In an embodiment, the first and third IPD layers 109a and 109c may each be disposed on opposite sides of the second IPD layer 109b, and the second IPD layer 109b may be an intermediate or second dielectric layer. In an embodiment, for example, the intermediate dielectric layer is made of a material having a higher dielectric constant than the first and third IPD layers 109a and 109 c. For example, the first and third IPD layers 109a and 109c may include a silicon oxide layer, and the second IPD layer 109b may be made of silicon nitride or another high-dielectric-constant insulator. In an embodiment, and as discussed in more detail in connection with fig. 1E, a barrier layer 115 is disposed between IPD region 109 and floating gate 105.

In an embodiment, the channel region 103 may include a channel liner or channel semiconductor film 111, and the channel semiconductor film 111 may include a semiconductor material such as polysilicon and may be included adjacent to the tunnel dielectric layer 112. In an embodiment, tunnel dielectric layer 112 may comprise any suitable dielectric material, and typically may comprise silicon oxide. In an embodiment, the pillars may include trench fills, which may include a dielectric material such as silicon oxide.

1C, 1D, and 1E illustrate side cross-sectional views of the memory cell 100 of FIGS. 1A and 1B, according to some embodiments. In an embodiment, fig. 1C, 1D, and 1E illustrate features of improved floating gate and dielectric layer geometries that may contribute to improved device performance and reliability of the memory cell 100. In embodiments, fig. 1C, 1D, and 1E include the same or similar elements as described in fig. 1A, and thus only certain elements are re-described for clarity. In an embodiment, as introduced above, the memory cell 100 includes a floating gate 105 adjacent to the channel region 103 along a first side 105a and a control gate 108 adjacent to the floating gate 105 along an opposite second side 105b of the floating gate 105.

In the embodiment of fig. 1C, the modified floating gate geometry comprises a length 105L of the floating gate 105 that extends at least as long as a length 108L of the control gate 108 in the direction of the channel region 103. Furthermore, in embodiments, the length 105L of the floating gate 105 in the direction of the channel region 103 may be significantly greater than the length 105W in the orthogonal direction of the channel region 103.

In an embodiment, fig. 1D illustrates additional features of an improved floating gate geometry that may contribute to improved device performance and reliability of the memory cell 100. In an embodiment, floating gate 105 includes one or more tapered edges 105T extending away from channel region 103 towards control gate 108, as shown at arrow 105A. In an embodiment, tapered edge 105T may narrow the floating gate towards the control gate. In an embodiment, also as indicated by arrow 105A, one or more tapered edges 109T of IPD region 109 may also extend away from channel region 103 towards control gate 108. Accordingly, in an embodiment, a portion of the intermediate or second dielectric layer 109b follows the tapered edge 109T near the floating gate 105. Further, according to various embodiments, the second IPD layer 109b may extend only about half way through the thickness of the floating gate 105 (e.g., refer to arrow 189), as indicated by arrow 199. Note that in the embodiment in fig. 1D, only one tapered edge 105T of the floating gate 105 is indicated, but both the floating gate 105 and the IPD region 109 (and including the second IPD layer 109b) have additional tapered edges on opposite sides.

Fig. 1E shows additional details of the barrier layer 115. In an embodiment, the barrier layer 115 may comprise an insulator material disposed between the IPD region 109 and the floating gate 105. In an embodiment, the barrier layer 115 is in direct contact with the floating gate 105 and may comprise silicon nitride. In an embodiment, the barrier layer 115 may be considered a fourth layer of the IPD region 109, and as can be seen in fig. 1E, the barrier layer 115 may form a discrete barrier for the memory cell 100 (i.e., the barrier layer is not shared by another proximate memory cell that may be located at a position along the channel or channel region 103). In an embodiment, barrier layer 115 may comprise silicon nitride, but in other embodiments may also comprise other dielectric materials having a higher dielectric constant than silicon oxide.

Fig. 1F shows a portion of memory structure 101 including a plurality of memory cells 100a, 100b, and 100 c. In an embodiment, memory structure 101 includes a vertical 3D NAND string of coupled memory cells (e.g., memory cells 100a, 100b, and 100c) in the direction of channel region 103. In an embodiment, a dielectric layer (e.g., an intermediate or second IPD layer 109b) may form a discrete region for each memory cell 100a, 100b or 100c adjacent to the floating gate 105 to at least partially insulate the floating gate 105 from adjacent memory cells. Accordingly, in an embodiment, the second IPD layer 109b is completely isolated and/or insulated by a substantially surrounding dielectric (e.g., silicon oxide) in each direction. In an embodiment, and as described above, the second IPD layer 109b may comprise silicon nitride, and may be separately defined for each of the plurality of memory cells 100a, 100b and 100c (as indicated between the memory cells 100a and 100b by the location of the second IPD layer 109b at location 100F and no second IPD layer 109b at location 100G).

Accordingly, in an embodiment, the memory structure includes a modified dielectric layer geometry in which an intermediate or second dielectric layer may be disposed between the control gate and the floating gate and follow the tapered edge 105T of the floating gate 105 to form discrete regions that at least partially insulate the floating gate from adjacent memory cells (e.g., one or more memory cells 100a, 100b, or 100 c). Note that the second IPD layer 109b of IPD region 109 is only indicated once in fig. 1F for memory cell 100a, but each of memory cells 100b and 100c includes a corresponding second IPD or dielectric layer to at least partially insulate the corresponding floating gate from adjacent memory cells.

Fig. 2 and 3A-3O are discussed together below. Figure 2 is a flow chart describing a process 200 for forming a memory structure with improved floating gate and dielectric layer geometry, according to an embodiment. Fig. 3A-3O show cross-sectional side and perspective views of various stages associated with process 200. In an embodiment, at block 201, the process 200 includes forming a channel region in a substrate. Accordingly, in an embodiment, fig. 3A shows a front view of the substrate 301 on the left side of fig. 3A and a perspective view of the substrate 301 on the right side. In an embodiment, forming substrate 301 may include depositing alternating layers of conductor 350 ("conductor layer 350" or "conductor 350") and insulator 375 ("insulator layer 375" or "insulator 375") to form a stack. In an embodiment, forming the stack may typically include Low Pressure Chemical Vapor Deposition (LPCVD) deposited polysilicon and silicon oxide.

Next, fig. 3B illustrates the formation of a channel or channel region 303 in the substrate 301 by anisotropically etching a cylindrical hole through the substrate 301 comprising a stack of alternating conductor layers 350 and insulator layers 375 for the embodiment. In an embodiment, the next block 203 of fig. 2 includes forming a plurality of control gates adjacent to the channel region 303. Accordingly, fig. 3C illustrates an embodiment wherein forming a plurality of control gates 308 may include isotropically etching conductor layers 350 in a stack of alternating conductor layers 350 and insulator layers 375 to create a plurality of pocket regions 360.

Returning to fig. 2, at block 205, process 200 includes forming a dielectric layer on the plurality of control gates. In an embodiment, a dielectric layer may be disposed between the plurality of control gates and the corresponding plurality of floating gates. In an embodiment, the dielectric layer may be formed in a manner that follows the tapered edge along one or more of the floating gates and in a manner that forms discrete regions proximate to the one or more floating gates. In an embodiment, the formation of the dielectric layer of block 205 in process 200 ("process") may be described in accordance with fig. 3D-3K, as described below. In an embodiment, forming the dielectric layer begins by forming a multi-layer dielectric (IPD region 109 of fig. 1) over the plurality of cavity regions 360. In an embodiment, this may include growing or depositing a first IPD layer 309a comprising, for example, silicon oxide, of a multi-layer dielectric over the bottom region of each of the plurality of pocket regions 360 as shown in fig. 3D. In an embodiment, the first IPD layer 309a may be silicon oxide grown from polysilicon.

Next, in an embodiment, as shown in fig. 3E, the process includes growing or depositing a second inter-dielectric layer of multi-layer dielectric or inter-poly dielectric (IPD) region 309b over a surface of each of the plurality of pocket regions 360. In an embodiment, depositing the second IPD layer 309b may comprise growing or depositing a silicon nitride layer.

Next, in an embodiment, as shown in fig. 3F, the process includes growing or depositing a sacrificial protective layer 333 over the second IPD layer 309 b. In an embodiment, accordingly, as shown next in fig. 3G, the process 200 may include performing an etching process on the sacrificial protection layer 333 to leave a portion of the sacrificial protection layer 333 in the bottom of the cavity region 360 over the second IPD layer 309 b. In an embodiment, a chemical agent that provides high etch removal selectivity may be used.

Next, in an embodiment, as shown in fig. 3H, the process includes selectively oxidizing or etching portions of the silicon nitride layer or second IPD layer 309b to form tapered edges 309T. In an embodiment, the formation of tapered features that improve the floating gate and dielectric layer geometry may begin at this stage.

Next, in an embodiment, as shown in fig. 3I, the remaining portion 335 of the sacrificial protective layer 333 may be removed, leaving the second IPD layer 309b with tapered edges 309T.

Next, in an embodiment, as shown in fig. 3J, the process includes removing portions of the second IPD layer 309b that cover the insulator layer 375 between one or more of the control gate regions 308. In an embodiment, the process may further include growing an additional layer 309a of a multi-layer dielectric to substantially insulate the second IPD layer 309 b.

Next, in an embodiment, as shown in fig. 3K, the process includes depositing an additional layer 315 ("barrier layer 315") over the multi-layer dielectric and over the alternating layers of both conductors 350 and insulators 375. In an embodiment, the additional layer 315 comprises Atomic Layer Deposition (ALD) of silicon nitride.

Accordingly, returning to FIG. 2, in an embodiment, the dielectric layer of block 205 of FIG. 2 has been substantially formed in connection with FIGS. 3D-3K.

Next, at block 207 of fig. 2, process 200 includes forming a corresponding plurality of floating gates adjacent to the plurality of control gates, each of the floating gates extending as long as the corresponding control gate. In some embodiments, the formation of the corresponding plurality of floating gates of block 207 may be described in terms of FIGS. 3L-3O.

Accordingly, in fig. 3L, the process includes depositing polysilicon material 305 that can become one or more floating gates. Next, in an embodiment, as shown in fig. 3M, a local etch back of the polysilicon material 305 may form discrete floating gates 305a, 305b, and 305 c. In an embodiment, as shown, barrier layer 315 between one or more floating gates 305a, 305b, and 305c may be removed (e.g.,

silicon nitride as indicated in fig. 3K) to achieve silicon nitride isolation between adjacent memory cells (e.g., 300a, 300b, and 300 c).

Next, in an embodiment, as shown in fig. 3N, a tunnel dielectric layer 312 is formed (see, e.g., tunnel dielectric layer 112). In an embodiment, silicon oxide may be grown on the polysilicon material of the floating gates 305a, 305b, and 305 c. In an embodiment, this stage of fig. 3N may substantially complete the isolation of barrier layer 315 (e.g., a silicon nitride layer) between adjacent memory cells (e.g., 300a, 300b, and 300 c).

Finally, next, in an embodiment, as shown in fig. 3O, a channel semiconductor film 311 is deposited. In an embodiment, dielectric fill 311a may then complete the formation of memory cells 300a, 300b, and 300 c. In an embodiment, the formation of the multiple control gates of block 207 is also complete.

Fig. 4A and 4B show side and top cross-sectional views, respectively, of a memory cell having improved floating gate and dielectric layer geometries, according to another embodiment. In an embodiment, memory cell 400 may be similar to memory cell 100 of fig. 1A and 1B and memory cells 300a, 300B, and 300c of fig. 3A-3O, except with an additional barrier layer adjacent to the control gate. In an embodiment, the additional barrier layer may be considered as a fifth IPD layer. Accordingly, in an embodiment, line 450A of fig. 4A illustrates the location of the cross-sectional view of fig. 4B, and line 450B of fig. 4B illustrates the location of the cross-sectional view of fig. 4A.

Accordingly, fig. 4A and 4B illustrate a memory cell 400 including a channel region 403, the channel region 403 may include a channel semiconductor film 411 lined with a tunnel dielectric layer 412. In an embodiment, the memory cell 400 includes a floating gate 405, the floating gate 405 being adjacent to the channel region 403 on a first side of the floating gate 405, and the memory cell 400 further includes a control gate 408 along an opposing second side of the floating gate 405. In an embodiment, floating gate 405 and control gate 408 comprise a conductive material, such as polysilicon. In an embodiment, a multi-layer dielectric or inter-poly dielectric (IPD) region 409 may be disposed between floating gate 405 and control gate 408. Accordingly, in an embodiment, the IPD region 409 may include a first IPD layer 409a, an intermediate or second IPD layer 409b and a third IPD layer 409 c. In an embodiment, the second IPD layer 409b may be a dielectric layer 409b made of a material having a higher dielectric constant than the first and third IPD layers 409a and 409 c. In an embodiment, the first and third IPD layers 409a and 409c may include silicon oxide layers, and the second dielectric layer 409b may be made of silicon nitride or other high dielectric constant insulator. In an embodiment, a barrier layer (similar to barrier layer 115 of fig. 1) or a layer that can be considered a fourth IPD layer 415 is disposed adjacent to floating gate 405. In that

In the embodiment of fig. 4, a fifth IPD layer 409D may be provided adjacent to the control gate 408.

In an embodiment, the process of forming memory cell 400 may be similar to the process of forming one or more memory cells 100 as described in fig. 3A-3O, but modified to include additional stages including the addition of a fifth IPD layer. In an embodiment, fig. 4C-4C5, which may include depositing a fifth IPD layer (e.g., silicon nitride) and subsequent taper etching, may replace fig. 3D in fig. 3A-3O. In an embodiment, accordingly, in fig. 4C, forming the plurality of control gates 408 includes isotropically etching the conductor layers 450 in the stack of alternating conductor layers 450 and insulator layers 475 to create a plurality of pocket regions 460 in the substrate 401. In fig. 4C1, silicon nitride or another high dielectric constant insulator may be added by depositing layer 409D over substrate 401 including alternating conductor layers 450 and insulator layers 475. In an embodiment, in fig. 4C2, the process includes growing or depositing a sacrificial protective layer 433 over the layer 409D, which may become the fifth IPD layer. Accordingly, next, in an embodiment, as shown in fig. 4C3, the sacrificial protection layer 433 may be subjected to an etching process to leave a portion of the sacrificial protection layer 433 over the layer 409D and over the area where the control gate 408 will eventually be formed. In an embodiment, a chemical agent that provides high etch removal selectivity may be applied to the silicon nitride. Next, in an embodiment, as shown in fig. 4C4, layer 409D may be etched to maintain isolation between adjacent memory cells in the vertical direction. Accordingly, the layer 409D may disappear along the exposed surface of the substrate 401 in fig. 4C4, but still remain under the remaining portion of the sacrificial protective layer 433. In fig. 4C5, in an embodiment, the remaining portion of sacrificial protective layer 433 may be removed and a taper etch may be applied to layer 409D to form a fifth IPD layer.

Fig. 5A-5C illustrate additional embodiments of one or more memory cells including similar elements as described above in connection with fig. 1-4. Fig. 5 includes a memory structure 501, where memory structure 501 includes one or more memory cells 500a, 500b, and 500c, and memory cells 500a, 500b, and 500c include a floating gate 505, a control gate 508, and a channel region 503. In an embodiment, each of the memory cells 500a, 500B, and 500c may be similar to the memory cells shown in fig. 1A, 1B, and 4A, 4B, respectively; however, memory cells 500a, 500b, and 500c may include floating gates having a concave or plano-concave curvature (e.g., as shown by the plano-concave vertical surface 588 of floating gate 505). As shown in fig. 5A, the next formed films (e.g., channel semiconductor film 511 and tunnel dielectric layer 512) may also follow the topology of the plano-concave vertical surface 588 of the floating gate 505. Note that fig. 5B and 5C illustrate modifications to the stages of process 200 as depicted in fig. 3L and 3M. For example, similar to that depicted in fig. 3L, fig. 5A and 5B may include a local etch-back of the polysilicon material 505 p; however, the local etchback may include a plano-concave curvature. In an embodiment, fig. 5C illustrates an etch back of the polysilicon material 505p to form discrete floating gates.

Fig. 6A, 6B, and 6C illustrate additional embodiments of one or more memory cells. In an embodiment, memory cell structure 601 can include memory cell 600 having concave curvature 698 of control gate 608. In an embodiment, an inter-poly dielectric (IPD) region 609 may be disposed between floating gate 605 and control gate 608, and may also follow concave curvature 698. As shown, for an embodiment, the concave curvature 698 may be implemented with respect to a memory cell having a flat concave curvature of the floating gate (similar to the embodiment of fig. 5A-5C). In other embodiments, concave curvature 698 of control gate 608 can be implemented with respect to a memory cell that may not include a flat concave curvature of the floating gate (e.g., memory cell 100 of fig. 1A and 1B). Note that fig. 6B and 6C show modifications to the stages of the process as depicted in fig. 3B and 3C. For example, similar to that depicted in FIG. 3B, FIG. 6B includes a front view of a memory cell structure 601, the memory cell structure 601 including alternating layers of conductor layers 650 and insulator layers 675. In an embodiment, fig. 6C illustrates an isotropic etch of the conductor layer 650 to create a plurality of pocket regions 660. In the illustrated embodiment, the plurality of pocket regions 660 can include a shape that can become the concave curvature 698 of the conductor layer 650 that can ultimately be included in the control gate 608.

7A-7C2 illustrate additional embodiments of one or more memory cells 700 in which the length L of the floating gate 705_FGMay be longer than the length L of the control gate 708_CGLong. In an embodiment, the dielectric portions of a similar deposition phase as described in connection with fig. 3A-3C may be modified to include first and second additional dielectric layers 778a, 778b on opposite sides of control gate 708. Accordingly, in fig. 7B, a memory substrate or structure 701 includes an alternating stack of conductor layers 750 and insulator layers 775 that includes first and second additional dielectric layers 778a, 778B that sandwich each of the conductor layers 750, according to various embodiments. FIG. 7C shows the anisotropic etching of a cylindrical hole through the substrate 701A channel region 703 is formed in the substrate 701. Next, fig. 7C1 and 7C2 illustrate embodiments in which forming the plurality of control gates 708 includes isotropically etching the conductor layer 750 and the first and second additional dielectric layers 778a and 778b to create a plurality of pocket regions 760. In an embodiment, the embodiments may be associated with a method described in connection with U.S. patent No.8,878,279, which is incorporated herein by reference.

Note that various operations of process 200 and/or various operations as additionally described in connection with fig. 4-7 are described as multiple discrete operations in a manner that is most helpful in understanding the claimed subject matter. The order of description should not be construed as to imply that these operations are necessarily order dependent. It is to be understood that the order of the operations associated with the processes may be varied and/or other actions included in accordance with the present disclosure. The storage arrays and methods described herein may be implemented in a system using any hardware and/or software configured as desired. Furthermore, it should be understood that various features of the memory device including one or more memory cells as described, such as electrical wiring features, interconnect structures, etc., that may be formed during the fabrication of the memory device, are not shown in fig. 1-7 for ease of understanding.

Fig. 8 schematically illustrates an example computing device 800 including a memory array with one or more memory cells having improved floating gate and dielectric layer geometries, according to an embodiment of this disclosure. The computing device 800 includes system control logic 808 coupled to the one or more processors 804; a memory device 812 having a memory array 810 (e.g., a 3D NAND vertical string array) including one or more memory cells as described in connection with fig. 1-7; one or more communication interfaces 816; and input/output (I/O) devices 820.

Memory device 812 may be a non-volatile computer memory chip that may include memory structures as described in connection with fig. 1-7. In an embodiment, the memory device 812 may include a package having disposed therein the memory device 812, driver circuitry (e.g., drivers), input/output connections that electrically couple the memory device 812 with other components of the computing device 800. The memory device 812 may be configured to be removably or permanently coupled with the computing apparatus 800. Memory device 812 may include a memory structure having one or more memory cells (e.g., memory cells described with reference to fig. 1-7). The memory structure may be formed using one or more of the techniques described in connection with fig. 3A-3O and fig. 4-7.

Communication interface 816 provides an interface for computing device 800 to communicate over one or more networks and/or with any other suitable device. Communication interface 816 may include any suitable hardware and/or firmware. Communication interface 816 for one embodiment may include, for example, a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem. For wireless communications, communication interface 816 for one embodiment may use one or more antennas to communicatively couple computing device 800 with a wireless network.

For one embodiment, at least one of the processors 804 may be packaged together with logic for one or more controllers of system control logic 808. For one embodiment, at least one of the processors 804 may be packaged together with logic for one or more controllers of system control logic 808 to form a System In Package (SiP). For one embodiment, at least one of the processors 804 may be integrated on the same die with logic for one or more controllers of system control logic 808. For one embodiment, at least one of the processors 804 may be integrated on the same die with logic for one or more controllers of system control logic 808 to form a system on a chip (SoC).

For one embodiment, the system control logic 808 includes any suitable interface controller to provide any suitable interface to at least one of the processors 804 and/or to any suitable device or component in communication with the system control logic 808. The system control logic 808 may move data into and/or out of various components of the computing device 800.

For one embodiment, the system control logic 808 includes a memory controller 824 to provide an interface to the memory device 812 to control various memory access operations. The memory controller 824 may include control logic 828, which may be specifically configured to control access of the memory devices 812.

In various embodiments, I/O device 820 includes a user interface designed to enable user interaction with computing device 800, a peripheral component interface designed to enable peripheral component interaction with computing device 800, and/or sensors designed to determine environmental conditions and/or location information related to computing device 800. In various embodiments, the user interface may include, but is not limited to, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more digital cameras that capture pictures and/or video, a flash (e.g., a light emitting diode flash), and a keyboard. In various embodiments, the peripheral component interfaces may include, but are not limited to, a non-volatile memory port, an audio jack, and a power interface. In various embodiments, the sensors may include, but are not limited to, a gyroscope sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may additionally/alternatively be part of the communication interface 816 or interact with the communication interface 816 to communicate with components of a positioning network, such as Global Positioning System (GPS) satellites.

In various embodiments, the computing device 800 may be: mobile computing devices such as, but not limited to, laptop computing devices, tablet computing devices, notebooks, smart phones, and the like; a desktop computing device; a workstation; a server; and so on. Accordingly, the mobile computing device may further include at least one of a display communicatively coupled to the processor and/or a battery coupled to the processor.

Computing device 800 may have more or fewer components and/or different architectures. In other implementations, the computing device 800 may be any other electronic device that processes data.

According to various embodiments, the present disclosure describes several examples.

Example 1 is a memory device comprising a plurality of memory cells, wherein at least one of the memory cells comprises: a channel region; a floating gate adjacent to the channel region along a first side, wherein a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction of the channel region; a control gate adjacent to the floating gate along a second, opposite side of the floating gate, wherein a length of the floating gate extending in the direction of the channel region is at least as long as a length of the control gate extending in the direction of the channel region and comprises a tapered edge extending away from the channel region towards the control gate; and a dielectric layer disposed between the control gate and the floating gate, wherein the dielectric layer follows the tapered edge along the floating gate and forms discrete regions proximate to the floating gate to at least partially insulate the floating gate from adjacent memory cells.

Example 2 is the memory device of example 1, wherein the plurality of memory cells includes vertical 3D NAND strings of coupled memory cells in the direction of the channel region, and the dielectric layer forms a discrete region for each memory cell.

Example 3 is the memory device of example 1, wherein the dielectric layer includes an intermediate dielectric layer of a multi-layer inter-poly dielectric (IPD) region that follows the tapered edge and is proximate to the floating gate.

Example 4 is the memory device of example 3, wherein the intermediate dielectric layer comprises a material having a higher dielectric constant than silicon oxide, and the IPD region comprises two oxide films, each disposed on opposite sides of the intermediate dielectric layer.

Example 5 is the memory device of example 4, wherein the intermediate dielectric layer comprises silicon nitride.

Example 6 is the memory device of example 3, further comprising a barrier layer comprising an insulator material disposed between the IPD region and the floating gate.

Example 7 is the memory device of example 6, wherein the blocking layer is in direct contact with the floating gate and comprises silicon nitride.

Example 8 is the memory device of any one of examples 1-7, wherein the channel region comprises a semiconductor pillar comprising silicon oxide and including a polysilicon liner along a length of the semiconductor pillar.

Example 9 is the memory device of any one of examples 1-8, wherein the tapered edge narrows the floating gate toward the control gate.

Example 10 is a system, comprising: a processor and a memory coupled with the processor, wherein the memory comprises a 3D stacked memory array, the 3D stacked memory array comprising a plurality of memory cells, wherein the plurality of memory cells comprises: a plurality of floating gates adjacent to a channel region, wherein one or more of the floating gates have a length along the channel region that is substantially greater than a length along an orthogonal direction of the channel region; a plurality of control gates each adjacent a corresponding floating gate of the plurality of floating gates, wherein a length that one or more of the corresponding floating gates extend in the direction of the channel region is at least as long as a length that an adjacent control gate extends in the direction of the channel region and includes a tapered edge that extends away from the channel region toward the adjacent control gate; and a dielectric layer disposed between one or more of the plurality of control gates and one or more of the corresponding floating gates, following the tapered edge along the one or more corresponding floating gates, and forming a discrete region proximate the one or more corresponding floating gates to assist in the isolation of the one or more corresponding floating gates from adjacent memory cells.

Example 11 is the system of example 10, wherein the dielectric layer comprises an intermediate dielectric layer of a multi-layer inter-poly dielectric (IPD) region proximate to the one or more corresponding floating gates.

Example 12 is the system of example 11, further comprising a barrier film disposed between the multilayer IPD region and the one or more corresponding floating gates and forming a discrete barrier layer for a corresponding memory cell.

Example 13 is the system of example 10, wherein the plurality of memory cells includes a vertical 3D NAND string, and the dielectric layer insulates a memory cell of the plurality of memory cells from a next memory cell of the vertical 3D NAND string.

Example 14 is the system of example 10, wherein the channel region includes a portion of a polysilicon pillar having a substantially circular cross-section.

Example 15 is the system of any of examples 10-14, wherein the system comprises a mobile computing device, and further comprises at least one of a display communicatively coupled to the processor or a battery coupled to the processor.

Example 16 is a method of manufacturing a memory device, the method comprising: forming a channel region in a substrate; forming a plurality of control gates adjacent to the channel region; forming a corresponding plurality of floating gates adjacent to the plurality of control gates, each floating gate extending in a direction of the channel region as long as the corresponding control gate extends in the direction of the channel region; and forming a dielectric layer disposed between the plurality of control gates and the plurality of floating gates, wherein the dielectric layer follows tapered edges along one or more of the floating gates and forms discrete regions proximate to the one or more floating gates to assist in insulating a memory cell including the one or more floating gates and a corresponding control gate, and wherein a length of the floating gate in a direction of the channel region is substantially longer than a length of the floating gate in an orthogonal direction of the channel region.

Example 17 is the method of example 16, further comprising forming the substrate by depositing alternating layers of conductors and insulators to form a stack of alternating layers of conductors and insulators.

Example 18 is the method of example 17, wherein forming the channel region in the substrate includes anisotropically etching a cylindrical hole through a stack of alternating conductor and insulator layers.

Example 19 is the method of example 18, wherein forming a plurality of control gates adjacent to the channel region includes isotropically etching conductor layers in a stack of alternating conductor and insulator layers to create a plurality of pocket regions.

Example 20 is the method of example 19, wherein forming the dielectric layer includes forming a multi-layer dielectric over the plurality of pocket regions.

Example 21 is the method of example 20, wherein forming the multi-layer dielectric includes: growing or depositing a first layer of the multi-layer dielectric comprising an oxide over a bottom region of each of the plurality of pocket regions; growing or depositing a second layer of the multi-layer dielectric comprising silicon nitride over a surface of a substrate comprising each of the plurality of pocket regions; growing or depositing a sacrificial protective layer over the second layer; and performing etching treatment on the sacrificial protection layer to leave a part of the sacrificial protection layer in the bottom of the cavity region.

Example 22 is the method of example 21, further comprising selectively oxidizing or etching portions of the silicon nitride layer to form the tapered edge.

Example 23 is the method of example 21, further comprising substantially isolating the multi-layer dielectric of each of the one or more control gates and corresponding floating gate from adjacent control gates and floating gates.

Example 24 is the method of example 23, wherein substantially isolating the multi-layer dielectric of each of the one or more control gates and corresponding floating gate from each of the other plurality of control gates and floating gates comprises: removing the sacrificial protection layer; removing portions of the second layer of the multi-layer dielectric covering the insulator layer between each of one or more of the plurality of control gates; and growing a third layer of the multi-layer dielectric to substantially insulate the silicon nitride layer.

Example 25 is the method of any of examples 20-23, further comprising depositing an additional layer over the multilayer dielectric and over alternating layers of both conductor layers and insulator layers, and wherein the additional layer comprises atomic layer deposition of silicon nitride.

Various embodiments may include any suitable combination of the above-described embodiments, including alternative (or) embodiments (e.g., "and" may be "and/or") to the above-described embodiments in combination (and). Further, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, result in the actions of any of the embodiments described above. Further, some embodiments may include devices or systems having any suitable means for carrying out various operations of the embodiments described above.

The above description of illustrated embodiments, including what is described in the abstract, is not intended to be exhaustive or to limit embodiments of the disclosure to the precise forms disclosed. While specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications can be made to the embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit embodiments of the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.