阅读说明：本技术 抗裂缝的深沟槽隔离结构、图像传感器结构及其形成方法 (Crack resistant deep trench isolation structure, image sensor structure and method of forming the same ) 是由 吴明锜 方俊杰 苏柏菖 杜建男 叶玉隆 林坤佑 陈世雄 于 2019-03-12 设计创作，主要内容包括：一种方法包括蚀刻半导体衬底以形成沟槽,将介电层填充到沟槽中,其中,在沟槽中和介电层的相对部分之间形成空隙,蚀刻介电层以暴露空隙,在介电层上形成扩散阻挡层,以及在扩散阻挡层上形成高反射率金属层。高反射率金属层具有延伸到沟槽中的部分。通过高反射率金属层包围空隙的剩余部分。本发明的实施例还提供了抗裂缝的深沟槽隔离结构、图像传感器结构及其形成方法。(A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, wherein a void is formed in the trench and between opposing portions of the dielectric layer, etching the dielectric layer to expose the void, forming a diffusion barrier layer on the dielectric layer, and forming a high reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. The remainder of the void is surrounded by a high reflectivity metal layer. Embodiments of the invention also provide crack resistant deep trench isolation structures, image sensor structures, and methods of forming the same.)

1. A method for forming an image sensor structure, comprising:

etching the semiconductor substrate to form a trench;

filling a dielectric layer into the trench, wherein a void is formed in the trench and between opposing portions of the dielectric layer;

etching the dielectric layer to expose the voids;

forming a diffusion barrier layer on the dielectric layer; and

and forming a high-reflectivity metal layer on the diffusion barrier layer, wherein the high-reflectivity metal layer comprises a part extending into the groove, and the rest part of the gap is surrounded by the high-reflectivity metal layer.

2. The method of claim 1, wherein forming the high-reflectivity metal layer comprises:

forming a seed layer extending into the trench;

plating a first copper-containing metal layer on the seed layer to be greater than

depositing a second copper-containing metal layer on the first copper-containing metal layer, wherein the second copper-containing metal layer is plated using a second plating current that is greater than the first plating current.

3. The method of claim 1, wherein forming the diffusion barrier layer comprises depositing a conformal high-k dielectric layer.

4. The method of claim 1, further comprising, prior to etching the semiconductor substrate to form the trench, etching the semiconductor substrate to form an array of pyramid bodies, wherein the pyramid bodies are formed from portions of the semiconductor substrate.

5. The method of claim 1, further comprising planarizing the high-reflectivity metal layer, the diffusion barrier layer, and the dielectric layer to form Deep Trench Isolation (DTI) regions, wherein the voids are sealed in the high-reflectivity metal layer after planarizing the high-reflectivity metal layer.

6. The method of claim 5, wherein the deep trench isolation regions form a mesh, and further comprising:

forming a pixel cell, wherein a portion of the pixel cell is located in the grid; and

forming color filters and microlenses overlapping the grid.

7. The method of claim 1, wherein a portion of the void extends beyond the semiconductor substrate.

8. The method of claim 1, wherein forming the diffusion barrier layer comprises depositing hafnium oxide or aluminum oxide.

9. A method for forming an image sensor structure, comprising:

forming a Shallow Trench Isolation (STI) region extending from a first surface of a semiconductor substrate into the semiconductor substrate;

forming a pixel unit between the shallow trench isolation regions;

forming a Deep Trench Isolation (DTI) region extending from a second surface of the semiconductor substrate toward the shallow trench isolation region, wherein forming the deep trench isolation region comprises:

etching the semiconductor substrate to form a trench extending from a second surface of the semiconductor substrate into the semiconductor substrate;

forming a dielectric layer extending into the trench;

filling a high-reflectivity metal layer to extend into the trench and over the dielectric layer, wherein the high-reflectivity metal layer surrounds a void therein; and

planarizing the high-reflectivity metal layer and the dielectric layer to form the deep trench isolation region; and

forming a microlens aligned with the pixel cell.

10. An image sensor structure comprising:

a Deep Trench Isolation (DTI) region extending into the semiconductor substrate from a top surface of the semiconductor substrate, wherein the deep trench isolation region comprises:

a dielectric layer extending into the semiconductor substrate; and

a high-reflectivity metal layer between opposing portions of the dielectric layer, wherein the high-reflectivity metal layer surrounds a void therein;

a diffusion barrier layer over the deep trench isolation region and the semiconductor substrate;

a pixel unit having a portion in the semiconductor substrate;

a color filter overlapping the pixel unit; and

a microlens overlapping the color filter.

Technical Field

Embodiments of the invention relate generally to the field of semiconductor technology and, more particularly, to crack resistant deep trench isolation structures, image sensor structures, and methods of forming the same.

Background

The semiconductor image sensor is operated to sense light. In general, semiconductor image sensors include Complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS) and Charge Coupled Device (CCD) sensors, which are widely used in various applications such as Digital Still Camera (DSC), cell phone camera, Digital Video (DV), and Digital Video Recorder (DVR) applications. These semiconductor image sensors utilize an array of image sensor elements, each including a photodiode and other elements, to absorb light and convert the sensed light into digital data or electrical signals.

Front-illuminated (FSI) CMOS image sensors and backside-illuminated (BSI) CMOS image sensors are two types of CMOS image sensors. The FSICMOS image sensor may be used to detect light projected from its front side, and the BSICMOS image sensor may be used to detect light projected from its back side. When light is projected onto the FSICMOS image sensor or the BSICMOS image sensor, photoelectrons are generated and then sensed by a photosensitive device in a pixel of the image sensor. The more photoelectrons are generated, the higher the quantum efficiency the image sensor has, thus improving the image quality of the CMOS image sensor.

However, when the CMOS image sensor technology is rapidly developed, a CMOS image sensor having higher quantum efficiency is desired.

Disclosure of Invention

According to an aspect of the present invention, there is provided a method for forming an image sensor structure, comprising: etching the semiconductor substrate to form a trench; filling a dielectric layer into the trench, wherein a void is formed in the trench and between opposing portions of the dielectric layer; etching the dielectric layer to expose the voids; forming a diffusion barrier layer on the dielectric layer; and forming a high-reflectivity metal layer on the diffusion barrier layer, wherein the high-reflectivity metal layer includes a portion extending into the trench and surrounds a remaining portion of the void through the high-reflectivity metal layer.

According to another aspect of the present invention, there is provided a method for forming an image sensor structure, comprising: forming a Shallow Trench Isolation (STI) region extending from a first surface of a semiconductor substrate into the semiconductor substrate; forming a pixel unit between the shallow trench isolation regions; forming a Deep Trench Isolation (DTI) region extending from a second surface of the semiconductor substrate toward the shallow trench isolation region, wherein forming the deep trench isolation region comprises: etching the semiconductor substrate to form a trench extending from a second surface of the semiconductor substrate into the semiconductor substrate; forming a dielectric layer extending into the trench; filling a high-reflectivity metal layer to extend into the trench and over the dielectric layer, wherein the high-reflectivity metal layer surrounds a void therein; and planarizing the high-reflectivity metal layer and the dielectric layer to form the deep trench isolation region; and forming a microlens aligned with the pixel unit.

According to still another aspect of the present invention, there is provided an image sensor structure comprising: a Deep Trench Isolation (DTI) region extending into the semiconductor substrate from a top surface of the semiconductor substrate, wherein the deep trench isolation region comprises: a dielectric layer extending into the semiconductor substrate; and a high-reflectivity metal layer between opposing portions of the dielectric layer, wherein the high-reflectivity metal layer surrounds a void therein; a diffusion barrier layer over the deep trench isolation region and the semiconductor substrate; a pixel unit having a portion in the semiconductor substrate; a color filter overlapping the pixel unit; and a microlens overlapping the color filter.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-12 illustrate cross-sectional views of intermediate stages of forming deep trench isolation regions, in accordance with some embodiments.

FIG. 13 illustrates a schematic diagram of a pixel cell according to some embodiments.

Figure 14 illustrates a top view of a deep trench isolation structure, in accordance with some embodiments.

Fig. 15 illustrates a cross-sectional view of a front-illuminated (FSI) image sensor chip, according to some embodiments.

FIG. 16 shows reflectance values for some metals as a function of wavelength according to some embodiments.

Fig. 17 illustrates the absorption index and the reflection index of copper as a function of copper thickness according to some embodiments.

Figure 18 illustrates a process flow for forming deep trench isolation regions in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Deep Trench Isolation (DTI) structures in a semiconductor substrate and methods of forming the same are provided according to various embodiments. An intermediate stage of forming a D/TI structure is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various figures and exemplary embodiments. According to some embodiments of the invention, the DTI structure forms a grid and comprises a high-reflectivity metal material and voids located in the high-reflectivity metal material. Therefore, by using a high-reflectivity metal material, the quantum efficiency of the image sensor is improved. On the other hand, in the case of forming the void, a buffer is provided to absorb stress generated in thermal cycles due to a significant difference between the high-reflectivity metal material and the semiconductor substrate. Thus, the possibility of cracking is reduced. The DTI structure may be used in back-illuminated (BSI) Complementary Metal Oxide Semiconductor (CMOS) image sensors or front-illuminated (FSI) CMOS image sensors, and may be used in other applications where deep trench isolation regions are used.

Figures 1-12 illustrate cross-sectional views of intermediate stages in forming a DTI structure, according to some embodiments of the invention. The steps shown in fig. 1 to 12 are also reflected schematically in the process flow 200 shown in fig. 18. According to some embodiments of the present invention, the DTI region may be used in an image sensor chip (such as an FSI image sensor chip or a BSI image sensor chip).

Fig. 1 illustrates an initial structure for forming an image sensor die 20, wherein the initial structure may be part of a wafer 22 including a plurality of image sensor dies 20 located therein. The corresponding process is shown in the process flow shown in fig. 18 as process 202. The image sensor chip 20 includes a semiconductor substrate 24. According to some embodiments of the present invention, semiconductor substrate 24 is a crystalline silicon substrate. According to other embodiments of the present invention, semiconductor substrate 24 comprises an elemental semiconductor such as germanium; a compound semiconductor including silicon carbon, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. Throughout the description, the main surface 24A of the substrate 24 is referred to as the front surface of the semiconductor substrate 24, and the surface 24B is referred to as the back surface of the semiconductor substrate 24. Surfaces 24A and 24B may lie in the (100) or (001) plane.

Isolation regions 32, alternatively referred to as Shallow Trench Isolation (STI) regions 32, are formed to extend into the semiconductor substrate 24 to define active areas for circuitry. According to some embodiments of the invention, as shown in the top view in fig. 14, STI regions 32 may form a grid including horizontal stripe portions and vertical stripe portions that cross each other.

Referring back to fig. 1, the image sensor 26 is formed to extend from the front surface 24A into the semiconductor substrate 24. The forming of the image sensor 26 may include implanting. The image sensor 26 is configured to convert optical signals (photons) into electrical signals. The image sensor 26 may be a light sensitive Metal Oxide Semiconductor (MOS) transistor, a photodiode, or the like. Throughout the description, the image sensors 26 are alternatively referred to as photodiodes 26, but they may be other types of image sensors. According to some embodiments of the present invention, the photodiodes 26 form an image sensor array.

Fig. 1 also shows a pixel cell 30, which may include at least a portion of an active region defined by STI regions 32. Fig. 13 shows a circuit diagram of an example of the pixel unit 30. According to some embodiments of the present invention, the pixel cell 30 includes a photodiode 26 having an anode electrically connected to ground GND and a cathode connected to the source of the transfer gate transistor 134. The drain of the pass gate transistor 134 may be connected to the drain of the reset transistor 138 and the gate of the source follower 142. The reset transistor 138 has a gate connected to a reset line RST. A source of the reset transistor 138 may be connected to a pixel supply voltage VDD. A floating diffusion capacitor 140 may be connected between the source/drain of the pass gate transistor 134 and the gate of the source follower 142. The reset transistor 138 is used to preset the voltage at the floating diffusion capacitor 140 to VDD. The drain of the source follower 142 is connected to the supply voltage VDD. The source of the source follower 142 is connected to a row selector 144. The source follower 142 provides a high impedance output for the pixel cell 30. The row selector 144 serves as a selection transistor of the corresponding pixel unit 30, and the gate of the row selector 144 is connected to a selection line SEL.

Referring back to fig. 1, the transistors are shown as examples of devices (such as 134, 138, 142, and 144 in fig. 13) in the pixel cell 30. For example, a pass-gate transistor 134 is shown in FIG. 1. According to some embodiments of the present invention, each photodiode 26 is electrically connected to a first source/drain region of a transfer gate transistor 134, wherein the transfer gate transistor 134 includes a gate 28 and a gate dielectric 31. The gate dielectric 31 is in contact with the front surface 24A of the substrate 24. The first source/drain region of the transfer gate transistor 134 may be shared by the respectively connected photodiodes 26. Floating diffusion capacitor 140 is formed in substrate 24, for example, by implanting substrate 24 to form a p-n junction, thereby functioning as floating diffusion capacitor 140. Floating diffusion capacitor 140 may be formed in the second source/drain region of transfer gate transistor 134 and, thus, one capacitor plate of floating diffusion capacitor 140 is electrically connected to the second source/drain region of transfer gate transistor 134. The photodiode 26 and the corresponding transfer gate transistor 134 and floating diffusion capacitor 140 located in the same active area form a pixel cell 30 as labeled in fig. 1.

A Contact Etch Stop Layer (CESL)40 is formed over the substrate 24 and transistors, such as the transfer gate transistor 134. An interlayer dielectric (ILD)42 is formed over CESL 40. The CESL 40 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., or a multilayer thereof. Conformal deposition such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) may be usedA product method to form CESL 40. ILD 42 may comprise a dielectric material formed using, for example, Flowable Chemical Vapor Deposition (FCVD), spin-on coating, CVD, or another deposition method. ILD 42 may also be formed of an oxygen-containing dielectric material, wherein the oxygen-containing dielectric material may be, for example, Tetraethylorthosilicate (TEOS) oxide, plasma-enhanced CVD (PECVD) silicon oxide (SiO)₂) Oxides of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like.

A frontside interconnect structure 44 is formed over the semiconductor substrate 24. The front-side interconnect structure 44 is used to electrically interconnect devices in the image sensor chip 20. The frontside interconnect structure 44 includes a dielectric layer 46, and metal lines 48 and vias 50 located in the dielectric layer 46. Throughout the description, the metal lines 48 in the same dielectric layer 46 are collectively referred to as metal layers. The front-side interconnect structure 44 may include multiple metal layers. According to some embodiments of the present invention, the dielectric layer 46 comprises a low-k dielectric layer. The low-k dielectric layer has, for example, a low-k value of less than about 3.0. One or more passivation layers 52 are formed over the dielectric layer 46. The passivation layer 52 may be formed of a non-low-k dielectric material having a k value equal to or greater than about 3.8. According to some embodiments of the present invention, the passivation layer 52 includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

Referring to fig. 2, wafer 22 is flipped. Backside grinding is performed to grind the back surface 24B (fig. 1) to a thin semiconductor substrate 24. The resulting back surface is referred to as 24B' in fig. 2. For example, the thickness of the substrate 24 may be reduced to less than about 10 μm, or less than about 5 μm. In the case where the semiconductor substrate 24 has a small thickness, light can penetrate into the semiconductor substrate 24 from the back surface 24B' and reach the photodiode 26.

According to some embodiments of the present invention, an etch mask 54 is formed on the back side 24B' of the semiconductor substrate 24. The corresponding process is shown as process 204 in the process flow shown in fig. 18. According to some embodiments of the present invention, etch mask 54 comprises a hard mask that may be formed of silicon nitride, titanium nitride, or the like. A pad layer (not shown) may also be formed under the hard mask. For example, the liner layer may be a thin film including silicon oxide formed using a thermal oxidation process or a deposition process such as Chemical Vapor Deposition (CVD). The pad layer may buffer the stress of the hard mask. According to some embodiments of the present invention, hard mask 54 may be formed from silicon nitride using, for example, Low Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments, the hard mask 54 is formed using thermal nitridation of silicon, Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. A photoresist (not shown) may be formed on the hard mask 54 and then patterned, and the hard mask 54 may be patterned using the photoresist as an etching mask. In the top view of the structure shown in fig. 2, patterned etch mask 54 may comprise a plurality of discrete blocks arranged in an array, with the spaces between the discrete blocks forming a grid.

Next, an etching process is performed to form the structure shown in fig. 3. A corresponding process is shown in the process flow shown in fig. 18 as process 206. The etching process may include a wet etching process, wherein the wet etching process may be performed using KOH, tetramethylammonium hydroxide (TMAH), or the like, as an etchant. Since the etching rates of the semiconductor substrate 24 on different planes are different from each other, for example, the inclined straight surface 56A is formed on the (111) plane, wherein the straight surface 56A has the inclination angle β equal to about 54.7 degrees. The recess 58 is formed to extend into the semiconductor substrate 24.

As the etching of the semiconductor substrate 24 proceeds, the straight surfaces 56A are recessed, and the opposite surfaces 56A facing the same groove 58 eventually intersect with each other to have a V shape. According to some embodiments of the present invention, the etch mask 54 is removed after the recess 58 begins to extend directly under the etch mask 54, followed by another wet etch to further extend the recess 58 down to the top of the semiconductor substrate 24 to form a taper. According to other embodiments, the etch mask 54 is consumed during the wet etch such that a single wet etch process may produce the structure shown in fig. 3. According to some embodiments of the present invention, when the recess 58 begins to extend directly below the etch mask 54, the etch mask 54 is removed and no further etching of the substrate 24 is performed after the etch mask 54 is removed.

After etching, cones 56 are formed, wherein each cone comprises four sides. Each of the four sides has a triangular shape. According to other embodiments, instead of having a pyramidal shape, a pseudo-pyramidal body is formed, which includes a facet platform at the top, which is formed because the portion of the substrate 24 directly below the etch mask 54 is not completely etched. Thus, the resulting structure will have a trapezoidal cross-sectional shape. In the subsequent discussion, pyramids are used as an example, and other shapes of the top of the substrate 24 are contemplated. When viewed from the top, the vertebral bodies (or pseudo-vertebral bodies) may form an array.

Next, an etching process is performed to form the trench 60. A corresponding process is shown in the process flow shown in fig. 18 as process 208. The etching is performed by an anisotropic etching process so that the sidewalls of the trenches 60 are straight and vertical, wherein the sidewalls are perpendicular to the main surface 24A of the substrate 24. The trench 60 may also be slightly tapered, and thus the sidewalls of the trench 60 are substantially perpendicular (and slightly inclined) to the major surface 24A of the substrate 24. For example, the angle α may be greater than about 88 degrees and less than 90 degrees. According to some embodiments of the present invention, the etching is performed by a dry etching method, wherein the dry etching method includes, but is not limited to, Inductively Coupled Plasma (ICP), Transfer Coupled Plasma (TCP), Electron Cyclotron Resonance (ECR), Reactive Ion Etching (RIE), and the like. For example, the process gas includes, for example, a fluorine-containing gas (such as SF)₆、CF₄、CHF₃、NF₃) Chlorine-containing gas (such as Cl)₂)、Br₂、HBr、BCl₃And the like. The trenches 60 form a grid when viewed from the top of the wafer 22. In addition, trenches 60 may overlap STI regions 32, STI regions 32 also forming a grid. The trenches 60 may be spaced a small distance, e.g., less than about 0.5 μm, from the respective underlying STI regions 32.

According to some embodiments of the present invention, the depth D1 of trench 60 is in a range between about 1 μm and about 10 μm. The width W1 of trench 60 may be in a range between about 0.1 μm and about 0.3 μm. The aspect ratio D1/W1 of trench 60 may be greater than about 5, or greater than about 10 or greater (e.g., between about 10 and 20). According to some embodiments of the present invention, the bottom surface of the groove 60 is circular and has a U-shape or V-shape in cross-sectional view.

FIG. 5 illustrates forming a dielectricLayer 62. The corresponding process is shown in the process flow shown in fig. 18 as process 210. According to some embodiments of the present invention, dielectric layer 62 comprises silicon oxide. The formation of dielectric layer 62 may be accomplished by a non-conformal and non-bottom-up deposition method such that recess 58 (fig. 4) is completely filled. A void (air gap) 64 is formed in the trench 60 and is sealed by the dielectric layer 62. For example, the dielectric layer 62 may be formed using High Density Plasma (HDP) Chemical Vapor Deposition (CVD). According to some embodiments, the apex of the void 64 may be higher than the apex of the vertebral body 56. The thickness T1 of the sidewall portion of the dielectric layer 62 in the trench 60 may be aboutTo about

Wherein the thickness T1 may be measured at a level midway between the bottom of the trench 60 and the top of the cone 56. According to some embodiments of the present invention, a planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed. According to an alternative embodiment of the present invention, no planarization process is performed on the dielectric layer 62.

Fig. 6 shows that dielectric layer 62 is opened to expose voids 64. The corresponding process is shown in the process flow shown in fig. 18 as process 212. According to some embodiments of the invention, the opening process comprises a dry etch or a wet etch process. For example, when dry etching is used, NF may be used₃And NH₃Mixed gas of (3) or HF and NH₃The mixed gas of (1). When wet etching is used, an HF solution may be used. The etching may be performed without any hard mask and all of the top surface of the dielectric layer 62 is exposed to the etchant. Since the portion of the dielectric layer 62 directly above the void 64 is thinner than the portion directly above the vertebral body 56, the void 64 is exposed while some other portion of the dielectric layer 62 remains to cover the vertebral body 56, although the etching is performed without an etch mask. According to some embodiments of the invention, the void 64 has a curved edge at the top, where a dashed line 65 is drawn to illustrate possible shapes. Rear endThe subsequently formed layers 66 and 68 will thus follow the contour of the dashed line 65. According to an alternative embodiment of the invention, an etch mask (not shown), such as a patterned photoresist, is used, wherein the patterned etch mask has portions that overlap the pyramid 56 and has openings that overlap the void 64. Dielectric layer 62 is etched using an etch mask to open voids 64.

Fig. 7 illustrates the formation of a diffusion barrier layer 66. A corresponding process is shown in the process flow shown in fig. 18 as process 214. According to some embodiments of the present invention, the diffusion barrier layer 66 is formed of a material that is effective to prevent a subsequently deposited high reflectivity layer 68 (FIG. 9) from diffusing into the substrate 24. Furthermore, the diffusion barrier layer 66 may also be formed from a high-k dielectric layer, as some high-k dielectric materials have favorable optical properties (such as good reflective properties). Embodiments also contemplate non-high k materials with good optical properties. According to some embodiments of the present invention, the diffusion barrier layer 66 is made of aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Tantalum oxide (Ta)₂O₅) Etc., or a composite layer including more than one of these material layers. The formation of the diffusion barrier layer 66 may be accomplished using a conformal deposition method such as Atomic Layer Deposition (ALD), CVD, and the like. The thickness of the diffusion barrier layer 66 is large enough to prevent the subsequently deposited high reflectivity layer 68 (fig. 9) from diffusing into the substrate 24, but small enough to leave sufficient space for the high reflectivity layer 68 and the voids 64. For example, the thickness T2 of the diffusion barrier layer 66 is greater than about 30 angstroms because the diffusion barrier layer 66 is not diffusion proof if the thickness T2 is small. In another aspect, thickness T2 may be less than about 10% of width W1 of trench 60. Otherwise, the remaining void 64 would be too small and would not have sufficient height. The thickness T2 of the diffusion barrier layer 66 may be aboutTo about

Within the range of (a). Thickness T2 may also be measured at a level midway between the bottom of groove 60 and the top of cone 56.

Fig. 8 illustrates the formation of the high-reflectance layer 68. The corresponding process is shown in the process flow shown in fig. 18 as process 216. According to some embodiments of the invention, the method of forming includes forming a seed layer (e.g., using PVD), and plating the high reflectivity layer 68. The seed layer may be formed of copper. The material of the high-reflectivity layer 68 includes a material having a high reflectivity of, for example, greater than about 90% at wavelengths greater than about 600 nm. FIG. 16 shows several metal-containing materials (thickness of) The reflectance value of (a). As shown in fig. 16, copper and aluminum copper (AlCu) have high reflectance values and may be used to form the high reflectance layer 68. By comparison, tungsten and titanium nitride have low reflectivity values and will not be used. Also, fig. 17 shows the absorption index k and the reflection index n of copper as a function of copper thickness, according to some embodiments. The results shown in fig. 17 were obtained using light having a wavelength of 940 nm. FIG. 17 shows that when the thickness of the copper layer is about 15nmOr greater, the absorption index k is high, e.g., having a value of about 5.0 or greater. When the thickness of copper is greater than about

In this case, the absorption index k becomes stably high. A high absorption index means that light entering the copper is absorbed more and does not penetrate the copper into the adjacent image sensor cell and adversely affect the adjacent image sensor cell. FIG. 17 also shows that when the copper layer has a thickness of about

Or greater, the index of reflection n is low. When the thickness of copper is greater than about

In this case, the reflection index n also becomes stably low. The low reflection index n means the reflection of light from the copper surfaceAnd more preferably. Furthermore, as the copper thickness increases to about

Or greater, the absorption index k and reflection index n of copper are satisfactory for all wavelengths.

Based on the results shown in FIG. 17, the thickness of the high reflectivity layer 68 was greater than about

And may be greater than about for devices with high performance requirements

The thickness of the high reflectivity layer 68 is also small enough so that the remaining voids 64 are large enough and the top of the voids 64 may be at least flush with the top of the substrate 24 or higher than the top of the substrate 24 so that the ability of the voids 64 to absorb stress is not compromised. According to some embodiments of the invention, the thickness T3 of the high reflectivity layer 68 (FIG. 8) may be about

And the combination

And may be in the range of about

And the combination

Within the range of (1). Thickness T3 may also be measured at a level midway between the bottom of groove 60 and the top of cone 56. Also, all portions of the high reflectivity layer 68 may have a reflectivity greater than about

Or greater than aboutIs measured.

In order to form the high-reflectance layer 68 while leaving the void 64 incompletely filled, a method capable of increasing the overhang (overhang) of the high-reflectance layer 68 is used, wherein the overhang portion is a portion directly above some portion of the void 64. The overhanging portions of the high reflectivity layer 68 grow toward each other and eventually seal the void 64 therein. According to some embodiments of the present invention, the high reflectivity layer 68 is plated, wherein the plating includes two stages. The first stage is carried out using a first plating current sufficiently small so that the correspondingly plated first layer of the high reflectivity layer 68 is substantially conformal. Thus, the plated first layer has good coverage. When the thickness of the first layer of the high-reflectivity layer 68 is greater than about

(e.g., for copper), the second stage is carried out and a second plating current higher than the first plating current is used to increase the deposition rate and form a second layer on the first layer. The deposition rate in the second stage is high so that the top of the metal layer 68 (especially the portion outside and around the top of the trench 60) grows much faster than the portion inside the trench 60. Thus, the void 64 is sealed. According to some embodiments of the invention, the first plating current of the first plating stage has a first current in a range between about 0.5 amps and about 5 amps and the second plating current has a second current in a range between about 10 amps and about 40 amps. It should be understood that the plating current is related to the total area to be plated. According to some embodiments of the invention, the ratio of the second current to the first current (and the corresponding current density) is greater than 1.0, greater than about 2.0, and may be in a range between about 2 and about 80.

Referring to fig. 9, a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove excess portions of layers 62, 66, and 68, thereby forming Deep Trench Isolation (DTI) 70. A corresponding process is shown in the process flow shown in fig. 18 as process 218. The remaining void 64 in the DTI region 70 has an apex that is flush or higher than the base of the vertebral body 56, e.g., at a level between the apex and the base of the vertebral body 56, to effectively absorb stresses. The apex of the void 64 may also be higher than the apex of the vertebral body 56 to further enhance the ability to absorb stresses. In addition, the DTI zone 70 includes a portion 70A that is above the apex of the vertebral body 56. There are no voids in the portion 70A. The portions of metal layer 68 in portion 70A also form a grid when viewed from the top of wafer 22. Thus, these portions of the metal layer 68 act as a metal grid. According to some embodiments of the invention, the height H2 of portion 70A is greater than about 0.5 μm to effectively limit incident light between the grids.

Fig. 10 illustrates the deposition of a diffusion barrier layer 72. The corresponding process is shown in the process flow shown in fig. 18 as process 220. According to some embodiments of the present invention, diffusion barrier layer 72 comprises silicon nitride or the like. The diffusion barrier layer 72 prevents upward diffusion of materials, such as copper, in the DTI region 70.

Figure 14 shows a top view of DTI region 70. According to some embodiments of the present invention, a plurality of DTI regions 70 are formed simultaneously, each having the structure shown in fig. 10. The plurality of DTI regions 70 form a plurality of stripes as shown in fig. 14, which includes a plurality of first stripes 70 extending in the X direction, and a plurality of second stripes 70 extending in the Y direction, wherein the X direction is perpendicular to the Y direction. Thus, the plurality of first DTI regions 70 and the plurality of second DTI regions 70 form a grid pattern in which portions of the semiconductor substrate 24 are separated from each other and defined by a grid. The grid of DTI regions 70 overlaps the grid formed by STI regions 32.

As shown in fig. 14, the void 64 may include a portion extending in the X direction and a portion extending in the Y direction. The portions of the voids 64 extending in the X-direction and the Y-direction are also interconnected to form an overall void having the shape of a grid when viewed from the top.

In subsequent process steps, additional features such as color filters 74 are formed as shown in fig. 11. The corresponding process is shown in the process flow shown in fig. 18 as process 222. Then, as shown in fig. 12, microlenses 76 are formed. A corresponding process is shown in the process flow shown in fig. 18 as process 224. Each image sensor 26 is aligned with one of the color filters 74 and one of the microlenses 76. Thereby forming image sensor chips 20 (and corresponding wafer 22).

The image sensor chip 20 as shown in fig. 12 is a BSI image sensor chip and incident light 78 is projected onto the image sensor 26 from the backside of the substrate 24. Light 78 may be scattered by the sloped surface 56A such that the light becomes more sloped within the substrate 24. The oblique light is more likely to be reflected (rather than transmitted through the substrate 24). Also, by forming the high-reflectance layer 68 using a high-reflectance material, light is more likely to be reflected than absorbed by the DTI 70. These factors increase the light propagation path in the substrate 24 (and image sensor 26) and there is more opportunity for light to be absorbed by the image sensor 26. The light conversion efficiency (quantum efficiency) is thus improved.

DTI regions 70 formed according to some embodiments of the present invention may also be used in other structures such as front-illuminated (FSI) image sensor chips. Fig. 15 illustrates an embodiment of forming a DTI region 70 in an FSI image sensor chip 20'. Referring to fig. 15, the FSI image sensor chip 20' includes DTI regions 70, wherein the DTI regions 70 form a grid similar to that shown in fig. 14. The pixel unit 30 has a portion formed in a region defined by the DTI region 70. According to some embodiments of the present invention, STI regions are no longer formed to define active regions, since the DTI regions 70 comprise dielectric layers that may also act as (electrical) isolation regions. Each pixel cell 30 may include a photodiode 26, a transfer gate transistor 134, and additional components (not shown in fig. 15, see fig. 13). DTI region 70 extends from a major surface 24A (which is the front surface) of semiconductor substrate 24 into an intermediate level of semiconductor substrate 24. Interconnect structure 44 may be formed over pixel cell 30 and DTI region 70 and include a plurality of metal lines and vias in a plurality of dielectric layers. Color filters 74 and microlenses 76 are formed over interconnect structure 44 and aligned with pixel cells 30. In the FSI image sensor chip 20 ', light 78 is projected from the front side of the chip 20' to the photodiode 26.

Multiple sets of samples were fabricated on semiconductor wafers to compare the results. The first set of samples was formed with an air gap (unfilled) as a DTI region. The second set of samples was formed with tungsten in the DTI region. A third set of samples was formed according to some embodiments of the present invention, in which copper was used. The first, second and third groups have the same number of pixels. After formation, three sets of samples were measured to determine the number of defective pixels and the quantum efficiency of the image sensor. The number of Dark Current (DC) pixels in the first, second and third sets of sample pixels is 17, 14 and 18, respectively. This means that the number of DC pixels according to some embodiments of the invention (the third group) is much better than the number of DC pixels of the second group and is about the same as the number of DC pixels of the first group. The number of White Pixels (WP) in the first, second and third sets of sample pixels is 522, 1145 and 438, respectively, which means that the number of DC pixels formed according to some embodiments of the invention (third set) is much better than both the first and second sets. Furthermore, the quantum efficiency (third set) of the samples formed according to some embodiments of the present invention was 19%, which was slightly lower than the 24% quantum efficiency of the first set of samples and much higher than the 5% quantum efficiency of the second set of samples. Thus, the samples formed according to some embodiments of the present invention have the best overall performance.

Embodiments of the present invention have some advantageous features. By forming the DTI region using a high-reflectivity metal material such as copper, the quantum efficiency of the image sensor is improved. However, the high-reflectivity metal material may have a Coefficient of Thermal Expansion (CTE) of about 16 to 16.7, which is much greater than the CTE of the substrate (about 3 to 5). Significant differences in CTE result in cracks that will form between the DTI region and the substrate. This problem is solved by forming voids (air gaps) in the DTI region. The voids act as a buffer for the increased copper volume at elevated temperatures and absorb the stress due to thermal cycling. Thus, the performance of the image sensor is improved without sacrificing reliability.

According to some embodiments of the invention, a method includes etching a semiconductor substrate to form a trench; filling a dielectric layer into the trench, wherein a void is formed in the trench and between opposing portions of the dielectric layer; etching the dielectric layer to expose the voids; forming a diffusion barrier layer on the dielectric layer; and forming a high-reflectivity metal layer on the diffusion barrier layer, wherein the high-reflectivity metal layer comprises a part extending into the groove, and the rest part of the gap is surrounded by the high-reflectivity metal layer. In an embodiment, forming the high-reflectivity metal layer includes: formed to extend into the trenchA seed layer; plating a first copper-containing metal layer on the seed layer to greater than about

A thickness, wherein the first copper-containing metal layer is plated using a first plating current; depositing a second copper-containing metal layer on the first copper-containing metal layer, wherein the second copper-containing metal layer is plated using a second plating current that is greater than the first plating current. In an embodiment, forming the diffusion barrier layer includes depositing a conformal high-k dielectric layer. In an embodiment, the method further comprises etching the semiconductor substrate to form an array of taper bodies, wherein the taper bodies are formed from portions of the semiconductor substrate, prior to etching the semiconductor substrate to form the trenches. In an embodiment, the method further comprises planarizing the high-reflectivity metal layer, the diffusion barrier layer, and the dielectric layer to form a DTI region, wherein the voids are sealed in the high-reflectivity metal layer after planarizing the high-reflectivity metal layer. In an embodiment, the DTI regions form a grid, and the method further comprises: forming a pixel unit, wherein a portion of the pixel unit is located in the grid; and forming a color filter and a microlens overlapping the grid. In an embodiment, a portion of the void extends beyond the semiconductor substrate. In an embodiment, forming the diffusion barrier layer comprises depositing hafnium oxide or aluminum oxide.

In an embodiment, forming the high-reflectivity metal layer includes: forming a seed layer extending into the trench; plating a first copper-containing metal layer on the seed layer to be greater than

Wherein the first copper-containing metal layer is plated using a first plating current; depositing a second copper-containing metal layer on the first copper-containing metal layer, wherein the second copper-containing metal layer is plated using a second plating current that is greater than the first plating current.

In an embodiment, forming the diffusion barrier layer comprises depositing a conformal high-k dielectric layer.

In an embodiment, the method further comprises, prior to etching the semiconductor substrate to form the trench, etching the semiconductor substrate to form an array of pyramid bodies, wherein the pyramid bodies are formed from portions of the semiconductor substrate.

In an embodiment, the method further comprises planarizing the high-reflectivity metal layer, the diffusion barrier layer, and the dielectric layer to form a Deep Trench Isolation (DTI) region, wherein the void is sealed in the high-reflectivity metal layer after planarizing the high-reflectivity metal layer.

In an embodiment, the deep trench isolation regions form a mesh, and the method further comprises: forming a pixel cell, wherein a portion of the pixel cell is located in the grid; and forming a color filter and a microlens overlapping the mesh.

In an embodiment, a portion of the void extends beyond the semiconductor substrate.

In an embodiment, forming the diffusion barrier layer comprises depositing hafnium oxide or aluminum oxide. According to some embodiments of the present invention, a method includes forming an STI region extending into a semiconductor substrate from a first surface of the semiconductor substrate; forming a pixel unit between the STI regions; forming a DTI region extending from the second surface of the semiconductor substrate toward the STI region, wherein forming the DTI region comprises: etching the semiconductor substrate to form a trench extending from the second surface of the semiconductor substrate into the semiconductor substrate; forming a dielectric layer extending into the trench; filling a high-reflectivity metal layer to extend into the trench and above the dielectric layer, wherein the high-reflectivity metal layer surrounds the gap therein; and planarizing the high-reflectivity metal layer and the dielectric layer to form a DTI region; and forming a microlens aligned with the pixel cell. In an embodiment, the DTI region includes a portion extending beyond the second surface of the semiconductor substrate, wherein the portion of the DTI region is located between the semiconductor substrate and the microlens. In an embodiment, the method further comprises etching the semiconductor substrate from the second surface to form a taper, prior to etching the semiconductor substrate to form the trench. In an embodiment, the dielectric layer further comprises a portion between the semiconductor substrate and the microlens. In an embodiment, the method further comprises forming a first diffusion barrier layer between the dielectric layer and the high-reflectivity metal layer; and forming a second diffusion barrier layer between the semiconductor substrate and the microlens. In an embodiment, filling the high-reflectivity metal layer includes: plating using a first plating current to form a substantially conformal layer; and plating with a second plating current greater than the first plating current to seal the void.

In an embodiment, the deep trench isolation region includes a portion that extends beyond the second surface of the semiconductor substrate, wherein the portion of the deep trench isolation region is located between the semiconductor substrate and the microlens.

In an embodiment, the method further comprises, prior to etching the semiconductor substrate to form the trench, etching the semiconductor substrate from the second surface to form a taper.

In an embodiment, the dielectric layer further comprises a portion between the semiconductor substrate and the microlens.

In an embodiment, the method further comprises: forming a first diffusion barrier layer between the dielectric layer and the high-reflectivity metal layer; a second diffusion barrier layer is formed between the semiconductor substrate and the microlens.

In an embodiment, filling the high-reflectivity metal layer includes: plating using a first plating current to form a conformal layer; and plating with a second plating current greater than the first plating current to seal the void.

According to some embodiments of the present invention, a structure includes a DTI region extending into a semiconductor substrate from a top surface of the semiconductor substrate, wherein the DTI region includes a dielectric layer extending into the semiconductor substrate; and a high-reflectivity metal layer disposed between the opposing portions of the dielectric layer, wherein the high-reflectivity metal layer surrounds the void therein; the diffusion barrier layer is positioned above the DTI area and the semiconductor substrate; a pixel unit having a portion in a semiconductor substrate; a color filter overlapping the pixel unit; and a microlens overlapping the color filter. In an embodiment, the structure further includes a Shallow Trench Isolation (STI) region extending into the semiconductor substrate from a bottom surface of the semiconductor substrate, wherein the DTI region overlaps the STI region. In an embodiment, the structure further comprisesA diffusion barrier layer between the semiconductor substrate and the color filter, wherein the dielectric layer includes a portion overlapping the semiconductor substrate, wherein the portion of the dielectric layer has opposing surfaces in contact with the semiconductor substrate and the diffusion barrier layer. In an embodiment, the structure further comprises an additional diffusion barrier layer located between the dielectric layer and the high-reflectivity metal layer, wherein the additional diffusion barrier layer is located in the semiconductor substrate. In an embodiment, the high-reflectivity metal layer has a reflectivity of greater than about 90%. In an embodiment, all portions of the high-reflectivity metal layer in the DTI region have a thickness greater than about

Is measured.

In an embodiment, the structure further comprises: a Shallow Trench Isolation (STI) region extending into the semiconductor substrate from a bottom surface of the semiconductor substrate, wherein the deep trench isolation region overlaps the shallow trench isolation region.

In an embodiment, the dielectric layer includes a portion overlapping the semiconductor substrate, wherein the portion of the dielectric layer has opposing surfaces in contact with the semiconductor substrate and the diffusion barrier layer.

In an embodiment, the structure further comprises an additional diffusion barrier layer located between said dielectric layer and said high reflectivity metal layer, wherein said additional diffusion barrier layer is located in said semiconductor substrate.

In an embodiment, the high-reflectivity metal layer has a reflectivity of greater than 90%.

In an embodiment, all portions of the high-reflectivity metal layer in the deep trench isolation region have a thickness greater than

Is measured.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.