阅读说明：本技术 显示面板和包括显示面板的显示装置 (Display panel and display device including the same ) 是由 李俊杰 高京秀 金湘甲 崔新逸 于 2019-06-25 设计创作，主要内容包括：提供了显示面板和包括显示面板的显示装置。所述显示面板包括基底,所述基底具有开口区域和至少部分地围绕开口区域的显示区域。显示元件布置在显示区域中。显示元件包括像素电极、对电极和置于像素电极与对电极之间的中间层。多层膜包括在基底与像素电极之间的第一绝缘层和位于第一绝缘层上的具有不同材料的第二绝缘层。薄膜封装层覆盖显示元件并且包括至少一个有机封装层和至少一个无机封装层。所述多层膜包括设置在开口区域与显示区域之间的第一凹槽。第一凹槽具有底切结构,在所述底切结构中,第一凹槽的下宽度大于第一凹槽的上宽度。(A display panel and a display apparatus including the same are provided. The display panel includes a substrate having an opening region and a display region at least partially surrounding the opening region. The display element is arranged in the display area. The display element includes a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode. The multi-layer film includes a first insulating layer between the substrate and the pixel electrode and a second insulating layer having a different material on the first insulating layer. The thin film encapsulation layer covers the display element and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove disposed between an opening region and a display region. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.)

1. A display panel, the display panel comprising:

a substrate having an open area and a display area at least partially surrounding the open area;

a plurality of display elements arranged in the display area, each of the plurality of display elements including a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode;

a multi-layer film including a first insulating layer disposed between the substrate and the pixel electrode and a second insulating layer disposed on the first insulating layer and having a material different from that of the first insulating layer; and

a thin film encapsulation layer covering the plurality of display elements and including at least one organic encapsulation layer and at least one inorganic encapsulation layer,

wherein the multilayer film includes a first groove disposed between the opening region and the display region, and

wherein the first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

2. The display panel according to claim 1, wherein the first insulating layer is an organic insulating layer, and wherein the second insulating layer is an inorganic insulating layer.

3. The display panel according to claim 1, wherein the pixel electrode contacts an upper surface of the first insulating layer, and an end portion of the pixel electrode is covered with the second insulating layer.

4. The display panel of claim 1, wherein the at least one inorganic encapsulation layer comprises a first inorganic encapsulation layer and a second inorganic encapsulation layer in the thin film encapsulation layer, wherein the at least one organic encapsulation layer comprises one organic encapsulation layer, wherein the organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

5. The display panel of claim 1, wherein the at least one inorganic encapsulation layer covers an inner surface of the first recess.

6. The display panel of claim 1, further comprising a third insulating layer disposed under the multilayer film,

wherein the at least one inorganic encapsulation layer is in direct contact with the third insulating layer through the first groove.

7. The display panel according to claim 6, wherein the third insulating layer is an inorganic insulating layer.

8. The display panel of claim 1, wherein the at least one organic encapsulation layer at least partially fills the first recess.

9. The display panel of claim 1, wherein the multilayer film further comprises a second groove adjacent to the first groove, the second groove being closer to the open region than the first groove.

10. The display panel of claim 9, wherein an end of the at least one organic encapsulation layer is located between the first and second grooves.

11. The display panel of claim 1, wherein the substrate and the thin film encapsulation layer each have an opening corresponding to the opening region.

12. A display panel, the display panel comprising:

a substrate having an open region;

a plurality of display elements disposed on the substrate, the plurality of display elements surrounding the opening region, and each of the plurality of display elements including a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode;

a multi-layer film including a first insulating layer disposed between the substrate and the pixel electrode and a second insulating layer disposed on the first insulating layer; and

an encapsulation layer covering the plurality of display elements,

wherein the multilayer film includes a first groove surrounding the opening region and recessed with respect to a depth direction of the multilayer film, and

wherein the first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

13. The display panel according to claim 12, wherein the first insulating layer is in direct contact with the pixel electrode, and the second insulating layer covers an edge of the pixel electrode.

14. The display panel according to claim 12, wherein the first insulating layer is an organic insulating layer, and wherein the second insulating layer is an inorganic insulating layer.

15. The display panel of claim 12, wherein the encapsulation layers comprise at least one inorganic encapsulation layer and at least one organic encapsulation layer.

16. The display panel of claim 15, wherein the at least one inorganic encapsulation layer covers an entire inner surface of the first groove and is in direct contact with an inorganic insulating layer disposed below the first insulating layer.

17. The display panel according to claim 12, wherein the at least one organic material layer in the intermediate layer and the counter electrode are each cut off with respect to the first groove.

18. The display panel of claim 12, wherein the first groove is defined by a first hole of the first insulating layer and a second hole of the second insulating layer, and

wherein an inner side of the second insulating layer facing the second hole protrudes toward a center of the first groove than an inner side of the first insulating layer facing the first hole.

19. The display panel of claim 18, wherein the inner side of the second insulating layer protrudes toward a center of the first groove by at least 2 μ ι η more than the inner side of the first insulating layer.

20. The display panel of claim 12, wherein each of the plurality of display elements comprises an organic light emitting diode.

21. A display device, the display device comprising:

a substrate having an open area and a display area at least partially surrounding the open area;

a plurality of display elements arranged in the display area, each display element including a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode;

a multi-layered film including an organic insulating layer disposed between the substrate and the pixel electrode and an inorganic insulating layer disposed on the organic insulating layer; and

a thin film encapsulation layer covering the plurality of display elements and including at least one organic encapsulation layer and at least one inorganic encapsulation layer,

wherein the multilayer film includes a first groove between the opening region and the display region, and

wherein the first groove has an undercut structure.

22. The display device according to claim 21, further comprising an electronic element corresponding to the opening region.

23. A display device according to claim 22, wherein the electronic component detects and/or generates light and/or sound.

24. The display device of claim 21, wherein the at least one inorganic encapsulation layer is in direct contact with an insulating layer disposed below the organic insulating layer through the first recess.

25. The display device of claim 24, wherein the multilayer film further comprises a second groove between the open region and the first groove, and an end of the at least one organic encapsulation layer is between the first groove and the second groove.

26. The display device of claim 21, wherein the substrate has an opening passing through from a top surface of the substrate to a bottom surface of the substrate.

Technical Field

The present disclosure relates to a display device, and more particularly, to a display panel and a display device including the same.

Background

In recent years, display devices are being used in a wider variety of products. In addition, display devices are becoming thinner and lighter in weight, and thus the range of use thereof is increasing.

When the display area of a display device is increased, a wide range of sensors and other elements are being integrated into the display device.

Disclosure of Invention

A display panel includes: a substrate having an open area and a display area at least partially surrounding the open area. A plurality of display elements are arranged in the display area. Each of the plurality of display elements includes a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode. The multilayer film includes a first insulating layer disposed between the substrate and the pixel electrode and a second insulating layer disposed on the first insulating layer and having a material different from that of the first insulating layer. A thin film encapsulation layer covers the plurality of display elements and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove disposed between an opening region and a display region. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

A display panel includes a substrate having an opening region. A plurality of display elements are disposed on the substrate. The plurality of display elements surround an opening area. Each of the plurality of display elements includes a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode. The multilayer film includes a first insulating layer disposed between the substrate and the pixel electrode and a second insulating layer disposed on the first insulating layer. An encapsulation layer covers the plurality of display elements. The multilayer film includes a first groove surrounding an open region and recessed with respect to a depth direction of the multilayer film. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

A display device includes a substrate having an open region and a display region at least partially surrounding the open region. A plurality of display elements are arranged in the display area. Each display element includes a pixel electrode, a counter electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode. The multilayer film includes an organic insulating layer disposed between the substrate and the pixel electrode and an inorganic insulating layer disposed on the organic insulating layer. A thin film encapsulation layer covers the plurality of display elements and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove between the opening region and the display region. The first groove has an undercut structure.

Drawings

A more complete understanding of the present disclosure and many of the attendant aspects thereof will be more readily obtained as the same become better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

fig. 1 is a perspective view schematically illustrating a display device according to an exemplary embodiment of the present disclosure;

fig. 2A to 2D are schematic cross-sectional views illustrating a display device according to an exemplary embodiment of the present disclosure;

fig. 3 is a schematic plan view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 4 is an equivalent circuit diagram schematically illustrating a pixel of a display panel according to an exemplary embodiment of the present disclosure;

fig. 5 is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present disclosure and illustrating signal lines located in a first non-display area of the display panel;

fig. 6 is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present disclosure and illustrating a groove located in a first non-display area of the display panel;

fig. 7 is a schematic cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 8 is an enlarged cross-sectional view illustrating the organic light emitting device of fig. 7;

fig. 9A is an extracted sectional view illustrating a first groove, and fig. 9B is a sectional view illustrating a stacked structure on the first groove of fig. 9A;

fig. 10 is a schematic cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 11 is a schematic partial plan view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 12 is a plan view showing a peripheral area around an opening area;

FIG. 13 is a cross-sectional view taken along line XIII-XIII' of FIG. 12;

fig. 14 is a schematic partial plan view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 15 is a plan view showing a peripheral area around an opening area; and

fig. 16 is a sectional view taken along line XVI-XVI' of fig. 15.

Detailed Description

In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner.

Like elements may be represented by like reference numerals throughout the specification and drawings. To the extent that a detailed description of a particular element has been omitted, it may be assumed that the undescribed element is at least similar to the corresponding element that has been described elsewhere in the specification.

Although terms such as "first," "second," etc. may be used to describe various components, such components should not be limited to the above terms. The above terms are only used to distinguish one component from another.

In the following embodiments, it will be understood that when a portion such as a layer, region or element is referred to as being "on" or "over" another portion, it can be directly on or over the other portion, or intervening portions may also be present.

The size of components in the drawings may be exaggerated or reduced for convenience of explanation.

When a layer, region or element is referred to as being "connected" to another structure as described herein, it may be interpreted not only that the layer, region or element is directly connected, but also that the layer, region or element is connected through other constituent elements interposed between the layer, region or element and the other structure. For example, when a layer, region, element, or the like is described as being connected or electrically connected to another structure, the layer, region, element, or the like may be not only directly connected or electrically connected but also connected through another layer, region, element, or the like interposed between the layer, region, or element and the other structure.

Fig. 1 is a perspective view schematically illustrating a display device 1 according to an exemplary embodiment of the present disclosure.

Referring to fig. 1, the display device 1 includes a plurality of regions, for example, a first region, a second region surrounding the first region, a third region between the first region and the second region, and a fourth region surrounding the second region. The first region may correspond to an opening region RA, the second region may correspond to a display region DA, the third region may correspond to a first non-display region NDA1, and the fourth region may correspond to a second non-display region NDA 2. The display device 1 includes a display area DA from which light is emitted and a non-display area NDA from which light is not emitted. The display device 1 can display an image by using light emitted from a plurality of pixels arranged in the display area DA of the display device 1.

The display device 1 includes an opening region RA at least partially surrounded by a display region DA. Fig. 1 shows that the opening area RA is completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 surrounding an opening area RA (e.g., located between the opening area RA and the display area DA) and a second non-display area NDA2 at least partially surrounding the outside of the display area DA. The first non-display area NDA1 may completely surround the opening area RA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

Hereinafter, according to an exemplary embodiment of the present disclosure, an organic light emitting display device (organic Electroluminescence (EL) display) will be described as an example of the display device 1, but the display device according to the present disclosure is not limited thereto. For example, various types of display devices such as an inorganic Electroluminescence (EL) display, a quantum dot light emitting display, and the like can be used.

Fig. 2A to 2D are sectional views schematically illustrating the display device 1 according to an exemplary embodiment of the present disclosure, and may correspond to a section cut along line II-II' of fig. 1.

Referring to fig. 2A, the display device 1 may include a display panel 10 and electronic elements 20 corresponding to an opening region RA of the display panel 10. Various elements such as an input sensing member sensing a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may also be disposed on the display panel 10.

The display panel 10 may include a substrate 100, a display element layer 200 disposed on the substrate 100 and including display elements, and a thin film encapsulation layer 300 (e.g., an encapsulation member) covering the display element layer 200.

The substrate 100 may include a substrate including SiO₂A glass material as a main component. The display element layer 200 includes display elements (such as organic light emitting diodes OLED) arranged in the display area DA. The display element layer 200 may include various circuits and wirings electrically connected to the organic light emitting diode OLED as a display element. The thin film encapsulation layer 300 may cover the display element layer 200, thereby preventing penetration of moisture or other external contaminants into the display element layer 200. The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

As shown in fig. 2A, the display panel 10 may include an opening 10H corresponding to the opening region RA and penetrating the display panel 10. The substrate 100, the display element layer 200, and the thin film encapsulation layer 300 may include first, second, and third openings 100H, 200H, and 300H corresponding to the opening region RA, respectively. The first, second, and third openings 100H, 200H, and 300H may together form an opening 10H of the display panel 10. The first opening 100H may pass through or penetrate from the top surface of the substrate 100 to the bottom surface of the substrate 100. The second opening 200H may pass through or penetrate from the top surface of the display element layer 200 to the bottom surface of the display element layer 200. The third opening 300H may pass through or penetrate from the top surface of the thin film encapsulation layer 300 to the bottom surface of the thin film encapsulation layer 300.

The opening region RA may correspond to a position where the electronic element 20 is disposed, and thus the electronic element 20 may be disposed to correspond to the first opening 100H of the substrate 100, the second opening 200H of the display element layer 200, and the third opening 300H of the thin film encapsulation layer 300. The first opening 100H may penetrate the upper and lower surfaces of the substrate 100, and the second opening 200H may penetrate the lowermost layer to the uppermost layer of the display element layer 200. The third opening 300H may penetrate the thin film encapsulation layer 300.

The electronic component 20 may be an electronic component that detects and/or generates light and/or sound. For example, the electronic components may include a sensor that receives light such as an infrared sensor, a camera that receives light to capture an image, a sensor that measures a distance or senses a fingerprint by outputting or sensing light or sound, a compact lamp that outputs light, a speaker that outputs sound, and the like. The electronic components that detect and/or generate light may use various bands of light such as visible, infrared, and/or ultraviolet light. The opening region RA may be understood as a transmissive region through which light and/or sound output from the electronic component 20 to the outside or traveling from the outside into the electronic component 20 may be transmitted. As shown in fig. 2A, when all portions of the display panel 10 corresponding to the opening region RA are removed (for example, when the opening 10H penetrates the display panel 10), light or sound output or received by the electronic element 20 may be more effectively processed.

Although fig. 2A illustrates that the electronic element 20 is disposed under the substrate 100, the present disclosure is not limited thereto. According to an exemplary embodiment of the present disclosure, the electronic component 20 may be located within the opening 10H of the display panel 10.

Fig. 2A illustrates the substrate 100 including the first opening 100H corresponding to the opening region RA, the display element layer 200 including the second opening 200H corresponding to the opening region RA, and the thin film encapsulation layer 300 including the third opening 300H corresponding to the opening region RA. However, in fig. 2B, the substrate 100 may not include the first opening 100H. For example, there may be no opening in the substrate 100 corresponding to the electronic component 20.

Referring to fig. 2B, although the substrate 100 does not include the first opening, the display element layer 200 and the thin film encapsulation layer 300 may include the second opening 200H and the third opening 300H, respectively, and thus, the transmittance of light used by the electronic element 20 may be ensured. According to an exemplary embodiment of the present disclosure, the light transmittance in the opening region RA of the display panel 10 shown in fig. 2B may be about 50% or more, more preferably, about 70% or more, about 75% or more, about 80% or more, about 85% or more, or about 90% or more.

Referring to fig. 2C and 2D, the substrate 100 of the display panel 10 may include a polymer resin, thereby providing flexibility further compared to a glass material substrate. For example, the substrate 100 may include a first base layer 101, a first inorganic layer 102, a second base layer 103, and a second inorganic layer 104, which are sequentially stacked.

Both the first substrate layer 101 and the second substrate layer 103 may comprise a transparent polymer resin. The polymer resin may be, for example, Polyethersulfone (PES), Polyarylate (PAR), Polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), Polyimide (PI), Polycarbonate (PC), cellulose Triacetate (TAC), Cellulose Acetate Propionate (CAP), or the like.

The first inorganic layer 102 and the second inorganic layer 104 are barrier layers for preventing permeation of external foreign substances, and each of these layers may be a layer including, for example, silicon nitride (SiN)_x) And/or silicon oxide (SiO)_x) A single-layer structure or a multi-layer structure of the inorganic material of (1).

The substrate 100 including the polymer resin may include the first opening 100H corresponding to the opening region RA (as shown in fig. 2C), or may not include the first opening (as shown in fig. 2D). Alternatively, as described above, the display element layer 200 and the thin film encapsulation layer 300 may have only the second opening 200H and the third opening 300H, respectively.

Fig. 3 is a plan view schematically illustrating the display panel 10 according to an exemplary embodiment of the present disclosure, and fig. 4 is an equivalent circuit diagram schematically illustrating a pixel of the display panel 10.

Referring to fig. 3, the display panel 10 includes a plurality of pixels P arranged in the display area DA. Each pixel P may include an organic light emitting diode OLED (see fig. 4). Each pixel P may emit light of a red color, light of a green color, light of a blue color, or light of a white color through the organic light emitting diode OLED.

Referring to fig. 4, each pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst.

The second thin film transistor T2 is a switching thin film transistor and is connected to the scan line SL and the data line DL, and transmits the data voltage input via the data line DL to the first thin film transistor T1 according to the switching voltage input via the scan line SL. The storage capacitor Cst is connected to the second thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between the voltage received from the second thin film transistor T2 and the first power supply voltage ELVDD supplied to the driving voltage line PL.

The first thin film transistor T1 is a driving thin film transistor and is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a predetermined luminance via a driving current. A counter electrode (e.g., a cathode electrode) of the organic light emitting diode OLED may receive the second power supply voltage ELVSS.

Fig. 4 shows a pixel circuit PC including two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. It will be understood that the number of thin film transistors and the number of storage capacitors may vary depending on the design of the pixel circuit PC.

Referring back to fig. 3, the first non-display area NDA1 may surround the opening area RA. The first non-display area NDA1 is an area where no display element (such as an organic light emitting diode OLED) is disposed. Signal lines, which will be described in detail below, included around the opening area RA or the groove, through which signals are supplied to the pixels P may be disposed in the first non-display area NDA 1. In the second non-display region NDA2, a scan driver 1100 supplying a scan signal to each pixel P, a data driver 1200 supplying a data signal to each pixel P, a main power supply wiring through which a first power supply voltage and a second power supply voltage are supplied, and the like may be arranged.

Fig. 3 may be understood to show the substrate 100 included in the display panel 10. For example, it may be understood that the substrate 100 includes an opening region RA, a display region DA, a first non-display region NDA1, and a second non-display region NDA 2.

Fig. 5 is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present disclosure, and fig. 5 illustrates signal lines located in a first non-display area.

Referring to fig. 5, the pixels P are arranged in a display area DA surrounding the opening area RA, and the first non-display area NDA1 may be arranged between the opening area RA and the display area DA.

The pixels P may be spaced apart from each other with respect to the opening area RA. The pixels P may be spaced apart from each other above and below the opening area RA with respect to the XY plane of fig. 5. Alternatively, the pixels P may be spaced apart from each other on the left and right sides with respect to the opening area RA with respect to the XY plane of fig. 5.

A signal line for supplying a signal to the pixel P and adjacent to the opening area RA may detour around the opening area RA. Some of the data lines DL passing through the display area DA may extend in the y-direction to supply data signals to the pixels P disposed above and below the opening area RA, and may simultaneously detour along the boundary of the opening area RA in the first non-display area NDA 1. Some scan lines SL passing through the display area DA may extend in the x direction to supply scan signals to the pixels P disposed on the left or right side with respect to the opening area RA, and may simultaneously detour along the boundary of the opening area RA in the first non-display area NDA 1.

Fig. 6 is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present disclosure, and illustrates a groove located in a first non-display area.

The groove is located between the opening region RA and the display region DA. In this regard, although fig. 6 illustrates the first and second grooves G1 and G2 between the opening region RA and the display region DA, one or more grooves may be included in addition to the first and second grooves G1 and G2 according to an exemplary embodiment of the present disclosure.

Each of the first and second grooves G1 and G2 may have a ring shape completely surrounding the opening region RA in the first non-display region NDA 1. Each of the first and second grooves G1 and G2 may have a diameter greater than that of the opening region RA, and the first and second grooves G1 and G2 may be spaced apart from each other by a predetermined distance.

Fig. 7 is a cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure. Fig. 7 corresponds to a section taken along the line VII-VII' of fig. 6. Fig. 8 is an enlarged cross-sectional view illustrating the organic light emitting device of fig. 7. Fig. 9A is a sectional view showing an extracted view of the first groove G1, and fig. 9B is a sectional view showing a stacked structure on the first groove G1 of fig. 9A.

First, referring to the display area DA shown in fig. 7, the substrate 100 may include glass as described above with reference to fig. 2A and 2B, or may include an inorganic layer and a matrix layer including a polymer resin as described above with reference to fig. 2C and 2D.

The buffer layer 201 may be formed on the substrate 100. The buffer layer 201 may prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include an inorganic insulating material such as silicon nitride or silicon oxide, and may be a single-layer structure or a multi-layer structure including the above inorganic insulating material. In some exemplary embodiments of the present disclosure, the second inorganic layer 104 described with reference to fig. 2C and 2D may be understood as a sub-layer of the buffer layer 201 having a multi-layer structure.

A pixel circuit PC including a thin film transistor TFT, a storage capacitor Cst, and the like may be disposed on the buffer layer 201. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The thin film transistor TFT as shown in fig. 7 may correspond to the driving thin film transistor described with reference to fig. 4. According to an exemplary embodiment of the present disclosure, a top gate type thin film transistor in which the gate electrode GE is disposed on the semiconductor layer Act and the gate insulating layer 203 is included between the gate electrode GE and the semiconductor layer Act is illustrated. Alternatively, the thin film transistor TFT may be a bottom gate type.

The semiconductor layer Act may include polysilicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed to have a multi-layer structure or a single-layer structure of the above materials.

The gate insulating layer 203 may be interposed between the semiconductor layer Act and the gate electrode GE, and the gate insulating layer 203 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and the like.

The source electrode SE and the drain electrode DE may each include a material having high conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed to have a multi-layer structure or a single-layer structure of the above-described materials. In one exemplary embodiment of the present disclosure, both the source electrode SE and the drain electrode DE may include a multilayer structure of Ti/Al/Ti.

The storage capacitor Cst includes the lower electrode CE1 and the upper electrode CE2 that are stacked on each other, and the first interlayer insulating layer 205 interposed between the lower electrode CE1 and the upper electrode CE 2. The storage capacitor Cst may overlap the thin film transistor TFT. In this regard, fig. 7 illustrates that the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst, but the present disclosure is not limited thereto. According to an exemplary embodiment of the present disclosure, the storage capacitor Cst may not overlap the thin film transistor TFT. The storage capacitor Cst may be covered with the second interlayer insulating layer 207.

The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or the like.

The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst is covered with a first insulating layer 209. The first insulating layer 209 is a planarization insulating layer and may include an organic insulating material such as a typical general-purpose polymer (e.g., polymethyl methacrylate (PMMA) or Polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aromatic ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof. According to an exemplary embodiment of the present disclosure, the first insulating layer 209 may include polyimide. According to an exemplary embodiment of the present disclosure, the first insulating layer 209 may have a thickness of about 1.7 μm to about 2.4 μm.

The organic light emitting diode OLED is disposed on the first insulating layer 209. The pixel electrode 221 of the organic light emitting diode OLED may be disposed on the first insulating layer 209 (i.e., contacting the upper surface of the first insulating layer 209) and may be connected to the pixel circuit PC through a contact hole of the first insulating layer 209.

The pixel electrode 221 may include a material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) Indium Gallium Oxide (IGO), or Aluminum Zinc Oxide (AZO). According to an exemplary embodiment of the present disclosure, the pixel electrode 221 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a composite thereof. According to an exemplary embodiment of the present disclosure, the pixel electrode 221 may further include a reflective layer made of ITO, IZO, ZnO, or In on or under the above reflective layer₂O₃The film formed.

The second insulating layer 211 may include an opening exposing an upper surface of the pixel electrode 221 and may cover an edge of the pixel electrode 221. The second insulating layer 211 includes an inorganic insulating material. For example, the second insulating layer 211 may include silicon oxide and/or silicon nitride, and may be a single-layer structure or a multi-layer structure. The thickness of the second insulating layer 211 may be less than the thickness of the first insulating layer 209.

The intermediate layer 222 includes an emission layer 222 b. The emission layer 222b may include a polymer or a low molecular weight organic material that emits light of a predetermined color. According to an exemplary embodiment of the present disclosure, the intermediate layer 222 may include a first functional layer 222a disposed under the emission layer 222b and/or a second functional layer 222c disposed on the emission layer 222 b.

The first functional layer 222a may have a single layer structure or a multi-layer structure. For example, when the first functional layer 222a is formed of a polymer material, the first functional layer 222a may be a Hole Transport Layer (HTL) having a single-layer structure, and may include poly (3, 4-ethylenedioxythiophene) (PEDOT) or Polyaniline (PANI). When the first functional layer 222a is formed of a low molecular weight material, the first functional layer 222a may include a Hole Injection Layer (HIL) and a Hole Transport Layer (HTL).

The second functional layer 222c is optional and may be omitted. For example, when the first functional layer 222a and the emission layer 222b are formed of polymer materials, the second functional layer 222c may be formed. The second functional layer 222c may have a single-layer structure or a multi-layer structure. The second functional layer 222c may include an Electron Transport Layer (ETL) and/or an Electron Injection Layer (EIL).

Some of the layers (for example, functional layers) constituting the intermediate layer 222 may be disposed not only in the display area DA but also in the first non-display area NDA1, and the layers may be cut by the first and second grooves G1 and G2 in the first non-display area NDA1, which will be described later.

The counter electrode 223 is disposed to face the pixel electrode 221, and the intermediate layer 222 is interposed between the counter electrode 223 and the pixel electrode 221. The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a transparent electrode including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereofA layer or a translucent layer. Alternatively, the counter electrode 223 may further include a transparent layer or a semi-transparent layer including, for example, ITO, IZO, ZnO, or In₂O₃Of (2) a layer of (a).

The organic light emitting diode OLED is covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Fig. 7 shows that the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 interposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. Alternatively, the stacking order and number of the encapsulation layers may be changed.

The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include an inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon nitride, and/or silicon oxynitride, and may be formed by, for example, Chemical Vapor Deposition (CVD). The organic encapsulation layer 320 may include a polymer-based material. Examples of the polymer-based material may include acrylic resin, epoxy resin, polyimide, and polyethylene.

Referring to the first non-display area NDA1 of fig. 7, the first non-display area NDA1 may include a first sub non-display area SNDA1 relatively far from the opening area RA and a second sub non-display area SNDA2 relatively close to the opening area RA.

The first sub non-display area SNDA1 is an area through which the signal lines pass, and the data lines DL shown in fig. 7 correspond to the data lines DL bypassing the opening area RA described with reference to fig. 5.

The data lines DL may be alternately arranged with an insulating layer interposed therebetween. The adjacent data lines DL may be disposed under and over an insulating layer (e.g., the second interlayer insulating layer 207), respectively, to reduce a distance (pitch) between the adjacent data lines DL. When the distance (pitch) is reduced, the width of the first non-display area NDA1 may be reduced. Although only the data lines DL are shown in the first sub non-display area SNDA1 in fig. 7, the scan lines bypassing the opening area RA described above with reference to fig. 5 may be formed in the first sub non-display area SNDA 1.

The second sub non-display region SNDA2 may prevent permeation of external moisture traveling in the lateral direction (x-direction) of the display element layer 200 through the openings 10H, and the first and second grooves G1 and G2 are arranged in the second sub non-display region SNDA 2.

Referring to fig. 9A, a first groove G1 is formed in the multilayer film 210. Here, the multilayer film 210 may include a first insulating layer 209 as a lower insulating layer and a second insulating layer 211 as an upper insulating layer. Other insulating layers (e.g., the buffer layer 201 to the second interlayer insulating layer 207) may be disposed under the multilayer film 210.

The first groove G1 may have a predetermined depth in the thickness direction of the multilayer film 210. The first groove G1 may be formed by removing a portion of the second insulating layer 211 and a portion of the first insulating layer 209. The portion of the second insulating layer 211 and the portion of the first insulating layer 209 may be removed by an etching process. According to an exemplary embodiment of the present disclosure, the operation of etching the first insulating layer 209 to form the first hole 209H and the operation of etching the second insulating layer 211 to form the second hole 211H may be separately performed.

The first width W1 of the first hole 209H of the first insulating layer 209 may be greater than the second width W2 of the second hole 211H of the second insulating layer 211, and the first groove G1 may have an undercut structure having a lower width greater than an upper width. In this regard, as shown in fig. 9A, at the interface between the second insulating layer 211 and the first insulating layer 209, an inner side 211IE of the second insulating layer 211 facing the second hole 211H protrudes a first distance d in the lateral direction (x-direction) toward the center of the first groove G1 than the inner side 209IE of the first insulating layer 209. The first distance d may be less than the thickness t1 of the first insulating layer 209, or may be equal to or greater than the thickness t1 of the first insulating layer 209. The first distance d may be greater than the thickness of the first inorganic encapsulation layer 310 or greater than the sum of the thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. According to an exemplary embodiment of the present disclosure, the first distance d may be about 2 μm or more.

After the first groove G1 is formed in the multilayer film 210 (as shown in fig. 9A), the intermediate layer 222 and the counter electrode 223 are formed, and the intermediate layer 222 and the counter electrode 223 may be cut (e.g., separated) by the first groove G1. In this regard, fig. 9B shows that the first and second functional layers 222a and 222c and the counter electrode 223 are cut by the first groove G1.

As shown in fig. 7, the intermediate layer 222 and the counter electrode 223 are formed on the substrate 100 on which the first groove G1 is disposed. Some of the layers (for example, the first functional layer 222a and/or the second functional layer 222c) constituting the intermediate layer 222 may be integrally formed in the display area DA and the first non-display area NDA1 like the electrode 223, and the first functional layer 222a and/or the second functional layer 222c may be cut with respect to the first groove G1 when the first groove G1 is formed in the first non-display area NDA 1. Similarly, the counter electrode 223 is cut off with respect to the first groove G1.

The first inorganic encapsulation layer 310 from among the thin film encapsulation layers 300 has better step coverage than the intermediate layer 222 and the counter electrode 223, and thus, the first inorganic encapsulation layer 310 may completely cover the inner surface of the first groove G1 (as shown in fig. 9B). The first inorganic encapsulation layer 310 is continuously formed as a single structure without being cut by the undercut structure of the first groove G1. For example, the first inorganic encapsulation layer 310 may cover the inner side 211IE and the bottom surface of the second insulating layer 211 and the inner side 209IE and the bottom surface of the first insulating layer 209. Here, the first inorganic encapsulation layer 310 may be in direct contact with the upper surface of the second interlayer insulating layer 207 exposed through the first groove G1.

A layer containing an organic material among layers formed on the substrate 100 may serve as a transmission path of foreign substances such as moisture or oxygen. However, when the first insulating layer 209, which is an organic insulating layer, is cut by the first groove G1, moisture can be prevented from being transmitted in the lateral direction (x direction). Further, when the first inorganic encapsulation layer 310 is in direct contact with the second interlayer insulating layer 207, which is an inorganic insulating layer exposed through the first groove G1, since all layers including an organic material are covered, moisture transmission in a lateral direction through the layer having an organic material may be prevented. Further, as described above, since the first functional layer 222a and/or the second functional layer 222c may be cut with respect to the first groove G1 and the second groove G2, it is possible to prevent moisture from being transmitted in the lateral direction (x direction).

A thickness of the first inorganic encapsulation layer 310 (e.g., a thickness in a direction perpendicular to the substrate 100 (z direction)) may be less than the thickness t1 of the first insulating layer 209. A portion of the first groove G1 may be filled with the organic encapsulation layer 320 on the first inorganic encapsulation layer 310.

Although fig. 9A and 9B illustrate a structure focused on the first groove G1, the second groove G2 may have a structure equivalent to that of the first groove G1.

Referring to fig. 7, the second groove G2 also has an undercut structure with a lower width greater than an upper width, and the detailed structure of the second groove G2 is the same as that described above with reference to fig. 9A. The intermediate layer 222 and the counter electrode 223 may be cut not only by the first groove G1 but also by the second groove G2. As described above with reference to the first groove G1, since the inner surface of the second groove G2 is completely covered by the first inorganic encapsulation layer 310, and the first inorganic encapsulation layer 310 is in direct contact with the second interlayer insulating layer 207 exposed through the second groove G2, a transmission path through an organic material may also be effectively blocked by using the second groove G2.

Unlike the upper portion of the first groove G1, in which the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 are, for example, in the second hole 211H of the second insulating layer 211, the organic encapsulation layer 320 may be omitted from the second groove G2.

The organic encapsulation layer 320 may be formed by applying, for example, a monomer on the substrate 100 and then hardening it, and when the organic encapsulation layer 320 forms the side of the opening 10H, moisture transmission may occur through the organic encapsulation layer 320. To prevent this, a portion of the organic encapsulation layer 320 (e.g., a portion corresponding to the region HA between the opening region RA and the first groove G1) may be removed by ashing or the like, and thus, the end portion 320E of the organic encapsulation layer 320 may be disposed between the first groove G1 and the second groove G2. Since the end portion 320E of the organic encapsulation layer 320 is disposed closer to the display area DA than the end portion of the first inorganic encapsulation layer 310 and the end portion of the second inorganic encapsulation layer 330, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may directly contact each other in the above-mentioned area HA. For example, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may also contact each other over the upper surface of the second insulating layer 211 and within the second groove G2.

During the operation of forming the organic encapsulation layer 320, when the organic material in the region HA is removed, the organic material existing in the second groove G2 is also removed in the ashing process. However, the organic residue 325 may remain under the eaves (e.g., overhangs) of the second insulating layer 211 in the undercut structure of the second groove G2. According to an exemplary embodiment of the present disclosure, according to the conditions of the ashing process and the like, as shown in fig. 10, no organic residue may be left in the second groove G2.

Although fig. 7 to 10 illustrate a structure in which an opening is formed in the substrate 100, the present disclosure is not limited to the structure as described above. The structures described with reference to fig. 7 to 10 and the structures described below with reference to fig. 11 to 16 may also be applied to an exemplary embodiment in which an opening is not formed in the substrate 100, for example, to the display panel 10 shown in fig. 2B and 2D and embodiments derived therefrom.

Fig. 11 is a schematic partial plan view illustrating a display panel 10' according to an exemplary embodiment of the present disclosure. Fig. 12 is a plan view showing a peripheral region around the opening region RA of fig. 11. Fig. 13 is a sectional view showing a peripheral region around the opening region taken along line XIII-XIII' of fig. 12. To the extent that detailed descriptions of the elements and structure of the display panel 10' of the present embodiment are omitted, it may be assumed that the omitted details are at least similar to those of the display panel 10 described above with respect to fig. 3.

Referring to fig. 11 and 12, the opening area RA of the display panel 10' may be partially surrounded by the display area DA. The pixels P may be spaced apart from each other on left and right sides with respect to the opening area RA. The scan lines SL transmitting scan signals to the pixels P on the left side of the opening area RA and the pixels P on the right side of the opening area RA may detour around the opening area RA in the first non-display area NDA 1.

The opening region RA may be surrounded (at least partially) by the first and second grooves G1 and G2. Fig. 12 shows that the first grooves G1 surround a portion of the opening area RA and the second grooves G2 completely surround the opening area RA, according to an exemplary embodiment of the present disclosure. The first groove G1 may surround a portion of the opening area RA, and both ends of the first groove G1 may be connected to the third groove G3 included in the second non-display area NDA 2. The second groove G2 may completely surround the opening area RA and may be connected to the fourth groove G4 included in the second non-display area NDA 2. The third groove G3 and the fourth groove G4 may extend along the boundary of the substrate 100.

The scan lines SL of the first sub non-display region SNDA1 shown in fig. 13 correspond to the scan lines bypassing the opening region RA described above with reference to fig. 12. The first and second grooves G1 and G2 are included between the scan line SL and the opening area RA. To the extent details regarding the arrangement of first groove G1 and second groove G2 have been omitted, it may be assumed that the details not described are at least similar to those of the corresponding elements already described elsewhere in the specification.

Fig. 14 is a schematic partial plan view illustrating the display panel 10 ″ according to an exemplary embodiment of the present disclosure. Fig. 15 is a plan view showing a peripheral region around the opening region RA of fig. 14. Fig. 16 is a sectional view of the peripheral region around the opening region, taken along line XVI-XVI' of fig. 15. To the extent that detailed descriptions of specific elements and structures of the display panel 10 "are omitted, it may be assumed that the elements and structures not described are at least similar to the corresponding elements and structures of the display panel 10 that have been described elsewhere in the specification with reference to fig. 3-10.

Referring to fig. 14 and 15, the opening area RA of the display panel 10 ″ may be partially surrounded by the display area DA. The pixels P may be spaced apart from each other above and below with respect to the opening area RA with respect to the XY plane of fig. 14 and 15. The data lines DL, through which data signals are transmitted to the pixels P above the opening area RA and the pixels P below the opening area RA, may detour around the opening area RA in the first non-display area NDA 1.

The opening region RA may be at least partially surrounded by the first and second grooves G1 and G2. Fig. 15 shows that the first grooves G1 surround a portion of the opening area RA and the second grooves G2 completely surround the opening area RA, according to an exemplary embodiment of the present disclosure. The first groove G1 may surround a portion of the opening area RA, and both ends of the first groove G1 may be connected to the third groove G3 included in the second non-display area NDA 2. The second groove G2 may completely surround the opening area RA and may be connected to the fourth groove G4 included in the second non-display area NDA 2. The third groove G3 and the fourth groove G4 may extend along the boundary of the substrate 100.

The data line DL of the first sub non-display region SNDA1 shown in fig. 16 corresponds to the data line bypassing the opening region RA described above with reference to fig. 15. The first and second grooves G1 and G2 are included between the data line DL and the opening area RA. The structure of the first groove G1 and the second groove G2 and the elements surrounding the first groove G1 and the second groove G2 are at least similar to the structure of the first groove G1 and the second groove G2 and the elements surrounding the first groove G1 and the second groove G2 described above.

According to the exemplary embodiments of the present disclosure, moisture transmission toward display elements in a display area in a lateral direction may be effectively blocked and prevented by the groove formed in the multi-layered film surrounding the opening area and having the undercut structure, and the prevention of moisture transmission may be achieved regardless of the type of the substrate.

Although various exemplary embodiments of the present disclosure have been described herein with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.