阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 綦振瀛 邹承翰 陈仕鸿 于 2019-03-25 设计创作，主要内容包括：本揭露提供半导体接触结构、包含半导体接触结构的半导体装置及其制造方法。在实施方式中,半导体装置包含基板上的通道层；通道层上的介面层,其中介面层包含钛(Ti)且接触通道层；以及在介面层上的接触金属层,其中接触金属层包含铝硅铜合金(AlSiCu)。(The present disclosure provides semiconductor contact structures, semiconductor devices including semiconductor contact structures, and methods of making the same. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, wherein the interface layer comprises titanium (Ti) and contacts the channel layer; and a contact metal layer on the interface layer, wherein the contact metal layer comprises an aluminum silicon copper alloy (AlSiCu).)

1. A semiconductor device, comprising:

a channel layer on a substrate;

an interface layer on the channel layer, wherein the interface layer comprises titanium (Ti) and contacts the channel layer; and

a contact metal layer on the interface layer, wherein the contact metal layer comprises an aluminum silicon copper alloy (AlSiCu).

Technical Field

The present disclosure relates to a semiconductor device.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing layers of insulating or dielectric materials, conductive materials, and semiconductor materials on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit elements and components thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size shrinks, other problems arise that should be addressed.

Disclosure of Invention

According to some embodiments, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer being in contact with the channel layer; a contact metal layer on the interface layer, the contact metal layer comprising an aluminum silicon copper alloy (AlSiCu).

Drawings

The aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, the various features of the drawings are not drawn to scale. In fact, the dimensions of the features may be arbitrarily scaled for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of a semiconductor substrate, according to some embodiments of the present disclosure;

FIG. 2 is a schematic cross-sectional view illustrating the formation of a dielectric layer and a patterned photoresist according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic cross-sectional view of an ion implantation process according to some embodiments of the present disclosure;

FIG. 4 is a schematic cross-sectional view illustrating the removal of the mask layer and the patterned photoresist according to some embodiments of the present disclosure;

FIG. 5 is a schematic cross-sectional view illustrating the formation of a hard mask layer and a patterned photoresist according to some embodiments of the present disclosure;

FIG. 6 is a schematic cross-sectional view illustrating etching of a channel layer and a buffer layer according to some embodiments of the present disclosure;

FIG. 7 is a schematic cross-sectional view illustrating the removal of the hard mask layer and the patterned photoresist according to some embodiments of the present disclosure;

FIG. 8 is a schematic cross-sectional view illustrating the formation of a gate dielectric layer according to some embodiments of the present disclosure;

FIG. 9 is a schematic cross-sectional view illustrating the formation of a metal gate layer according to some embodiments of the present disclosure;

FIG. 10 illustrates a cross-sectional view of forming a metal stack, according to some embodiments of the present disclosure;

FIG. 11 is a schematic cross-sectional view illustrating the formation of an inter-layer dielectric layer according to some embodiments of the present disclosure;

12A-12B illustrate cross-sectional views of openings formed in an inter-layer dielectric layer, according to some embodiments of the present disclosure;

FIG. 13 is a schematic cross-sectional view illustrating the formation of a conductive liner according to some embodiments of the present disclosure;

FIG. 14 is a schematic cross-sectional view illustrating the formation of a conductive fill material according to some embodiments of the present disclosure;

FIGS. 15A-15C are schematic cross-sectional views illustrating the formation of a conductive contact according to some embodiments of the present disclosure;

FIG. 16 is a schematic perspective view of a transistor including a conductive contact according to some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the description that a first feature is formed over or on a second feature encompasses embodiments in which the first and second features are in direct contact, as well as embodiments in which other features are formed between the first and second features such that the first and second features are not in direct contact. Moreover, in various embodiments, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, the spatially relative terms, such as "below", "…", "below", "above", "…", "above", and the like, are used for ease of describing the relationship of the elements or features and other elements or features depicted in the drawings. Spatially relative terms may encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide conductive contacts that may be used in planar metal-oxide-semiconductor field-effect transistors (MOSFETs), fin-field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA FETs), or the like, as well as processes for forming the same. The conductive contact may include a titanium (Ti) layer and an aluminum silicon copper (AlSiCu) layer on the titanium layer. The conductive contact may be in contact with a channel layer, wherein the channel layer is disposed on a transition layer, wherein the transition layer is disposed on the semiconductor substrate. The channel layer may include indium gallium arsenide (InGaAs), the buffer layer may include indium aluminum arsenide (InAlAs), and the semiconductor substrate may include indium phosphide (InP). According to embodiments of the present application, the conductive contacts may be formed of a material compatible with complementary metal-oxide-semiconductor (CMOS) fabrication procedures as well as silicon-based MOSFET fabrication procedures. Because the conductive contacts of the present application are gold-free, the manufacturing costs of the conductive contacts are reduced. In addition, the conductive contact may have a low characteristic contact resistance (specific contact resistance) and provide an ohmic contact. The conductive contact can be used in tunneling field-effect transistors (TFETs), planar metal-oxide-semiconductor field-effect transistors (MOSFETs), fin-type field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA FETs), and the like.

Referring to fig. 1, a substrate 102 has a buffer layer 104 and a channel layer 106 disposed thereon. The substrate 102 may comprise a semiconductor material and may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor on insulator layerA bulk-on-insulator (SOI) substrate or a strained semiconductor-on-insulator (SSOI) substrate. The semiconductor material of the substrate 102 may comprise a first semiconductor material, for example a group IV element, such as germanium or silicon. In some embodiments, the semiconductor material of the substrate 102 may comprise indium phosphide (InP), silicon germanium (Si)_xGe_(1-x)) Silicon (Si), germanium (Ge), silicon carbide (SiC), sapphire (Al)₂O₃) Combinations or the like thereof. The substrate 102 may be a multilayer or gradient substrate.

The buffer layer 104 may be made of a material having a high resistivity and may be used to isolate the channel layer 106 and subsequently formed transistors from the substrate 102 and other devices on the substrate 102. For example, the buffer layer 104 may have a resistivity greater than about 10⁵Ω · cm, e.g. about 10⁶Omega cm. The material of the buffer layer 104 may be, for example, Al_xGa_(1-x)Sb、In_xGa_(1-x)As、In_xGa_(1-x)P、In_xAl_(1-x)As、In_xGa_(1-x)N、Al_xGa_(1-x)N、Si_xGe_(1-x)、Al_xSb_(1-x)、Ga_xSb_(1-x)Alloys, combinations or multiple layers thereof; or similar materials. In at least one embodiment, the buffer layer 104 may comprise inaias. The buffer layer 104 may be formed on the substrate 102 by epitaxial growth, such as Molecular Beam Epitaxy (MBE), Vapor Phase Epitaxy (VPE), or Liquid Phase Epitaxy (LPE), Chemical Vapor Deposition (CVD), a combination thereof, or any suitable deposition process; the chemical vapor deposition can be, for example, Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Reduced Pressure Chemical Vapor Deposition (RPCVD). The buffer layer 104 may have a thickness between about 0.5 microns and about 2.0 microns, such as about 0.6 microns.

As will be discussed in more detail belowIn various embodiments, a portion of the channel layer 106 may be used to form a channel of a transistor. The channel layer 106 may comprise a semiconductor material comprising indium gallium arsenide (In)_xGa_(1-x)As), indium gallium phosphide (In)_xGa_(1-x)P), indium aluminum arsenide (In)_xAl_(1-x)As), indium gallium nitride (In)_xGa_(1-x)N), aluminum gallium nitride (Al)_xGa_(1-x)N), silicon germanium (Si)_xGe_(1-x)) Indium arsenide (In)_xAs_(1-x)) Combinations or layers thereof, and the like. The channel layer 106 may be formed on the substrate 102 by epitaxial growth (e.g., molecular beam epitaxy, vapor phase epitaxy, or liquid phase epitaxy) or chemical vapor deposition (e.g., metal organic chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition), a combination thereof, or any other suitable deposition process. The channel layer 106 may have a thickness of less than about 200 nanometers, such as about 190 nanometers or about 167.9 nanometers, or a thickness of less than about 100 nanometers, such as about 50 nanometers.

The material of the channel layer 106 may be undoped. In some embodiments, the channel layer 106 may be lightly doped (e.g., the channel layer 106 may have less than about 10 a)¹⁷cm^-3Doping concentration of). For example, in embodiments where an n-type device is formed on the substrate 102, the channel layer 106 may be lightly p-type doped. In embodiments where a p-type device is formed on the substrate 102, the channel layer 106 may be lightly n-doped. The n-type dopant ions that may Be implanted into channel layer 106 include silicon (Si), germanium (Ge), tin (Sn), etc., and the p-type dopant ions that may Be implanted into channel layer 106 include beryllium (Be), zinc (Zn), carbon (C), etc.

In at least one embodiment, the substrate 102 may comprise indium phosphide (InP), the buffer layer 104 may comprise indium aluminum arsenide (InAlAs), and the channel layer 106 may comprise indium gallium arsenide (InGaAs). As such, the materials of the substrate 102, the buffer layer 104, and the channel layer 106 may be lattice matched.

In fig. 2, a first dielectric layer 108 and a first photoresist 110 are formed on the channel layer 106. The first dielectric layer 108 may be used to prevent postDamage to the underlying channel layer 106 during a subsequent ion implantation, such as the ion implantation process 112 described below with reference to fig. 3. The first dielectric layer 108 may be made of silicon dioxide (SiO)₂) Or the like. The first dielectric layer 108 may be deposited using a deposition process such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), combinations thereof, and the like. The first dielectric layer 108 may have a thickness between about 10 nanometers and about 50 nanometers, such as about 20 nanometers.

As shown in fig. 2, a first photoresist 110 is then formed on the first dielectric layer 108. The first photoresist 110 may be deposited using a spin-on technique or the like. The first photoresist 110 may be patterned using a patterned energy source (e.g., a patterned light source, an electron beam (e-beam) source, etc.) to expose the first photoresist 110 and exposing the patterned first photoresist 110 to a developer. As shown in fig. 2, the first photoresist 110 may be patterned to form openings that expose the first dielectric layer 108.

In fig. 3, an ion implantation process 112 is performed on the first photoresist 110 and the first dielectric layer 108. Ions may pass through the first dielectric layer 108 and may be implanted into the channel layer 106 to form source/drain regions 114. The portion of the channel layer 106 disposed between the source/drain regions 114 may form a channel region 115. In embodiments where an n-type device is formed on the substrate 102, the ion implantation process 112 may implant n-type dopant ions, such as silicon (Si), selenium (Se), tin (Sn), etc., into the channel layer 106. In embodiments where p-type devices are formed on the substrate 102, the ion implantation process 112 may ion implant p-type dopants, such as beryllium (Be), zinc (Zn), etc., into the channel layer 106.

The ion implantation process 112 may be performed using an energy in a range from about 7.5keV to about 37.5keV, such as about 15keV or about 25keV, at a dose in a range from about 5 x10¹³Ion/cm²To about 7.5X 10¹⁴Ion/cm²E.g. about 1X10¹⁴Ion/cm²Or about 5X 10¹⁴Ion/cm². The ion implantation process 112 may be performed at a temperature of about 500 c to about 800 c. In some embodiments, the channelThe doping concentration of the region of the layer 106 exposed to the ion implantation process 112 may be about 2.0 x10¹⁸cm^-3And about 6.2X 10¹⁸cm^-3Within a range of, for example, about 4.1X 10¹⁸cm^-3. In at least one embodiment, silicon may be implanted in the channel layer 106 such that the silicon ion concentration in the exposed portions of the channel layer is about 1x10¹⁸cm^-3And about 1X10²⁰cm^-3In the meantime.

Thus, an ion implantation process 112 is used to form source/drain regions 114. After the ion implantation process 112, the source/drain regions 114 may have an increased electron concentration and a reduced contact resistance as compared to unexposed portions of the channel layer 106. The channel region 115 disposed between the source/drain regions 114 may serve as a channel for a subsequently formed transistor.

After the ion implantation process 112, the implanted ions may be activated by a Rapid Thermal Annealing (RTA) process (not separately shown). The rapid thermal annealing process may be performed at a temperature of about 500 ℃ to about 800 ℃, such as about 650 ℃, for a time of about 5 seconds to about 100 seconds, such as about 30 seconds. The rapid thermal annealing process may be performed in nitrogen (N)₂) The process is carried out in the ambient environment.

In fig. 4, the first dielectric layer 108 and the first photoresist 110 are removed from over the channel layer 106 after the rapid thermal anneal process. The first dielectric layer 108 and the first photoresist 110 may be removed by a suitable etch process. In some embodiments, the etching process may be an isotropic etching process, such as a wet etching process or a chemical etching process. In other embodiments, the etching process may be an anisotropic etching process, such as a dry etching process. In at least one embodiment, the first dielectric layer 108 and the first photoresist 110 may be removed by a wet etch process using an etchant including hydrofluoric acid (HF), such as diluted hydrofluoric acid (dHF). In dilute hydrofluoric acid, the hydrofluoric acid may be diluted in deionized water (DIW) at a ratio of about 1:10 (HF: DIW).

In fig. 5, on channel layer 106 and source/drain regions 114,a second dielectric layer 116 and a second photoresist 118 are formed. The second dielectric layer 116 may be a hard mask layer. The second dielectric layer 116 may be made of silicon dioxide (SiO)₂) Silicon nitride (SiN), combinations thereof or multiple layers thereof, and the like. The second dielectric layer 116 may be deposited on the channel layer 106 and the source/drain regions 114 using a deposition process such as atomic layer deposition, physical vapor deposition, Chemical Vapor Deposition (CVD), a combination thereof, or the like. The second dielectric layer 116 may have a thickness between about 20 nanometers and about 60 nanometers, such as about 40 nanometers.

A second photoresist 118 may be deposited on the second dielectric layer 116 using spin-on techniques and the like. The second photoresist 118 may be patterned by exposing the second photoresist 118 to a patterned energy source (e.g., a patterned light source, an electron beam source, etc.) and exposing the patterned second photoresist 118 to a developer. As shown in fig. 5, the second photoresist 118 may be patterned to cover the source/drain regions 114 and the channel regions formed between the source/drain regions 114.

After patterning the second photoresist 118, the second dielectric layer 116 may be etched through the openings formed in the second photoresist 118. The second dielectric layer 116 may be etched by any suitable etching process, such as a dry etching process. In some embodiments, the second dielectric layer 116 may be etched by a dry etching process, such as reactive-ion etching (RIE), neutral-beam etching (NBE), combinations thereof, and the like. The etch process used to etch the second dielectric layer 116 may be anisotropic.

In fig. 6, the channel layer 106 and the buffer layer 104 are etched. As shown in fig. 6, the channel layer 106 may be etched to leave the source/drain regions 114 and the channel region 115. Any suitable etch process may be used to etch the channel layer 106 and the buffer layer 104. The etching process may be an anisotropic etching process, such as a dry etching process. In some embodiments, the channel layer 106 and the buffer layer 104 may be etched by a dry etching process, such as reactive ion etching, neutral beam etching, combinations thereof, and the like. The channel layer 106 and the buffer layer 104 may be etched by the same etch process as the second dielectric layer 116, and in some embodiments, the second dielectric layer 116, the channel layer 106, and the buffer layer 104 may be etched simultaneously.

As shown in fig. 6, a portion of the buffer layer 104 may remain above the substrate 102 in the region exposed to the etching process and outside the region covered by the second photoresist 118 and the second dielectric layer 116. The portion of the buffer layer 104 disposed outside the area covered by the second photoresist 118 may be used to isolate subsequently formed devices from other devices formed on the substrate 102.

In fig. 7, the second dielectric layer 116 and the second photoresist 118 above the channel layer 106 are removed. The second dielectric layer 116 and the second photoresist 118 may be removed by the same etching process as the first dielectric layer 108 and the first photoresist 110 or a similar etching process. The etching process used to remove the second dielectric layer 116 and the second photoresist 118 may also be used to clean the surface of the structure shown in fig. 7 and remove native oxide formed on the surface of the structure shown in fig. 7. For example, a wet etch process using an etchant comprising hydrofluoric acid (e.g., dHF) may be used to remove any native oxide formed on the second dielectric layer 116, the second photoresist 118, and the channel layer 106 or the buffer layer 104. In dHF, the hydrofluoric acid may be diluted in deionized water at a ratio of about 1:10 (HF: DIW).

In some embodiments, the channel layer 106 may be formed of germanium (Ge) or the like. In embodiments where channel layer 106 comprises germanium, channel layer 106 may be subjected to a rapid thermal oxidation process to form a conformal oxide layer (not separately shown) on the surfaces of channel layer 106 and buffer layer 104. This step may be optional.

The surfaces of the channel layer 106 and the buffer layer 104 may then be subjected to a plasma treatment, such as a nitrogen plasma. A nitrogen plasma may be used to nitride the surfaces of the channel layer 106 and the buffer layer 104. This step of nitridizing the surfaces of the channel layer 106 and the buffer layer 104 reduces the interface state density between the channel layer 106 and the buffer layer 104, and then forming the gate dielectric layer 120 (discussed below with reference to fig. 8) to improve the interface between the channel layer 106 and the buffer layer 104 and the gate dielectric layer 120.

In fig. 8, a gate dielectric layer 120 is formed over the channel layer 106 and the buffer layer 104. GridThe pole dielectric layer 120 may be a high-k (dielectric constant) dielectric layer, such as HfO₂、Al₂O₃、LaO₂、TiO₂、HfZrO、Ta₂O₃、HfSiO₄、ZrO₂、ZrSiO₂Combinations thereof, or other suitable materials. As shown in fig. 8, the gate dielectric layer 120 may be deposited by a conformal deposition process. For example, the gate dielectric layer 120 may be deposited by chemical vapor deposition, atomic layer epitaxy, etc. Gate dielectric layer 120 may have a thickness between about 2.5 nanometers and about 7.5 nanometers, such as about 5 nanometers.

In fig. 9, a metal gate 122 is formed on the gate dielectric layer 120. The metal gate 122 may be formed of titanium nitride (TiN). In some embodiments (not separately shown), the metal gate 122 may include a work function adjusting layer and a conductive material formed on the work function adjusting layer. The work function adjusting layer may be formed of TiN, TSN, WN, WCN, AlN, TaAlC, TiAl, TiAlN, WAlN, other suitable materials, or combinations thereof. The conductive material may be formed of W, Co, Ru, Al, or other suitable material. The metal gate 122 may be formed by a physical vapor deposition process, such as sputtering. The metal gate 122 may have a thickness between about 37.5 nanometers and about 112.5 nanometers, such as about 75 nanometers.

After depositing the metal gate 122, the resulting structure may be subjected to a Post Metal Anneal (PMA) process. The post-metal annealing process may be performed at a temperature of about 200 c to about 400 c, such as about 300 c. The post-metal anneal process may be performed in the presence of a forming gas (e.g., nitrogen (N)₂) And hydrogen (H)₂) Mixtures of (b) and the like. The post-metal anneal process improves the characteristics of the resulting structure by reducing boundary traps near the interface of the gate dielectric layer 120.

In fig. 10, portions of metal gate 122 and gate dielectric layer 120 are removed to form a gate stack. The gate stack includes a metal gate 122 and a gate dielectric layer 120. The gate stack may be patterned by depositing a photoresist (not separately shown) on the metal gate 122, exposing the photoresist to a patterned energy source (e.g., a patterned light source, an electron beam source, etc.), developing the photoresist, and etching the metal gate 122 and the gate dielectric layer 120 through the photoresist. The metal gate 122 and the gate dielectric layer 120 may be etched by a dry etching process, such as reactive ion etching, neutral beam etching, combinations thereof, or other similar processes. The etch process used to etch the metal gate 122 and the gate dielectric layer 120 may be anisotropic.

In fig. 11, a third dielectric layer 124 is formed over the gate stack, the channel layer 106, and the buffer layer 104. The third dielectric layer 124 may be an inter-layer dielectric (ILD) layer. The third dielectric layer 124 may be formed of a dielectric material having a low dielectric constant (e.g., a low-k material). For example, the third dielectric layer 124 may be made of silicon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Combinations or layers thereof, and the like. The third dielectric layer 124 may be deposited using a conformal deposition process, such as atomic layer deposition, physical vapor deposition, chemical vapor deposition, combinations thereof, or the like. The third dielectric layer 124 may have a thickness between about 40 nanometers and about 120 nanometers, such as about 80 nanometers.

In fig. 12A, an opening 126 is formed in the third dielectric layer 124. The opening 126 may extend through the third dielectric layer 124 to expose a portion of the source/drain region 114. An opening 126 may be formed by depositing a photoresist (not separately shown) on the third dielectric layer 124, exposing the photoresist to a patterned energy source (e.g., a patterned light source, an electron beam source, etc.), developing the photoresist, and etching the third dielectric layer 124 through the photoresist. The third dielectric layer 124 may be etched by a dry etching process, such as reactive ion etching, neutral beam etching, combinations thereof, or other similar processes. The etch process used to etch the third dielectric layer 124 may be anisotropic. Opening 126 may have a width W1 of between about 1 micron and about 3 microns, such as about 2 microns. Opening 126 may also have a length (not separately shown) of between about 1.5 microns and about 4.5 microns, such as about 3 microns.

As shown in fig. 12B, in some embodiments, the opening 126 may have sloped sidewalls (tapered sidewalls). In other embodiments, the sidewalls of the opening 126 may be reverse tapered (reversed tapered), have curved sidewalls, and the like. The opening 126 may have a square shape, a rectangular shape, a circular shape, an oval shape, or the like in plan view.

In fig. 13, a conductive liner 128 is deposited over the third dielectric layer 124 and in the opening 126. The conductive liner 128 may comprise a conductive material, such as titanium (Ti). The conductive liner 128 may be deposited by a conformal deposition process. For example, the conductive liner 128 may be deposited by a physical vapor deposition process, such as sputtering. The conductive liner 128 may have a thickness between about 0.1 nanometers and about 100 nanometers, such as about 10 nanometers or about 16.94 nanometers.

In fig. 14, a conductive fill material 130 is deposited over the conductive liner 128. The conductive fill material 130 can fill the remainder of the opening 126 as shown in fig. 14. The conductive fill material 130 can comprise a conductive material, such as aluminum silicon copper (AlSiCu). The conductive fill material 130 may be deposited by a conformal deposition process. For example, the conductive fill material 130 may be deposited by a physical vapor deposition process, such as sputtering. The conductive fill material 130 may have a thickness between about 0.1 nanometers and about 1000 nanometers, such as about 200 nanometers or about 115.20 nanometers.

In some embodiments, the conductive fill material 130 may be formed of AlSiCu, which has the formula Al_(1-x-y)Si_xCu_yWherein x is between about 1 atomic percent and about 2 atomic percent and y is between about 0.5 atomic percent and about 4 atomic percent. In other embodiments, x is about 0 atomic percent and y is about 0.5 atomic percent to about 4 atomic percent. Increasing the copper concentration in the conductive fill material 130 may reduce the resistivity of the fill material 130 while reducing the thermal stability of the conductive fill material 130. Likewise, increasing the concentration of silicon in the conductive fill material 130 may increase the resistivity of the fill material 130 while increasing the thermal stability of the conductive fill material 130.

Still further embodiments may include additional conductive layers (shown as conductive layer 129 in fig. 15C), such as a layer of nickel (Ni) or other conductive material, disposed on the conductive liner 128 and the conductive filler material 130. The additional conductive layer may be deposited by a conformal deposition process. For example, the additional conductive layer may be deposited by a physical vapor deposition process, such as sputtering. This additional conductive layer may have a thickness between about 0.1 nanometers and about 100 nanometers. The additional conductive layer may increase the thermal stability of subsequently formed source/drain contacts (discussed below with reference to fig. 15C).

In fig. 15A, portions of the conductive liner 128 and conductive fill material 130 are removed to form source/drain contacts. The source/drain contacts comprise a conductive liner and a conductive fill material (in some embodiments, an additional conductive layer is also included). The source/drain contacts may be patterned by depositing photoresist (not separately shown) on the conductive fill material 130, exposing the photoresist to a patterned energy source (e.g., a patterned light source, an electron beam source, etc.), developing the photoresist, and etching the conductive fill material 130 and the conductive liner 128 through the photoresist. The conductive fill material 130 and the conductive liner 128 may be etched by a dry etch process, such as reactive ion etching, neutral beam etching, combinations thereof, and the like. The etching process used to etch the conductive fill material 130 and the conductive liner 128 may be anisotropic.

The source/drain contacts may have a low contact resistance. For example, the source/drain contacts may have a contact resistance between about 0.0195 Ω · mm and about 0.0585 Ω · mm, such as about 0.039 Ω · mm. The source/drain contacts may also have a low characteristic contact resistivity. For example, the source/drain contacts may have a width of about 1.425 × 10^-7Ω·cm²And about 4.275X 10^-7Ω·cm²Characteristic contact resistivity therebetween, e.g. about 2.85 x10^-7Ω·cm². As shown in fig. 15A, an upper portion of the source/drain contact (e.g., the portion of the source/drain contact disposed above the third dielectric layer 124) may have a width greater than the width W1 of the opening 126. As described above, the upper portions of the source/drain contacts may also have a length (not separately shown) greater than the length of the openings 126.

In some embodiments, the third dielectric layer 124 may not be deposited prior to forming the conductive liner 128 and the conductive fill material 130, and the conductive liner 128 and the conductive fill material 130 may be deposited directly on the source/drain regions 114. In these embodiments, the conductive liner 128 and the conductive fill material 130 may be etched to form source/drain contacts, and an interlayer dielectric layer may be deposited around the source/drain contacts. In still further embodiments, the source/drain contacts may further include one or more layers of platinum (Pt) deposited on the conductive fill material.

As shown in fig. 15B, the source/drain contacts, including the conductive liner 128 and the conductive fill material 130, may have any suitable shape, such as a tapered shape in the region extending through the third dielectric layer 124. In various other embodiments, the source/drain contact portions extending through the third dielectric layer 124 may have an inverted conical shape, curved sidewalls, or the like. The top portions of the source/drain contacts extending over the third dielectric layer 124 may have rounded corners, sloped sidewalls, curved sidewalls, reverse sloped sidewalls, and the like. Furthermore, the top of the source/drain contacts may have any suitable shape in top view, such as square, rectangular, circular, oval, and the like.

As shown in fig. 15C, the source/drain contacts may also include a conductive layer 129 disposed between the conductive fill material 130 and the conductive liner 128. The conductive layer 129 may be formed of nickel (Ni) or the like. The conductive layer 129 may have a thickness between about 0.1 nanometers and about 100 nanometers and may increase the thermal stability of the source/drain contacts.

Fig. 16 shows a perspective view of the transistor structure of fig. 15A. As shown in fig. 16, the transistor structure includes a substrate 102, a buffer layer 104 over the substrate 102, a channel layer 106 (including source/drain regions 114 and a channel region 115) over the buffer layer 104, and a gate stack (including a gate dielectric layer 120 and a metal gate 122) over the channel layer 106. The third dielectric layer 124 extends over the top surface of the buffer layer 104 and along the sidewalls of the buffer layer 104, the channel layer 106, and the gate stack. The source/drain contacts, which include a conductive liner 128 and a conductive fill material 130, extend through the third dielectric layer to contact the source/drain regions 114.

In accordance with the above-described embodiments, a semiconductor device is formed that produces gold-free (Au-free), low characteristic contact resistivity source/drain contacts that can be used with InGaAs semiconductor materials. Because the source/drain contacts are gold-free, the manufacturing cost of the contacts is reduced. Furthermore, since titanium and aluminum silicon copper are commonly used materials in silicon-based fabrication technologies, the above-described source/drain contacts may be integrated with existing fabrication technologies (e.g., the source/drain contacts may be compatible with silicon MOSFET) technologies, CMOS technologies, etc.). The source/drain contacts may have a low characteristic contact resistivity and may not require a post-metal anneal after the source/drain contacts are formed.

According to some embodiments, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer being in contact with the channel layer; a contact metal layer on the interface layer, the contact metal layer comprising an aluminum silicon copper alloy (AlSiCu). In one embodiment, the channel layer comprises indium gallium arsenide (InGaAs). In one embodiment, the channel layer includes indium arsenide (InAs), indium gallium phosphide (InGaP), indium aluminum arsenide (InAlAs), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or silicon germanium (SiGe). In one embodiment, the substrate comprises indium phosphide (InP). In one embodiment, the substrate comprises silicon germanium (SiGe), gallium arsenide (GaAs), silicon (Si), germanium (Ge), silicon carbide (SiC) or sapphire (Al)₂O₃). In one embodiment, the material of the contact metal layer is of the formula Al_(1-x-y)Si_xCu_yExpressed, x is about 1 atomic percent to about 2 atomic percent and y is between about 0.5 atomic percent to about 4 atomic percent. In one embodiment, the material of the contact metal layer is represented by the formula Al_(1-x-y)Si_xCu_yExpressed, x is about 0 atomic percent and y is between about 0.5 atomic percent and about 4 atomic percent.

According to another embodiment, a semiconductor device includes a substrate; a buffer layer over the substrate; a channel layer on the buffer layer; a conductive contact in contact with the via layer, the conductive contact comprising a conductive liner comprising titanium (Ti) and a conductive filler material comprising an aluminum silicon copper alloy (AlSiC)u). In one embodiment, the semiconductor device further includes a gate stack over the channel layer, the gate stack including a gate dielectric layer and a gate electrode. In one embodiment, the gate dielectric layer comprises aluminum oxide (Al)₂O₃) The gate comprises titanium nitride (TiN). In one embodiment, the channel layer includes a first source/drain region on a first side of the gate stack, the first source/drain region doped with a silicon (Si) dopant, and the conductive contact is in contact with the first source/drain region. In one embodiment, the silicon dopant of the first source/drain region has a doping concentration of 1x10¹⁸cm^-3To 1x10²⁰cm^-3In the meantime. In one embodiment, the substrate comprises indium phosphide (InP), the buffer layer comprises indium aluminum arsenide (InAlAs), and the channel layer comprises indium gallium arsenide (InGaAs). In one embodiment, the conductive liner is between 0.1 nm and 100 nm thick and the conductive filler material is between 0.1 nm and 1000 nm thick.

According to yet another embodiment, a method includes forming a channel layer on a substrate; forming a gate stack on the channel layer; forming an interlayer dielectric layer on the channel layer and the gate stack; forming an opening in the interlayer dielectric layer to expose the channel layer; and forming a conductive contact in the opening, the conductive contact comprising a conductive liner comprising titanium (Ti) and a conductive fill material comprising an aluminum silicon copper alloy (AlSiCu). In one embodiment, forming the conductive contact comprises depositing a conductive liner in the opening; and depositing a conductive filling material on the conductive lining layer, wherein the conductive lining layer and the conductive filling material fill the opening. In one embodiment, the conductive liner and conductive filler material are deposited by sputtering. In one embodiment, the conductive liner is between 0.1 nm and 100 nm thick and the conductive filler material is between 0.1 nm and 1000 nm thick. In one embodiment, the method further includes forming a buffer layer on the substrate, wherein the channel layer is formed on the buffer layer, the channel layer includes indium gallium arsenide (InGaAs), and the buffer layer includes indium aluminum arsenide (InAlAs). In one embodiment, the interlayer dielectric layer comprises silicon dioxide (SiO)₂)。

The above summary of the present disclosure is provided to enable one of ordinary skill in the art to make and use the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.