阅读说明：本技术 半导体工艺的方法及半导体器件 (Semiconductor process method and semiconductor device ) 是由 高琬贻 柯忠祁 于 2019-04-09 设计创作，主要内容包括：本公开涉及半导体工艺的方法及半导体器件。公开了形成作为氧化阻挡层的含氮层的方法,该方法包括：在晶片上形成硅层；以及形成与所述硅层接触的氧化物层。在形成所述氧化物层之后,在所述硅层与所述氧化物层之间形成与所述硅层和所述氧化物层接触的氮化硅层。然后去除所述硅层的一部分。(The present disclosure relates to a method of semiconductor processing and a semiconductor device. Disclosed is a method of forming a nitrogen-containing layer as an oxidation barrier layer, the method comprising: forming a silicon layer on a wafer; and forming an oxide layer in contact with the silicon layer. After forming the oxide layer, a silicon nitride layer is formed between the silicon layer and the oxide layer in contact with the silicon layer and the oxide layer. A portion of the silicon layer is then removed.)

1. A method of semiconductor processing, comprising:

forming a silicon layer on a wafer;

forming an oxide layer in contact with the silicon layer;

forming a silicon nitride layer in contact with the silicon layer and the oxide layer between the silicon layer and the oxide layer after forming the oxide layer; and

removing a portion of the silicon layer.

2. The method of claim 1, wherein forming the silicon nitride layer comprises: in the presence of ammonia (NH)₃) The wafer is annealed in an environment of (a).

3. The method of claim 2, wherein the annealing is performed at a temperature in a range between 500 ℃ and 700 ℃, with an annealing duration in a range between 20 minutes and 40 minutes.

4. The method of claim 2, wherein the annealing is performed at a temperature in a range between 900 ℃ and 1100 ℃, with an annealing duration in a range between 1 millisecond and 5 milliseconds.

5. The method of claim 2, wherein the plasma is turned off during the annealing.

6. The method of claim 1, wherein forming the silicon nitride layer comprises:

conducting nitrogen atoms to penetrate through the oxide layer, wherein the nitrogen atoms are blocked by the silicon layer.

7. The method of claim 1, wherein forming the silicon layer comprises: a crystalline silicon layer is epitaxially grown.

8. The method of claim 1, wherein forming the silicon layer comprises: and depositing a polysilicon layer.

9. A method of semiconductor processing, comprising:

etching a semiconductor substrate of a wafer to form grooves, wherein semiconductor strips are located between the grooves;

depositing a silicon layer extending on sidewalls of the semiconductor strips;

depositing an oxygen-containing dielectric layer on the silicon layer;

annealing the wafer in an ammonia-containing environment;

forming an isolation region in the trench;

recessing the isolation region, wherein a top portion of the semiconductor strip above a top surface of the recessed isolation region forms a semiconductor fin;

forming a gate stack on the semiconductor fin; and

forming source/drain regions based on the semiconductor fin, wherein the source/drain regions are located on opposite sides of the gate stack.

10. A semiconductor device, comprising:

a semiconductor substrate;

an isolation region extending into the semiconductor substrate, wherein the isolation region comprises:

a silicon nitride layer; and

an oxide layer on the silicon nitride layer;

a semiconductor fin protruding above a top surface of the silicon nitride layer; and

a semiconductor strip overlapping the semiconductor fin, wherein the semiconductor strip is in contact with the silicon nitride layer.

Technical Field

The present disclosure relates to a method of semiconductor processing and a semiconductor device.

Background

Transistors are basic building blocks in integrated circuits. In earlier developments of integrated circuits, fin field effect transistors (finfets) were formed instead of planar transistors. In forming the FinFET, a semiconductor fin is formed, and a dummy gate is formed on the semiconductor fin. Gate spacers are formed on sidewalls of the dummy gate stack. The dummy gate stack is then removed to form trenches between the gate spacers. A replacement gate is then formed in the trench.

Disclosure of Invention

An embodiment of the present disclosure provides a method of a semiconductor process, including: forming a silicon layer on a wafer; forming an oxide layer in contact with the silicon layer; forming a silicon nitride layer in contact with the silicon layer and the oxide layer between the silicon layer and the oxide layer after forming the oxide layer; and removing a portion of the silicon layer.

Embodiments of the present disclosure also provide a method of a semiconductor process, including: etching a semiconductor substrate of a wafer to form grooves, wherein semiconductor strips are located between the grooves; depositing a silicon layer extending on sidewalls of the semiconductor strips; depositing an oxygen-containing dielectric layer on the silicon layer; annealing the wafer in an environment containing ammonia; forming an isolation region in the trench; recessing the isolation region, wherein a top portion of the semiconductor strip above a top surface of the recessed isolation region forms a semiconductor fin; forming a gate stack on the semiconductor fin; and forming source/drain regions based on the semiconductor fin, wherein the source/drain regions are located on opposite sides of the gate stack.

Embodiments of the present disclosure also provide a semiconductor device including: a semiconductor substrate; an isolation region extending into the semiconductor substrate, wherein the isolation region comprises: a silicon nitride layer; and an oxide layer on the silicon nitride layer; a semiconductor fin protruding above a top surface of the silicon nitride layer; and a semiconductor strip overlapping the semiconductor fin, wherein the semiconductor strip is in contact with the silicon nitride layer.

Drawings

Various aspects of this disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-16 illustrate cross-sectional and perspective views of an intermediate stage in forming a fin field effect transistor (FinFET), according to some embodiments.

Fig. 17A and 17B illustrate cross-sectional views of a FinFET in accordance with some embodiments.

Fig. 18 illustrates a process flow for forming a FinFET in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just some examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "lower," "below," "lower," "upper," and the like, may be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s), as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, a fin field effect transistor (FinFET) and a method of forming the same are provided. An intermediate stage of forming a FinFET is shown, according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments. According to some embodiments of the present disclosure, a silicon nitride monolayer is formed by annealing in ammonia. The silicon nitride monolayer is located between the oxide region and the semiconductor region such that the silicon nitride monolayer may protect the semiconductor region from oxidation, particularly during a subsequent annealing process during which oxygen may migrate to the semiconductor region to cause undesirable oxidation of the semiconductor region.

Fig. 1-16 and 17A and 17B illustrate perspective views of intermediate stages in forming a FinFET, according to some embodiments of the present disclosure. The processes shown in fig. 1-16 and 17A and 17B are also schematically reflected in the process flow 200 shown in fig. 18.

Figure 1 shows a perspective view of the initial structure. The initial structure includes a wafer 10, the wafer 10 including a substrate 20. The substrate 20 may further include a substrate (portion) 20-1. The substrate 20-1 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20-1 may also be a bulk substrate or a semiconductor-on-insulator substrate.

According to some embodiments of the present disclosure, the illustrated region is a p-type device region in which a p-type transistor, such as a p-type fin field effect transistor (FinFET), is to be formed. An epitaxial semiconductor layer 20-2 may be epitaxially grown on top of the substrate 20-1 to form the substrate 20. For example, the epitaxial semiconductor layer 20-2 may be formed of silicon germanium (SiGe) or germanium (with no silicon therein). The atomic percent of germanium in epitaxial semiconductor layer 20-2 may be higher than the atomic percent of germanium in substrate portion 20-1. According to some embodiments of the present disclosure, the atomic percentage in the epitaxial semiconductor layer 20-2 (when formed of SiGe) ranges between approximately 30% and 100%. The epitaxial semiconductor layer 20-2 may be formed of SiP, SiC, SiPC, SiGeB, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like. The epitaxial semiconductor layer 20-2 may also be substantially free of silicon, for example, wherein the percentage of silicon is less than about 1%.

According to some embodiments of the present disclosure, the illustrated region is a p-type device region in which a p-type transistor, such as a p-type FinFET, is to be formed. Accordingly, the epitaxial semiconductor layer 20-2 may be formed. According to some embodiments of the present disclosure, the illustrated region is an n-type device region in which an n-type transistor, such as an n-type FinFET, is to be formed. The epitaxial layer 20-2 extending to the p-type device regions may or may not extend to the n-type device regions. The p-type device region and the n-type FinFET region may be located on the same wafer and the same device die. Accordingly, dashed lines are drawn between substrate portions 20-1 and 20-2 to show that epitaxial layer 20-2 may or may not be present in the device regions shown.

The pad layer 22 and the mask layer 24 may be formed on the semiconductor substrate 20. The pad layer 22 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 22 is formed in a thermal oxidation process, wherein a top surface layer of the semiconductor substrate 20 is oxidized. The pad layer 22 functions as an adhesion layer between the semiconductor substrate 20 and the mask layer 24. The pad layer 22 may also serve as an etch stop layer for etching the mask layer 24. According to some embodiments of the present disclosure, mask layer 24 is formed of silicon nitride, for example, using Low Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments of the present disclosure, mask layer 24 is formed by thermal nitridation of silicon, Plasma Enhanced Chemical Vapor Deposition (PECVD), or plasma anodic nitridation. In a subsequent photolithography process, the mask layer 24 serves as a hard mask.

Referring to fig. 2, the mask layer 24 and the pad layer 22 are etched, exposing the underlying semiconductor substrate 20. The exposed semiconductor substrate 20 is then etched to form trenches 26. In the process flow shown in fig. 18, the corresponding process is shown as process 202. The portion of the semiconductor substrate 20 between adjacent trenches 26 is hereinafter referred to as a semiconductor strip 30. Portions of the trenches 26 may have strip shapes that are parallel to each other (when viewed in a top view of the wafer 100), and the trenches 26 are positioned closely to each other. According to some embodiments of the present disclosure, the aspect ratio (depth to width) of the trench 26 is greater than about 7, and may be greater than about 10. Although one semiconductor strip 30 is shown, a plurality of semiconductor strips may be formed parallel to each other with trenches 26 separating the plurality of semiconductor strips from each other. According to some embodiments of forming epitaxial semiconductor layer 20-2, the bottom of trench 26 is below interface 23 between substrate portion 20-1 and epitaxial semiconductor layer 20-2. Interface 23 is also the bottom surface of epitaxial semiconductor layer 20-2.

Referring to fig. 3, a silicon layer 32 is deposited according to some embodiments of the present disclosure. In the process flow shown in fig. 18, the corresponding process is shown as process 204. The deposition may be performed by a conformal deposition method, such as Chemical Vapor Deposition (CVD). Silicon layer 32 may be free or substantially free of other elements such as germanium, carbon, and the like. For example, the atomic percent of silicon in silicon layer 32 may be greater than about 95%. The silicon layer 32 may be formed as a crystalline silicon layer or a polysilicon layer, which may be achieved by, for example, adjusting the temperature and growth rate during deposition. The silicon layer 32 may have a thickness greater than aboutSo that it can act as an effective nitrogen barrier in subsequent processes. The thickness of the silicon layer 32 may range from about

To about

In the meantime.

When the epitaxial layer 20-2 is formed in the previous step, the silicon layer 32 is formed. The silicon layer 32 may or may not be formed in a region where the epitaxial layer 20-2 is not formed and the entire semiconductor strip 30 is formed of silicon (because the semiconductor strip 30 itself is formed of silicon). In fig. 3, silicon layer 32 is shown with dashed lines to indicate that silicon layer 32 may or may not be formed according to various embodiments.

An oxygen-containing dielectric layer (which may be an oxide layer) 34 is then deposited over the silicon layer 32. In the process flow shown in fig. 18, the corresponding process is shown as process 206. According to some embodiments of the present disclosure, the oxygen-containing dielectric layer 34 is made of silicon oxide (SiO)₂) And (4) forming. According to other embodiments of the present disclosure, the oxygen-containing dielectric layer 34 is formed of silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like. The formation method may include a conformal deposition method, such as Atomic Layer Deposition (ALD), CVD, and the like. Containing oxygenThe thickness of the dielectric layer 34 is selected to be thin enough so that nitrogen atoms can penetrate it during a subsequent anneal, while still being thick enough to act as a barrier to nitrogen atoms so that they can accumulate between the oxygen-containing dielectric layer 34 and the silicon layer 32 during a subsequent process. According to some embodiments of the present disclosure, the thickness of the oxygen-containing dielectric layer 34 ranges from about greater thanTo about

In the meantime. When the thickness of the oxygen-containing dielectric layer 34 is outside this range, the oxygen-containing dielectric layer 34 either does not allow penetration of the nitrogen atoms or does not allow the nitrogen atoms to accumulate to a predetermined thickness between the layers 32 and 34.

Fig. 4 illustrates the formation of a (first) silicon-and-nitrogen-containing dielectric layer 36 between the oxygen-containing dielectric layer 34 and the silicon layer 32. According to some embodiments of the disclosure, the composition is prepared by adding ammonia (NH) to ammonia₃) The wafer 10 is thermally processed in an environment to effect the formation process. According to some embodiments of the disclosure, the method comprises₂、N₂H₂Etc. to perform the forming process by heat-treating the wafer 10. The environment may be a process chamber. In the process flow shown in fig. 18, the corresponding process is shown as process 208. According to some embodiments of the disclosure, NH₃The pressure of (a) is in a range of between about 0.5 torr and about 10 torr. The heat treatment temperature may range between about 500 ℃ to about 700 ℃, and the treatment time may range between about 20 minutes to about 40 minutes. According to other embodiments of the present disclosure, the heat treatment temperature ranges between about 900 ℃ to about 1100 ℃, and the treatment time may range between about 1 millisecond to about 5 milliseconds. During the heat treatment, the plasma is turned off.

Due to the presence of NH₃Is treated in the environment of (NH)₃The nitrogen atoms in (a) penetrate through the oxygen-containing dielectric layer 34. The oxygen in the oxygen-containing dielectric layer 34 causes the oxygen-containing dielectric layer 34 to be permeable to nitrogen atomsAnd (4) the product is used. At NH₃After penetrating through the oxygen-containing dielectric layer 34, the penetrating nitrogen atoms are blocked by the silicon layer 32, and the silicon layer 32 is an effective barrier for nitrogen. Thus, nitrogen atoms accumulate between the oxygen-containing dielectric layer 34 and the silicon layer 32 to form the silicon-and-nitrogen-containing dielectric layer 36. According to some embodiments of the present disclosure, silicon-and-nitrogen-containing dielectric layer 36 comprises silicon nitride, for example, with Si₃N₄In the form of (1). The silicon and nitrogen-containing dielectric layer 36 may be formed as a conformal layer or a substantially conformal layer, with the oxygen-containing dielectric layer 34 in both cases in contact with the silicon layer 32. The atomic percent of nitrogen in silicon-and-nitrogen-containing dielectric layer 36 may be greater than about 30%, and may be in the range of about 40% to about 70%. The silicon and nitrogen-containing dielectric layer 36 may include small amounts of hydrogen, oxygen, and carbon therein (e.g., less than about 20 atomic percent in combination). By way of illustration, the silicon and nitrogen containing dielectric layer 36 is referred to as a silicon nitride layer 36, although it may include other elements as described above. The silicon nitride layer 36 may be a single layer or may include a plurality of single layers.

It will be appreciated that the thickness of the silicon nitride layer 36 is affected by various factors such as the composition and thickness of the oxygen-containing dielectric layer 34. For example, a thicker oxygen-containing dielectric layer 34 may result in a thicker silicon nitride layer 36. However, a thicker silicon nitride layer 36 is formed by a longer process time and/or a higher process temperature. According to some embodiments of the present disclosure, the thickness of the silicon nitride layer 36 ranges approximately from

To about

In the meantime. Accordingly, to allow the thickness of the silicon nitride layer 36 to fall within a desired range, an oxygen-containing dielectric layer 34 of an appropriate thickness is employed. In addition, the sample wafer may be tested using different combinations of process conditions/factors (e.g., thickness of layer 34, anneal time, anneal temperature, etc.) to find a set of process factors (and conditions) such that the resulting thickness of silicon nitride layer 36 may fall within a desired (b)Target) range. The desired thickness of the silicon nitride layer 36 and its effects are also discussed in subsequent paragraphs. The thickness of the silicon nitride layer 36 may be less than both the thickness of the silicon layer 32 and the thickness of the oxygen-containing dielectric layer 34. Further, the thickness of the silicon layer 32 may be less than the thickness of the oxygen-containing dielectric layer 34.

More nitrogen atoms are removed from the NH-containing gas during the initial stages of the treatment₃Into the silicon layer 32. After the nitrogen atoms accumulate, more and more nitrogen atoms are transferred from the accumulated silicon nitride layer 36 to the NH-containing layer₃The environment of (a) diffuses back. When the process is sufficiently long, equilibrium is established and the thickness of the silicon nitride layer 36 remains substantially constant even with prolonged annealing.

A dielectric material 40 is then formed to fill the remaining portions of the trench 26 and then planarized to produce the structure shown in fig. 5. In the process flow shown in fig. 18, the corresponding process is shown as process 210. The method of forming the dielectric material 40 may be selected from the following methods: flowable Chemical Vapor Deposition (FCVD), spin coating, CVD, ALD, High Density Plasma Chemical Vapor Deposition (HDPCVD), low pressure CVD (lpcvd), and the like.

According to some embodiments using FCVD, silicon and nitrogen containing precursors (e.g., Trisilamines (TSA) or Disilylamine (DSA)) are used, and thus the resulting dielectric material 40 is flowable. According to an alternative embodiment of the present disclosure, an alkyl aminosilane-based precursor is used to form the flowable dielectric material 40. During deposition, the plasma is turned on to activate the gas precursors to form a flowable oxide. After the dielectric material 40 is formed, an annealing/curing process is performed that converts the flowable dielectric material 40 into a solid dielectric material. The hardened dielectric material is also referred to as dielectric material 40.

According to some exemplary embodiments of the present disclosure, the annealing is performed in an oxygen-containing ambient. The annealing temperature may be greater than about 200 deg.c, for example in a temperature range of about 200 deg.c to about 700 deg.c. During thermal processing, an oxygen-containing process gas is introduced into the process chamber in which the wafer 10 is placed. The oxygen-containing process gas may comprise oxygen (O)₂) Ozone (O)₃) Or a combination thereof. Can also useSteam (H)₂O). As a result of the heat treatment, the dielectric material 40 is cured and hardened. The resulting dielectric material 40 may be an oxide. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, may be performed to planarize the top surface of the dielectric material 40. The hard mask 24 may be used as a stop layer during planarization.

During curing of the dielectric material 40, oxygen may migrate from the dielectric material 40 to the semiconductor strip 30, thereby oxidizing the exterior of the semiconductor strip 30. This results in an undesirable thinning of the semiconductor strip 30. According to some embodiments of the present disclosure, the silicon nitride layer 36 is formed as a barrier layer to oxygen, which prevents oxygen from reaching the semiconductor strip 30. The thicker silicon nitride layer 36 more effectively blocks oxygen. On the other hand, a thicker silicon nitride layer 36 attracts more charge in the underlying portions of the semiconductor strips 30 and the substrate 20, resulting in more charge accumulating in the silicon layer 32 and its adjacent portions of the substrate 20 and the semiconductor strips 30. The charge accumulation layer forms a channel for leakage current. Therefore, the silicon nitride layer 36 cannot be too thick. To balance the oxygen barrier effect without causing an undesirable increase in leakage current, the thickness of silicon nitride layer 36 may be selected to be about

To aboutWithin the range of (a).

The combination of the oxygen-containing dielectric layer 34 and the silicon nitride layer 36, according to some embodiments of the present disclosure, shows good results in both reducing leakage and preventing oxidation (due to the silicon nitride layer 36). Good results are due to the presence of the oxygen-containing dielectric layer 34 that does not attract charge and also due to the limited thickness of the silicon nitride layer 36.

Next, as shown in fig. 6, the dielectric region comprising silicon layer 32, silicon nitride layer 36, and oxygen-containing dielectric layer 34 is recessed, and the resulting dielectric region is referred to as dielectric region 42. In the process flow shown in FIG. 18, the correspondingThe process is shown as process 212. Throughout the specification, the dielectric region 42 is alternatively referred to as an isolation region 42 or a Shallow Trench Isolation (STI) region 42. The portions of semiconductor strip 30 above STI region 42 (and the portions of silicon layer 32 above STI region 42) are referred to as protruding (semiconductor) fins 44. According to some embodiments of the present disclosure, the top surface of STI region 42 is higher than bottom surface 23 of epitaxial layer 20-2 (if formed). The recessing of the dielectric region may be performed using a dry etch process, wherein HF₃And NH₃Used as an etching gas. According to an alternative embodiment of the present disclosure, the recessing of the dielectric region is performed using a wet etch process. For example, the etching chemistry may include, for example, an HF solution.

In the embodiments shown above, the semiconductor fins may be formed by any suitable method. For example, the semiconductor fins may be patterned using one or more photolithography processes (including double patterning or multiple patterning processes). Typically, double-patterning or multi-patterning processes combine lithographic and self-alignment processes, allowing for the creation of patterns with, for example, smaller pitches than would otherwise be obtained using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers or mandrels may be used to pattern the fins.

Referring to fig. 7, dummy gate stacks 46 are formed to intersect the protruding fins 44. In the process flow shown in FIG. 18, the corresponding process is shown as process 214. The dummy gate stack 46 may include a dummy gate dielectric 48 and a dummy gate electrode 50 over the dummy gate dielectric 48. The dummy gate dielectric 48 may be formed of silicon oxide or other dielectric material. For example, polysilicon or amorphous silicon may be used, and other materials may be used to form the dummy gate electrode 50. Each dummy gate stack 46 may also include one (or more) hard mask layer(s) 52 over dummy gate electrode 50. The hard mask layer 52 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 46 may span a single or multiple protruding fins 44 and/or STI regions 42. The dummy gate stack 46 also has a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fins 44. The formation of the dummy gate stack 46 includes: depositing a dummy gate dielectric layer, depositing a gate electrode layer over the dummy gate dielectric layer, planarizing the dummy gate dielectric layer, depositing a hard mask layer, and patterning the stack layer to form a dummy gate stack 46.

Next, referring to fig. 8, gate spacers 54 are formed on the sidewalls of the dummy gate stack 46. In the process flow shown in fig. 18, the corresponding process is shown as process 216. The formation of gate spacers 54 may include depositing a blanket dielectric layer and performing an anisotropic etch to remove horizontal portions of the dielectric layer such that gate spacers 54 remain on the sidewalls of dummy gate stack 46. According to some embodiments of the present disclosure, the gate spacers 54 are made of, for example, SiO₂Oxygen-containing dielectric materials (oxides) such as SiOC and SiOCN. The gate spacers 54 may also comprise a non-oxide dielectric material, such as silicon nitride, according to some embodiments of the present disclosure.

Referring to fig. 9, a heat treatment is performed to form a silicon and nitrogen containing layer 56. In the process flow shown in fig. 18, the corresponding process is shown as process 218. The process is similar to the process for forming silicon nitride layer 36. The process details may be substantially the same as those for forming silicon nitride layer 36 and, therefore, are not repeated herein. The resulting details (e.g., composition, thickness, etc.) of silicon and nitrogen containing layer 56 may be similar to the details of silicon nitride layer 36. Throughout the specification, silicon and nitrogen containing layer 56 is alternatively referred to as silicon nitride layer 56, although it may include other elements such as carbon, oxygen, and the like. According to some embodiments in which the dummy gate electrode 50 is formed of polysilicon or amorphous silicon, the dummy gate electrode 50 acts as a barrier layer for blocking nitrogen atoms, and thus no additional silicon layer is formed in order to block nitrogen atoms. According to an alternative embodiment in which gate electrode 50 is formed of a non-silicon material (e.g., amorphous carbon), an additional silicon layer (not shown) is formed on the sidewalls of dummy gate stack 46 prior to forming gate spacers 54. Thus, a silicon nitride layer 56 will be formed between the additional silicon layer and the gate spacer 54. In subsequent paragraphs, the silicon nitride layer 56 and the gate spacer 54 are referred to in combination as a gate spacer 58.

According to an alternative embodiment of the present disclosure, the heat treatment for forming silicon nitride layer 56 is skipped, and thus silicon nitride layer 56 is not formed.

In a subsequent step, an etching process (hereinafter referred to as fin recess) is performed to etch the portion of the protruding fin 44 not covered by the dummy gate stack 46 and the gate spacer 58, resulting in the structure shown in fig. 10. In the process flow shown in fig. 18, the corresponding process is shown as process 220. The recessing of the protruding fins 44 may be performed by an anisotropic etch process, so that the portions of the protruding fins 44 directly under the dummy gate stack 46 and the gate spacers 58 are protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 30 may be lower than the top surface 42A of the STI region 42. Thus, the recess 60 is located between the STI regions 42. Recesses 60 are located on opposite sides of dummy gate stack 46. During the recessing, portions of silicon layer 32 above bottom surface 60A of recess 60 are also etched, thereby exposing sidewalls of silicon nitride layer 36. The bottom surface 60A may also be above, flush with, or below the interface 23. Thus, there may or may not be a remaining portion of the epitaxial semiconductor layer 20-2 directly below the recess 60.

Next, epitaxial regions (source/drain regions) 62 are formed by selectively growing semiconductor material from the recesses 60, resulting in the structure in fig. 11. In the process flow shown in fig. 18, the corresponding process is shown as process 222. According to some embodiments of the present disclosure, the epitaxial region 62 comprises silicon germanium, silicon, or silicon carbon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, either a p-type or n-type impurity may be doped in-situ as the epitaxy progresses. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, or the like may be grown. In contrast, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. According to an alternative embodiment of the present disclosure, epitaxial region 62 is formed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After epitaxial region 62 completely fills recess 60, epitaxial region 62 begins to expand horizontally and may be faceted.

After the epitaxy step, the epitaxial region 62 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted with reference numeral 62. According to an alternative embodiment of the present disclosure, the implantation process is skipped when the epitaxial region 62 is doped with p-type or n-type impurities in situ during the epitaxy.

In accordance with an alternative embodiment of the present disclosure, rather than recessing the protruding fin 44 and regrowing the source/drain regions 62, an encapsulated source/drain region is formed. According to these embodiments, the protruding fin 44 as shown in fig. 9 has no recess, and an epitaxial region (not shown) is grown on the protruding fin 44. The material of the grown epitaxial region may be similar to the material of the epitaxial semiconductor material 62 as shown in fig. 11, depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET. Thus, source/drain region 62 includes protruding fin 44 and an epitaxial region. An implantation process of implanting an n-type impurity or a p-type impurity may (or may not) be performed.

Fig. 12 shows a perspective view of the structure after forming a Contact Etch Stop Layer (CESL)66 and an interlayer dielectric (ILD) 68. In the process flow shown in FIG. 18, the corresponding process is shown as process 224. CESL 66 may be formed of silicon nitride, silicon carbonitride, or the like. The CESL 66 may be formed, for example, using a conformal deposition method such as ALD or CVD. ILD68 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or other deposition methods. ILD68 may also be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as Tetraethylorthosilicate (TEOS) oxide, plasma-enhanced cvd (pecvd) oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed to level the top surfaces of ILD68, dummy gate stack 46, and gate spacer 58 with one another. In the formation of ILD68, an annealing process may be employed. According to some embodiments of the present disclosure, silicon nitride layer 56 acts as a barrier layer to block oxygen from penetrating through and reaching protruding fins 44 (not visible in fig. 12, refer to fig. 6 and 7).

Next, dummy gate stack 46, including hard mask layer 52, dummy gate electrode 50, and dummy gate dielectric 48, is etched in one or more etch processes to form trenches 70 between opposing portions of gate spacers 58, as shown in fig. 13. In the process flow shown in FIG. 18, the corresponding process is shown as process 226. The etching process may be performed using, for example, dry etching. The plasma may also be turned on during the etching process. The etching gas is selected based on the material to be etched. For example, when hard mask 36 comprises silicon nitride, the etch gas may comprise a fluorine-containing process gas, such as CF₄/O₂/N₂、NF₃/O₂、SF₆Or SF₆/O₂And the like. Can use C₂F₆、CF₄、SO₂、HBr、 Cl₂And O₂HBr, Cl₂And O₂Or HBr, Cl₂、O₂And CF₂The dummy gate electrode 50 is etched. NF may be used₃And NH₃Or HF and NH₃The mixture etches the dummy gate dielectric 48. If a silicon layer is formed on the sidewalls of the dummy gate stack 46, the silicon layer is also removed.

Silicon nitride layer 56 is exposed to trench 70 as a result of etching dummy gate stack 46. During the etching process, silicon nitride layer 56 may be thinned, for example, to a thickness in the range of about

To aboutIn the meantime. According to some embodiments, where the original silicon nitride layer 56 is very thin prior to removing the dummy gate stack 46, the silicon nitride layer 56 may also be removed due to etching, so that the sidewalls of the gate spacers 54 are exposed to the trenches 70. Silicon nitride layer 56 with a high nitrogen percentage for etchingThe damage caused by the plasma etching dummy gate stack 46 is more resistant.

Next, referring to fig. 14, a (replacement) gate stack 72 is formed that includes a gate dielectric 74 and a gate electrode 76. In the process flow shown in FIG. 18, the corresponding process is shown as process 228. The formation of the gate stack 72 includes forming/depositing multiple layers and then performing a planarization process, such as a CMP process or a mechanical polishing process. Gate dielectric 74 extends to trench 70 (fig. 13). According to some embodiments of the present disclosure, the gate dielectric 74 includes an Interfacial Layer (IL)78 as its lower portion (fig. 17A and 17B). IL 78 is formed on the exposed surface of protruding fin 44. IL 78 may include an oxide layer, such as a silicon oxide layer formed by thermal oxidation, a chemical oxidation process, or a deposition process of protruding fin 44. Gate dielectric 74 may also include a high-k dielectric layer 80 formed over IL 78. High-k dielectric layer 80 may include a high-k dielectric material, such as HfO₂、ZrO₂、 HfZrO_x、HfSiO_x、HfSiON、ZrSiO_x、HfZrSiO_x、Al₂O₃、HfAlO_x、HfAlN、 ZrAlO_x、La₂O₃、TiO₂、Yb₂O₃Silicon nitride, and the like. The high-k dielectric material has a dielectric constant (k value) higher than 3.9 and may be higher than about 7.0. High-k dielectric layer 80 is formed as a conformal layer and extends onto the sidewalls of protruding fin 44 and the sidewalls of gate spacer 58. According to some embodiments of the present disclosure, the high-k dielectric layer 80 is formed using ALD or CVD.

Referring again to fig. 14, a gate electrode 76 is formed on top of the gate dielectric 74 and fills the remaining portion of the trench left by the removed dummy gate stack. The sublayers in gate electrode 76 are not separately shown in fig. 14, but in practice, the sublayers may be distinguished from each other due to their different compositions. The deposition of at least the lower sub-layer may be performed using a conformal deposition method, such as ALD or CVD, such that the thickness of the vertical portion and the thickness of the horizontal portion of the gate electrode 76 (of each sub-layer) are substantially equal to each other.

The gate electrode 76 may include a plurality of layers including, but not limited to, a Titanium Silicon Nitride (TSN) layer, a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a titanium aluminum (TiAl) layer, additional TiN and/or TaN layers, and a fill metal. Some of these layers define the work function of the corresponding FinFET. Furthermore, the metal layers of the p-type FinFET and the n-type FinFET may be different from each other such that the work function of the metal layers is appropriate for the respective p-type or n-type FinFET. The filler metal may comprise aluminum, copper or cobalt.

Next, as shown in fig. 15, a hard mask 82 is formed. According to some embodiments of the present disclosure, the forming of the hard mask 82 includes: replacement gate stack 72 is recessed by etching to form a recess, a dielectric material is filled into the recess, and planarization is performed to remove excess portions of the dielectric material. . The remaining portion of the dielectric material is a hard mask 82. According to some embodiments of the present disclosure, the hard mask 82 is formed of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like.

Fig. 16 shows a subsequent step of forming a contact plug. Contact openings are first formed by etching into ILD68 and CESL 66 to expose source/drain regions 62. Silicide regions 84 and source/drain contact plugs 86 are then formed to extend into ILD68 and CESL 66. In the process flow shown in fig. 18, the corresponding process is shown as process 230. The top edge of silicon nitride layer 36 may be in contact with silicide regions 84 or with source/drain contact plugs 86 depending on where silicide regions 84 extend. Alternatively, the top edge of silicon nitride layer 36 may be in contact with source/drain region 62.

In subsequent steps, as shown in FIG. 17A, etch stop layer 88 is formed, followed by ILD 90. Fig. 17A shows a cross-sectional view taken from the same plane as fig. 16 containing line a-a. According to some embodiments of the present disclosure, the etch stop layer 88 is formed of SiN, SiCN, SiC, SiOCN, or another dielectric material. The forming method may include PECVD, ALD, CVD, and the like. The material of ILD 90 may be selected from the same candidate materials (and methods) for forming ILD68, and ILDs 68 and 90 may be formed from the same or different dielectric materials. According to some embodiments of the present disclosure, the ILD 90 is formed using PECVD, FCVD, spin-on coating, or the likeFormed of, and may include silicon oxide (SiO)₂)。

ILD 90 and etch stop layer 88 are etched to form openings. The etching may be performed using, for example, Reactive Ion Etching (RIE). A gate contact plug 92 and a source/drain contact plug 94 are formed in the opening to be electrically connected to the gate electrode 76 and the source/drain contact plug 86, respectively. Thereby forming FinFET 96.

Fig. 17B shows a cross-sectional view of FinFET 96 taken from another plane that is the same as the plane containing line B-B in fig. 16. Fig. 17B shows silicon nitride layers 36 and 56 for other features.

Embodiments of the present disclosure have some advantageous features. By forming the silicon nitride layer, the advantageous properties of the silicon nitride layer for preventing oxygen from reaching the fins and oxidizing the fins are achieved. On the other hand, the silicon nitride layer is very thin and therefore does not lead to an unfavourable increase in leakage current. The thin layer of silicon nitride and the oxide layer combine to form a good oxidation and leakage barrier.

According to some embodiments of the disclosure, a method comprises: forming a silicon layer on a wafer; forming an oxide layer in contact with the silicon layer; forming a silicon nitride layer in contact with the silicon layer and the oxide layer between the silicon layer and the oxide layer after forming the oxide layer; and removing a portion of the silicon layer. According to an embodiment, forming the silicon nitride layer includes including ammonia (NH)₃) The wafer is annealed in the ambient of (a). According to an embodiment, the annealing is performed at a temperature in a range between about 500 ℃ and about 700 ℃, with an annealing duration in a range between about 20 minutes and about 40 minutes. According to an embodiment, the annealing is performed at a temperature in a range of between about 900 ℃ and about 1100 ℃, with an annealing duration in a range of between about 1 millisecond and about 5 milliseconds. According to an embodiment, the plasma is turned off during annealing. According to an embodiment, forming the silicon nitride layer includes: conducting nitrogen atoms to penetrate the peroxide layer, wherein the nitrogen atoms are blocked by the silicon layer. According to an embodiment, forming the silicon layer comprises epitaxially growing a crystalline silicon layer. According to an embodiment, forming the silicon layer includes depositing a polysilicon layer. According to an embodiment, the silicon layer is substantially free of germaniumAnd the silicon layer is formed on the germanium-containing semiconductor region. According to an embodiment, the silicon layer is a dummy gate electrode, and the method further comprises removing the dummy gate electrode to expose the silicon nitride layer.

According to some embodiments of the present disclosure, a method includes etching a semiconductor substrate of a wafer to form trenches, wherein a semiconductor strip is located between the trenches; depositing a silicon layer extending on the sidewalls of the semiconductor strips; depositing an oxygen-containing dielectric layer on the silicon layer; annealing the wafer in an environment containing ammonia; forming an isolation region in the trench; a recessed isolation region, wherein a top portion of the semiconductor strip above a top surface of the recessed isolation region forms a semiconductor fin; forming a gate stack on the semiconductor fin; and forming source/drain regions based on the semiconductor fin, wherein the source/drain regions are located on opposite sides of the gate stack. According to an embodiment, the annealing results in a silicon nitride layer being formed between the silicon layer and the oxygen-containing dielectric layer. According to an embodiment, the annealing is performed at a temperature in a range between about 500 ℃ and about 700 ℃, with an annealing duration in a range between about 20 minutes and about 40 minutes. According to an embodiment, the annealing is performed at a temperature in a range between about 900 ℃ and about 1100 ℃, with an annealing duration in a range between about 1 millisecond and about 5 milliseconds. In an embodiment, the method further comprises epitaxially growing a germanium-containing semiconductor layer over the silicon substrate, wherein the germanium-containing semiconductor layer and the silicon substrate form, in combination, a semiconductor substrate, and the silicon layer is formed to contact a remaining portion of the germanium-containing semiconductor layer in the semiconductor strip.

According to some embodiments of the present disclosure, a device includes a semiconductor substrate; an isolation region extending into a semiconductor substrate, wherein the isolation region comprises: a silicon nitride layer; and an oxide layer on the silicon nitride layer; a semiconductor fin protruding above a top surface of the silicon nitride layer; and a semiconductor strip overlapping the semiconductor fin, wherein the semiconductor strip is in contact with the silicon nitride layer. According to an embodiment, a semiconductor strip includes: a lower portion, wherein the lower portion comprises silicon and is free of germanium; and an upper portion comprising: an inner portion formed of a germanium-containing semiconductor material;and an outer portion formed of silicon, and the outer portion is substantially free of germanium, and the outer portion contacts the silicon nitride layer. According to an embodiment, the interface between the lower portion and the upper portion is at an intermediate level between the top surface and the bottom surface of the isolation region. According to an embodiment, the silicon nitride layer has a thickness in the range of about

To about

In the meantime. According to an embodiment, the silicon nitride layer further comprises carbon and oxygen.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method of semiconductor processing, comprising: forming a silicon layer on a wafer; forming an oxide layer in contact with the silicon layer; forming a silicon nitride layer in contact with the silicon layer and the oxide layer between the silicon layer and the oxide layer after forming the oxide layer; and removing a portion of the silicon layer.

Example 2 is the method of example 1, wherein forming the silicon nitride layer comprises: the wafer is annealed in an environment containing ammonia (NH 3).

Example 3 is the method of example 2, wherein the annealing is performed at a temperature in a range between about 500 ℃ and about 700 ℃, and an annealing duration in a range between about 20 minutes and about 40 minutes.

Example 4 is the method of example 2, wherein the annealing is performed at a temperature in a range between about 900 ℃ and about 1100 ℃, and an annealing duration in a range between about 1 millisecond and about 5 milliseconds greater.

Example 5 is the method of example 2, wherein during the annealing, the plasma is turned off.

Example 6 is the method of example 1, wherein forming the silicon nitride layer comprises: conducting nitrogen atoms to penetrate through the oxide layer, wherein the nitrogen atoms are blocked by the silicon layer.

Example 7 is the method of example 1, wherein forming the silicon layer comprises: a crystalline silicon layer is epitaxially grown.

Example 8 is the method of example 1, wherein forming the silicon layer comprises: a polycrystalline silicon layer is deposited.

Example 9 is the method of example 1, wherein the silicon layer is substantially free of germanium and the silicon layer is formed on a germanium-containing semiconductor region.

Example 10 is the method of example 1, wherein the silicon layer is a dummy gate electrode, and the method further comprises removing the dummy gate electrode to expose the silicon nitride layer.

Example 11 is a method of semiconductor processing, comprising: etching a semiconductor substrate of a wafer to form trenches, wherein semiconductor strips are located between the trenches; depositing a silicon layer extending over sidewalls of the semiconductor strips; depositing an oxygen-containing dielectric layer on the silicon layer; annealing the wafer in an ammonia-containing environment; forming an isolation region in the trench; recessing the isolation region, wherein a top portion of the semiconductor strip above a top surface of the recessed isolation region forms a semiconductor fin; forming a gate stack on the semiconductor fin; and forming source/drain regions based on the semiconductor fin, wherein the source/drain regions are located on opposite sides of the gate stack.

Example 12 is the method of example 11, wherein annealing causes a silicon nitride layer to be formed between the silicon layer and the oxygen-containing dielectric layer.

Example 13 is the method of example 11, wherein the annealing is performed at a temperature in a range between about 500 ℃ and about 700 ℃, and an annealing duration in a range between about 20 minutes and about 40 minutes.

Example 14 is the method of example 11, wherein the annealing is performed at a temperature in a range between about 900 ℃ and about 1100 ℃, and an annealing duration in a range between about 1 millisecond and about 5 milliseconds.

Example 15 is the method of example 11, further comprising epitaxially growing a germanium-containing semiconductor layer over a silicon substrate, wherein the germanium-containing semiconductor layer and the silicon substrate form the semiconductor substrate in combination, and the silicon layer is formed to contact a remaining portion of the germanium-containing semiconductor layer in the semiconductor strip.

Example 16 is a semiconductor device, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate, wherein the isolation region comprises: a silicon nitride layer; and an oxide layer on the silicon nitride layer; a semiconductor fin protruding above a top surface of the silicon nitride layer; and a semiconductor strip overlapping the semiconductor fin, wherein the semiconductor strip is in contact with the silicon nitride layer.

Example 17 is the device of example 16, wherein the semiconductor strip includes: a lower portion, wherein the lower portion comprises silicon and is free of germanium; and an upper portion comprising: an inner portion formed of a germanium-containing semiconductor material; and an outer portion formed of silicon, and the outer portion is substantially free of germanium, and the outer portion is in contact with the silicon nitride layer.

Example 18 is the device of example 17, wherein an interface between the lower portion and the upper portion is at an intermediate level between a top surface and a bottom surface of the isolation region.

Example 19 is the device of example 16, wherein the silicon nitride layer has a thickness in a range of approximately

To about

In the meantime.

Example 20 is the device of example 16, wherein the silicon nitride layer further comprises carbon and oxygen.