阅读说明：本技术 碳化硅半导体装置 (Silicon carbide semiconductor device ) 是由 辻崇 木下明将 于 2019-04-25 设计创作，主要内容包括：本发明提供在高温下能提高基于栅极电压控制的电流控制性的碳化硅半导体装置。在p型基区(23)的比有源区靠外侧的p型基区延伸部(23’)设置p<Sup>+</Sup>型高浓度区(51)。在与半导体基板的正面平行的第一方向X上,在p<Sup>+</Sup>型高浓度区(51)与n<Sup>+</Sup>型源区(24)之间,以及在与半导体基板(10)的正面平行且与第一方向X正交的第二方向Y上在p<Sup>+</Sup>型高浓度区与最外侧的沟槽(26)之间的部分是构成p型基区延伸部(23’)的p型碳化硅外延层,且在半导体基板的正面(13a)露出。第一方向X上从p<Sup>+</Sup>型高浓度区到n<Sup>+</Sup>型源区的第一距离X1为0.6μm以上。第二方向Y上从p<Sup>+</Sup>型高浓度区到最外侧的沟槽的第二距离Y1为0.6μm以上。(The invention provides a silicon carbide semiconductor device capable of improving current controllability by gate voltage control at high temperature. The p-type base region extension part (23') of the p-type base region (23) is provided with p + A high concentration region (51). In a first direction X parallel to the front surface of the semiconductor substrate, in p + A high concentration region (51) and n + Of a source region (24)And p in a second direction Y parallel to the front surface of the semiconductor substrate (10) and orthogonal to the first direction X + The part between the type high concentration region and the outermost trench (26) is a p-type silicon carbide epitaxial layer constituting a p-type base extension part (23'), and is exposed on the front surface (13a) of the semiconductor substrate. From p in a first direction X + Type high concentration region to n + The first distance X1 of the source region is 0.6 μm or more. From p in a second direction Y + The second distance Y1 between the type high concentration region and the outermost trench is 0.6 μm or more.)

1. A silicon carbide semiconductor device is characterized by comprising:

an active region which is provided in a semiconductor substrate of a first conductivity type having a first main surface and a second main surface and through which a main current flows;

a termination region surrounding a periphery of the active region;

a second conductivity type epitaxial layer which constitutes a part of the semiconductor substrate and forms the first main surface of the semiconductor substrate;

a first semiconductor region of the first conductivity type selectively provided in the active region in a surface layer on the first principal surface side of the second conductivity type epitaxial layer;

a second semiconductor region of a second conductivity type which is provided in a surface layer of the second conductivity type epitaxial layer on the first principal surface side selectively at a boundary region between the active region and the termination region and has an impurity concentration higher than that of the second conductivity type epitaxial layer;

a third semiconductor region of the second conductivity type which is a portion of the second conductivity type epitaxial layer other than the first semiconductor region and the second semiconductor region;

a fourth semiconductor region of the first conductivity type which is a portion of the semiconductor substrate other than the second conductivity type epitaxial layer;

a trench penetrating the first semiconductor region and the third semiconductor region to reach the fourth semiconductor region;

a gate electrode provided inside the trench with a gate insulating film interposed therebetween;

a first electrode electrically connected to the first semiconductor region and the third semiconductor region; and

a second electrode provided on the second main surface of the semiconductor substrate,

the second semiconductor region is disposed in a manner separated from the first semiconductor region,

a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate between the second semiconductor region and the first semiconductor region.

2. The silicon carbide semiconductor device according to claim 1, wherein the trench extends linearly in a first direction parallel to the first main surface of the semiconductor substrate,

the second semiconductor region is disposed in the vicinity of an end portion of the trench so as to be separated from the first semiconductor region in the first direction.

3. The silicon carbide semiconductor device according to claim 2, wherein the trenches are arranged in a plurality in a stripe shape extending from the active region to the boundary region in the first direction,

the first semiconductor region is disposed between adjacent ones of the trenches,

the second semiconductor region is arranged so as to be separated from an outermost trench among the plurality of trenches that is closest to the boundary region in a second direction parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction,

a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate between the second semiconductor region and the outermost trench.

4. The silicon carbide semiconductor device according to claim 3, wherein a portion of the third semiconductor region exposed at the first main surface of the semiconductor substrate is disposed in the boundary region and surrounds the active region.

5. The silicon carbide semiconductor device according to claim 2, wherein a first distance from the second semiconductor region to the first semiconductor region in the first direction is 0.6 μm or more.

6. The silicon carbide semiconductor device according to claim 3 or 4, wherein a second distance from the second semiconductor region to the outermost trench in the second direction is 0.6 μm or more.

7. The silicon carbide semiconductor device according to claim 6, wherein a first distance from the second semiconductor region to the first semiconductor region in the first direction is 9.35 μm or more.

8. The silicon carbide semiconductor device according to claim 1, wherein a plurality of the trenches are arranged in a stripe shape extending from the active region to the boundary region in a first direction parallel to the first main surface of the semiconductor substrate,

the first semiconductor region is disposed between adjacent ones of the trenches,

the second semiconductor region is arranged so as to be separated from an outermost trench among the plurality of trenches that is closest to the boundary region in a second direction parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction,

a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate between the second semiconductor region and the outermost trench.

9. The silicon carbide semiconductor device according to claim 8, wherein a second distance from the second semiconductor region to the outermost trench in the second direction is 0.6 μm or more.

10. The silicon carbide semiconductor device according to any one of claims 1 to 9, wherein an impurity concentration of the second semiconductor region is 6.4 x 10¹⁴/cm²The following.

11. The silicon carbide semiconductor device of claim 2, wherein the trench extends from the active region to the boundary region and terminates at a location closer to the active region than the second semiconductor region.

12. The silicon carbide semiconductor device according to any one of claims 1 to 11, further comprising a fifth semiconductor region of the second conductivity type selectively provided in a portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate and having an impurity concentration higher than that of the third semiconductor region,

the third semiconductor region is electrically connected to the first electrode via the fifth semiconductor region.

13. The silicon carbide semiconductor device according to claim 12, wherein the fifth semiconductor region is a diffusion region in which an impurity of the second conductivity type is ion-implanted into the epitaxial layer of the second conductivity type.

14. The silicon carbide semiconductor device according to any one of claims 1 to 13, wherein the second semiconductor region is a diffusion region in which a second-conductivity-type impurity is ion-implanted into the second-conductivity-type epitaxial layer.

Technical Field

The present invention relates to a silicon carbide semiconductor device.

Background

Silicon carbide (SiC) is expected as a semiconductor material that can realize high breakdown voltage, low on-resistance, low loss, high-speed characteristics, high-temperature characteristics, and the like, as compared with silicon (Si). In addition, a trench Gate structure is employed in a semiconductor device having a MOS Gate structure such as a MOSFET (Metal Oxide semiconductor field Effect Transistor) having an Insulated Gate formed of a 3-layer structure of a Metal-Oxide-semiconductor and/or an IGBT (Insulated Gate Bipolar Transistor).

The trench gate structure includes a MOS gate structure in which a MOS gate is embedded in a trench formed in a front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along a sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which a channel is formed along the front surface of a semiconductor substrate, the density of unit cells (structural cells of an element) per unit area can be increased, and the current density per unit area can be increased, which is advantageous in terms of cost. The planar gate structure is a MOS gate structure in which a MOS gate is provided in a planar shape on the front surface of a semiconductor substrate.

A structure of a conventional silicon carbide semiconductor device (a semiconductor device using silicon carbide as a semiconductor material) will be described with a MOSFET as an example. Fig. 21 is a plan view showing a layout of a conventional silicon carbide semiconductor device when viewed from the front surface side of a semiconductor substrate. Fig. 22 is a sectional view showing a sectional structure at a cutting line AA-AA' of fig. 21. Fig. 22 shows a cross-sectional structure of a region (hereinafter referred to as a boundary region) 103 between the active region 101 and the edge termination region 102. Fig. 23 is a plan view showing a part of fig. 21 in an enlarged manner. Fig. 24 and 25 are sectional views showing the sectional structures at the cutting lines CC-CC and DD-DD' of fig. 23, respectively.

FIG. 23 shows a rectangular frame surrounded by vertices BB, BB' as diagonal verticesThe state near the boundary between the active region 101 and the boundary region 103 near the corner of the semiconductor substrate (semiconductor chip) 110. The vertex BB of the rectangular frame is the corner side of the semiconductor substrate 110, and the vertex BB' is the central side of the semiconductor substrate 110. The corner of the semiconductor substrate 110 refers to a vertex of the semiconductor substrate 110 having a substantially rectangular planar shape. In FIG. 23, n is shown⁺ Type source region 124, p⁺ Type contact region 125, trench 126 and p⁺The gate insulating film 127 and the gate electrode 128 are omitted from the layout of the type high concentration region 151.

In the conventional silicon carbide semiconductor device shown in fig. 21 to 25, p is provided between the active region 101 and the edge termination region 102⁺A MOSFET in the boundary region 103 of the type high concentration region 151. The active region 101 is disposed in the center of a semiconductor substrate 110 made of silicon carbide. A plurality of unit cells of a vertical MOSFET having a trench gate structure are arranged in the active region 101, and when the MOSFET is turned on, a main current flows in the active region 101. The trench gate structure (the gate electrode 128 embedded in the trench 126 via the gate insulating film 127) is arranged in a stripe shape extending in the direction X parallel to the front surface of the semiconductor substrate 110.

The edge termination region 102 is a region between the boundary region 103 and the end portion of the semiconductor substrate 110, and surrounds the periphery of the active region 101 with the boundary region 103 interposed therebetween. The edge termination region 102 has a function of relaxing electric field concentration at the end of the active region 101 to maintain a predetermined withstand voltage (withstand voltage). The breakdown voltage is a limit voltage at which a source-drain voltage does not increase any more even if avalanche breakdown occurs in the pn junction and a current between the source and the drain increases. In the edge termination region 102, for example, a plurality of p layers are arranged so that the impurity concentration decreases as the p layers are arranged outside (on the end side of the semiconductor substrate 110)^- Type regions 141 and p^--A Junction Termination (JTE) structure 140 formed by a type region 142, and the like.

The boundary region 103 is composed of p disposed on the entire front surface of the semiconductor substrate 110 between the active region 101 and the edge termination region 102⁺The type high concentration region 151. p is a radical of⁺The high concentration region 151 is provided in a portion of the p-type base region 123 of the MOSFET extending in the boundary region 103(hereinafter referred to as p-type base extension) 123', and n⁺ Type source regions 124 and p⁺The type contact region 125. In addition, p⁺The p of the innermost region (the central portion of the semiconductor substrate 110) of the type high concentration region 151 and the JTE structure 140^-The type region 141 is in contact. p is a radical of⁺The impurity concentration of the type high concentration region 151 is higher than that of the p-type base region 123.

p⁺The high concentration region 151 has a function of lowering the resistance of the p-type base region 123. By lowering the resistance of the p-type base region 123, the potential of the p-type base region 123 is prevented from rising when a hole current 162 generated mainly at the end portion of the active region 101 or the edge termination region 102 to which a high electric field is applied by the avalanche breakdown 161 at the time of turn-off is drawn toward the source 131. For example, if the potential of the p-type base region 123 rises excessively, an electric field applied to the thin gate insulating film 127 becomes large in the vicinity of the contact portion from which the hole current 162 is extracted, and therefore, the life of the gate insulating film 127 is shortened and/or dielectric breakdown is caused.

In addition, to reduce the sheet resistance of the p-type base region 123 of the MOSFET, p⁺N-type high concentration region 151 and MOSFET⁺Source region 124 is contiguously disposed. The p is⁺The type high concentration region 151 is generally formed by ion implantation of a p-type impurity such as aluminum (Al) and heat treatment for impurity activation (hereinafter referred to as activation annealing) performed after the ion implantation. For forming p⁺The ion implantation conditions of the high concentration region 151 are, for example, 350keV for the maximum acceleration energy and 5.15X 10 for the total dose of p-type impurities¹⁵/cm²。

Reference numerals 121, 111, and 112 denote silicon carbide epitaxial layers constituting the semiconductor substrate 110. The symbols 122, 122', 129, 132, 133, 143, 144 are each n^-The field oxide film is formed on the gate pad, and the field oxide film is formed on the gate pad. Reference numeral 130 denotes a metal film which makes ohmic contact with the semiconductor portion. Reference numerals 152 and 153 denote a gate potential conductive layer and a gate runner, respectively. Symbols 137, 138 are p⁺A molding region. The symbol Y is the direction in which the grooves 126 are arranged side by side. The symbol Z indicates the depth direction of the semiconductor substrate 110.

As such conventional carbonA trench gate MOSFET having a plurality of unit cells each having 1 MOS gate constituted by a gate electrode in the interior of 1 trench, wherein the outermost p is provided⁺A device in which the type contact region extends to the edge termination region and contacts the innermost p-type region of the JTE structure (see, for example, patent document 1 (paragraph 0044) below). In the following patent document 1, n in the mesa region is set to be n⁺Source region and p in the same mesa region⁺P in the vicinity of the termination of the type contact region or trench⁺Contact the type contact region to connect all n⁺The source regions are fixed at the same potential.

Disclosure of Invention

Technical problem

However, in the above-described conventional silicon carbide semiconductor device (see fig. 21 to 25), when the semiconductor substrate 110 is kept in the off state at a high temperature (for example, about 125 ℃ or higher), a gate voltage Vg that is negatively biased with respect to the potential of the source 131 is applied to the gate electrode 128 for a long time (gate voltage Vg < 0: hereinafter referred to as gate negative bias). At this time, the gate threshold voltage Vth is changed greatly in the negative direction (lower direction) than the initial state, and the current starts flowing through the drain current Id by the gate voltage Vg lower than the initial state. Therefore, the gain curve of the drain current Id (see fig. 26) greatly changes in the negative direction of the gate voltage Vg as compared with the initial state.

The initial state is a state totaling 0 (zero) V which is a time for applying a gate negative bias voltage to the gate electrode 128. The drain current Id is the current flowing from n⁺Type drain region (n)⁺Type starting substrate 121) toward n⁺The flow of electrons moved by source region 124. The gain curve of the drain current Id means that when a gate voltage Vg (gate voltage Vg ≧ 0: hereinafter referred to as gate positive bias) that is positively biased with respect to the potential of the source 131 is applied to the gate electrode 128 and the gate voltage Vg increases, the gate voltage Vg that is equal to or higher than the gate threshold voltage Vth starts to flow, and increases as the gate voltage Vg increasesAn increase curve of the added drain current Id.

The gate voltage Vg corresponding to the predetermined current amount of the drain current Id changes irregularly with respect to the initial state, and the change amount Δ Vg is largest in the negative direction at an arbitrary application time of the gate negative bias voltage applied to the gate electrode 128. The change amount Δ Vg of the gate voltage Vg is not changed in the positive direction compared to the change amount Δ Vg of the gate voltage Vg in the initial state. Therefore, when the application time of the gate negative bias voltage applied to the gate electrode 128 is taken as a time axis, the change amount Δ Vg of the gate voltage Vg does not change regularly between the maximum value in the initial state of the minimum change amount Δ Vg and the minimum value in any application time of the maximum change amount Δ Vg.

This phenomenon is conspicuously exhibited in the rising region of the drain current Id in the gain curve. Fig. 26 and 27 show the results of verifying this phenomenon. Fig. 26 is a characteristic diagram showing a region in the initial stage of current rise in a gain curve of the drain current Id of the conventional silicon carbide semiconductor device. The horizontal axis of fig. 26 represents the gate voltage Vg (gate positive bias) applied to the gate electrode 128 at the time of energization [ V [)]. The vertical axis of fig. 26 is the normalized leakage current obtained by dividing the rated current I0 by the leakage current Id. In general, the gate threshold voltage Vth is defined such that the normalized drain current (═ Id/I0) becomes 10^-3The gate voltage Vg.

Note that fig. 26 is a timing of application of the gate negative bias voltage to the gate electrode 128. When a gate negative bias is applied to the gate electrode 128, a voltage between the drain 133 and the source 131 (source-drain voltage) is 0 (zero) V. Note that the sample of "0 h" shown in the notation of fig. 26 corresponds to the initial state described above. Fig. 27 is a characteristic diagram showing a relationship between a change amount Δ Vg of the gate voltage Vg (gate positive bias) in the initial state and an application time of the gate voltage Vg (gate negative bias) at the time of turn-off in fig. 26. In fig. 27, the horizontal axis represents the time [ hour (h: hour) ] for applying the gate negative bias, and the vertical axis represents the amount of change Δ Vg of the gate positive bias with respect to the initial state.

First, a MOSFET having a structure of a conventional silicon carbide semiconductor device (see fig. 21 to 25) is prepared, and a plurality of samples in which a gate negative bias is applied to the gate electrode 128 under a high temperature condition of 200 ℃ for the semiconductor substrate 110 are prepared. The gate negative bias applied to the gate electrode 128 of these samples was-5V (gate voltage Vg ═ 5V), and the application time of the gate negative bias was different in the range of 0h to 2500 h. Fig. 26 shows the results of measuring the current amount [ a ] of the drain current Id by applying a gate positive bias to the gate electrode 128 at room temperature (for example, about 25 ℃) and applying a current thereto, and then increasing the gate positive bias to measure the current amount [ a ] of the drain current Id for these samples.

Fig. 27 shows the amount of change Δ Vg of the gate positive bias voltage with respect to the initial state, which corresponds to the predetermined current amounts Id1/I0 and Id2/I0 (positions indicated by broken lines denoted by reference symbols 171 and 172 in fig. 26) of the normalized drain current Id/I0. Fig. 27 shows, for example, a current amount Id1/I0 (10) in which the current amount of the drain current Id is one thousandth of the rated current I0 (current amount Id is one thousand)^-3) The measurement point (hereinafter referred to as the first measurement point 171') of (a) and the current amount Id2/I0 (10 parts per million) in which the current amount of the drain current Id is equal to the current amount Id1 of the drain current Id at the first measurement point 171^-9) The change Δ Vg of the gate positive bias voltage at the measurement point (hereinafter referred to as the second measurement point 172') of (a).

As shown in fig. 27, the gate positive bias voltage corresponding to the current amount of the drain current Id at the first measurement point 171' is 5.2V in all samples in which the application time of the gate negative bias voltage applied to the gate electrode 128 is different. That is, the change Δ Vg of the gate positive bias voltage at the first measurement point 171' corresponding to the current amount of the drain current Id from the initial state is almost 0 (zero) V regardless of the presence or absence of the application of the gate negative bias voltage. In contrast, the amount of change Δ Vg of the gate positive bias voltage from the initial state corresponding to the current amount of the drain current Id at the second measurement point 172 'in the state where the gate voltage Vg applied to the gate electrode 128 is applied in a state where the gate positive bias voltage is closer to the gate threshold voltage Vth than the first measurement point 171' is applied is-1.2V at the maximum.

From the results shown in fig. 27, it is understood that the characteristics of the gate threshold voltage Vth become unstable due to the adverse effects of high Temperature and application of the gate Negative Bias in the rising region of the drain current Id (specifically, in the vicinity of the second measurement point 172'), so-called NBTI (Negative Bias Temperature Instability). In this way, the gain curve of the drain current Id is greatly shifted in the negative direction of the gate voltage Vg from the initial state only in the rising region of the drain current Id.

Such a shift of the gain curve of the drain current Id causes an increase in leakage current in the opposite direction when the gate voltage Vg of 0V or less is applied to the gate electrode 128 to maintain the off state, or causes a problem of heat exposure and element destruction due to excessive leakage current.

In order to solve the above-described problems of the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device having improved current controllability by gate voltage control at high temperatures (about 200 ℃.

Technical scheme

In order to solve the above problems and achieve the object of the present invention, a semiconductor device of the present invention has the following features. An active region through which a main current flows is provided in a semiconductor substrate of a first conductivity type having a first main surface and a second main surface. The termination region surrounds the periphery of the active region. The second conductivity type epitaxial layer constitutes a part of the semiconductor substrate, and forms the first main surface of the semiconductor substrate. In the active region, a first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second conductivity type epitaxial layer on the first principal surface side. A second semiconductor region of a second conductivity type is selectively provided in a surface layer of the second conductivity type epitaxial layer on the first main surface side in a boundary region between the active region and the termination region. The second semiconductor region has an impurity concentration higher than that of the second conductivity type epitaxial layer. The third semiconductor region of the second conductivity type is a portion of the second conductivity type epitaxial layer other than the first semiconductor region and the second semiconductor region. The fourth semiconductor region of the first conductivity type is a portion of the semiconductor substrate other than the second conductivity type epitaxial layer. The trench penetrates the first semiconductor region and the third semiconductor region to reach the fourth semiconductor region. The gate electrode is provided inside the trench with a gate insulating film interposed therebetween. The first electrode is electrically connected to the first semiconductor region and the third semiconductor region. The second electrode is provided on the second main surface of the semiconductor substrate. The second semiconductor region is disposed apart from the first semiconductor region. A portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate between the second semiconductor region and the first semiconductor region.

In the semiconductor device according to the present invention, in the above-described invention, the trench linearly extends in a first direction parallel to the first main surface of the semiconductor substrate. The second semiconductor region is disposed in the vicinity of an end portion of the trench so as to be separated from the first semiconductor region in the first direction.

In the semiconductor device according to the present invention, in the above-described invention, the plurality of trenches are arranged in a stripe shape extending from the active region to the boundary region in the first direction. The first semiconductor region is disposed between adjacent trenches. The second semiconductor region is disposed so as to be separated from an outermost trench among the plurality of trenches, the outermost trench being closest to the boundary region in a second direction parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction. A portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate between the second semiconductor region and the outermost trench.

In the semiconductor device according to the present invention, in the above-described invention, a portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate is disposed in the boundary region and surrounds the periphery of the active region.

In the semiconductor device according to the present invention, in the above-described invention, a first distance from the second semiconductor region to the first semiconductor region in the first direction is 0.6 μm or more.

In the semiconductor device according to the present invention, in the above-described invention, a second distance from the second semiconductor region to the outermost trench in the second direction is 0.6 μm or more.

In the semiconductor device according to the present invention, in the above-described invention, a first distance from the second semiconductor region to the first semiconductor region in the first direction is 9.35 μm or more.

In the semiconductor device according to the present invention, in the above-described invention, the plurality of trenches are arranged in a stripe shape extending from the active region to the boundary region in a first direction parallel to the first main surface of the semiconductor substrate. The first semiconductor region is disposed between adjacent trenches. The second semiconductor region is disposed apart from an outermost trench among the plurality of trenches, the outermost trench being closest to the boundary region in a second direction parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction. A portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate between the second semiconductor region and the outermost trench.

In the semiconductor device according to the present invention, in the above-described invention, a second distance from the second semiconductor region to the outermost trench in the second direction is 0.6 μm or more.

In the semiconductor device according to the present invention, the impurity concentration of the second semiconductor region is 6.4 × 10¹⁴/cm²The following.

In the semiconductor device according to the present invention, the trench extends from the active region to the boundary region and terminates at a position closer to the active region than the second semiconductor region.

In the semiconductor device according to the present invention, the semiconductor device further includes a fifth semiconductor region of the second conductivity type selectively provided in a portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate. The impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the third semiconductor region. The third semiconductor region is electrically connected to the first electrode via the fifth semiconductor region.

In the semiconductor device according to the present invention, in the above invention, the fifth semiconductor region is a diffusion region formed by ion-implanting second-conductivity-type impurities into the second-conductivity-type epitaxial layer.

In the semiconductor device according to the present invention, in the above invention, the second semiconductor region is a diffusion region in which a second conductivity type impurity is ion-implanted into the second conductivity type epitaxial layer.

According to the above invention, when a negative gate bias is applied to the gate electrode under high temperature conditions, holes can be prevented from accumulating at the interface between the third semiconductor region and the gate insulating film. This suppresses a shift of a gain curve of a current flowing from the fourth semiconductor region toward the first semiconductor region in a negative direction of the gate voltage compared to an initial state when a gate positive bias equal to or higher than the gate threshold voltage is applied to the gate electrode.

Effects of the invention

According to the silicon carbide semiconductor device of the present invention, the current controllability by the gate voltage control can be improved at a high temperature (about 200 ℃.

Drawings

Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to embodiment 1, as viewed from the front surface side of a semiconductor substrate.

Fig. 2 is a sectional view showing a sectional structure at a cutting line a-a' of fig. 1.

Fig. 3 is a plan view showing a part of fig. 1 in an enlarged manner.

Fig. 4 is a sectional view showing a sectional structure at a cutting line C-C' of fig. 3.

Fig. 5 is a sectional view showing a sectional structure at a cutting line D-D' of fig. 3.

Fig. 6 is a sectional view showing a state in the process of manufacturing the silicon carbide semiconductor device according to embodiment 1.

Fig. 7 is a sectional view showing a state in the process of manufacturing the silicon carbide semiconductor device according to embodiment 1.

Fig. 8 is a characteristic diagram showing the result of verification performed on the first distance in example 1.

Fig. 9 is a plan view showing a layout of a part of the silicon carbide semiconductor device according to embodiment 2, as viewed from the front surface side of the semiconductor substrate.

Fig. 10 is a characteristic diagram showing the result of verification performed on the first distance in example 2.

Fig. 11 is a plan view showing a layout of a part of the silicon carbide semiconductor device according to embodiment 3, as viewed from the front surface side of the semiconductor substrate.

FIG. 12 shows p in example 3⁺The dose in the type high concentration region was verified to be a characteristic diagram.

Fig. 13 is a plan view showing a layout of a part of the silicon carbide semiconductor device according to embodiment 4, as viewed from the front surface side of the semiconductor substrate.

FIG. 14 shows p in example 4⁺The dose in the type high concentration region was verified to be a characteristic diagram.

Fig. 15 is a plan view showing a layout of a part of the silicon carbide semiconductor device according to embodiment 5, as viewed from the front surface side of the semiconductor substrate.

Fig. 16 is a sectional view showing a sectional structure at a cutting line E-E' of fig. 15.

Fig. 17 is a plan view showing a layout of a part of the silicon carbide semiconductor device according to embodiment 6, as viewed from the front surface side of the semiconductor substrate.

Fig. 18 is a sectional view showing a sectional structure at a cutting line F-F' of fig. 17.

Fig. 19 is a plan view showing the layout of the silicon carbide semiconductor device according to embodiment 7, as viewed from the front surface side of the semiconductor substrate.

Fig. 20 is a characteristic diagram showing a relationship between the first distance and the avalanche current Iav in example 6.

Fig. 21 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate.

Fig. 22 is a sectional view showing a sectional structure at a cutting line AA-AA' of fig. 21.

Fig. 23 is a plan view showing a part of fig. 21 in an enlarged manner.

Fig. 24 is a sectional view showing a sectional structure at a cutting line CC-CC of fig. 23.

Fig. 25 is a sectional view showing a sectional structure at a cutting line DD-DD' of fig. 23.

Fig. 26 is a characteristic diagram showing a region in the initial stage of current rise in a gain curve of the drain current Id of the conventional silicon carbide semiconductor device.

Fig. 27 is a characteristic diagram showing a relationship between the change amount Δ Vg of the gate voltage Vg in fig. 26 and the application time of the gate voltage Vg at the time of turn-off.

Description of the symbols

1: active region

2: edge termination region

3: boundary zone

4: invalid region

10: semiconductor substrate

11：n^-Epitaxial layer of type silicon carbide

12: p-type silicon carbide epitaxial layer

13: step difference of front surface of semiconductor substrate

13a, 13 a': front surface of semiconductor substrate

13 b: inclined portion of step difference on front surface of semiconductor substrate

13 c: corner of step difference on front surface of semiconductor substrate

21：n⁺Type starting substrate

22：n^-Type drift region

22': n-type JFET region

23: p-type base region

23': p-type base region extension

24：n⁺Source region of the pattern

25，25'：p⁺Type contact zone

26, 26': groove

27: gate insulating film

28: gate electrode

29: interlayer insulating film

29a to 29 c: contact hole

30: metal film

31: source electrode

32: gate pad

33: drain electrode

37: p directly under the trench⁺Type region

38: p of mesa region⁺Type region

40: JTE structure

41, 42: p-type region of JTE structure

43: n-type channel stop region

44: field oxide film

51，51'：p⁺Type high concentration region

52: conductive layer

53: gate runner

61: oxide film

61a：p⁺Formation region of type contact region

61b：p⁺Formation region of type high concentration region

62: ion implantation

t 1: p directly under the trench⁺Thickness of the molding zone

t 2: p of mesa region⁺Thickness of the molding zone

t 3: p of boundary region⁺Thickness of the type high concentration region

t11：n^-Thickness of type silicon carbide epitaxial layer

t 12: thickness of p-type silicon carbide epitaxial layer

X: a direction parallel to the front surface of the semiconductor substrate (first direction)

X1, X1', X11: from p in the first direction⁺Type high concentration region to n⁺Distance of source region (first distance)

Y: a direction (second direction) parallel to the front surface of the semiconductor substrate and orthogonal to the first direction

Y1: from p in the second direction⁺Distance (second distance) from the pattern high concentration region to the outermost trench

Z: direction of depth

Detailed Description

Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and the drawings, in a layer and a region prefixed with n or p, it is indicated that electrons or holes are majority carriers, respectively. In addition, the + and-marked on n or p indicate that the impurity concentration is higher and lower than that of the layer or region not marked with the + and-respectively. In the following description of the embodiments and the drawings, the same components are denoted by the same reference numerals, and redundant description thereof is omitted.

(embodiment mode 1)

A structure of a silicon carbide semiconductor device (a semiconductor device using silicon carbide (SiC) as a semiconductor material) according to embodiment 1 will be described with a MOSFET as an example. Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to embodiment 1, as viewed from the front surface side of a semiconductor substrate. Fig. 2 is a sectional view showing a sectional structure at a cutting line a-a' of fig. 1. A cross-sectional structure of a region (boundary region) 3 between the active region 1 and the edge termination region 2 is shown in fig. 2. Fig. 3 is a plan view showing a part of fig. 1 in an enlarged manner. Fig. 4 and 5 are sectional views showing sectional structures at cutting lines C-C 'and D-D' of fig. 3, respectively.

Fig. 3 shows a state in the vicinity of the boundary between the active region 1 and the boundary region 3 in the vicinity of the corner of the semiconductor substrate (semiconductor chip) 10 surrounded by a rectangular frame having a vertex B, B' of fig. 1 as a diagonal vertex. The vicinity of the vertex B of the rectangular frame is a portion on the corner side of the semiconductor substrate 10, and the vicinity of the vertex B' is a portion on the center side of the semiconductor substrate 10. The corner of the semiconductor substrate 10 is a vertex of the semiconductor substrate 10 having a substantially rectangular planar shape. In FIG. 3, n is shown⁺Type source region (first semiconductor region) 24, p⁺ Type contact region 25, trench 26 and p⁺The layout of the type high concentration region (second semiconductor region) 51 is not illustrated with the gate insulating film 27 and the gate electrode 28.

The silicon carbide semiconductor device according to embodiment 1 shown in fig. 1 to 5 includes p between an active region 1 and an edge termination region 2⁺A vertical MOSFET of a trench gate structure in the boundary region 3 of the type high concentration region 51. The active region 1 is disposed in the center of a semiconductor substrate 10 made of silicon carbide. A plurality of unit cells (structural cells of an element) of a vertical MOSFET having a trench gate structure are arranged in the active region 1, and when the MOSFET is turned on (energized), a main current (drain current Id) flows through the active region 1. The trench gate structure has a MOS gate formed of a gate electrode 28 buried through a gate insulating film 27 in a trench 26 reaching a predetermined depth from the front surface 13a of the semiconductor substrate 10.

The active region 1 is n, which is more than described later⁺A region of the outer periphery of source region 24 close to the inner side (the center side of semiconductor substrate 10) has a planar shape of, for example, a substantially rectangular shape. N in the first direction X described later⁺The outer periphery of source region 24 is n extending linearly along trench 26 in first direction X between adjacent trenches 26⁺The end of the source region 24 in the first direction X. N in the second direction Y described later⁺The outer periphery of the source region 24 refers to the inner side wall and n of the trench (outermost trench) 26 at the outermost side (end side of the semiconductor substrate 10) in the second direction Y⁺The boundary of source region 24. The edge termination region 2 is the ratio p⁺The high concentration region 51 and p of JTE structure 40 described later^-The region outside the boundary of the mold region 41.

The semiconductor substrate 10 is formed by⁺N of silicon carbide of type drain region⁺On the front surface of the type starting substrate 21, n is sequentially formed^-An epitaxial substrate in which the silicon carbide epitaxial layers 11 and 12 of the drift region (fourth semiconductor region) 22 and the p-type base region (third semiconductor region) 23 are epitaxially grown. In the semiconductor substrate 10, a main surface (first main surface) of the p-type silicon carbide epitaxial layer (second conductivity type epitaxial layer) 12 exposed is defined as a front surface 13a, and n is defined as⁺The main surface (second main surface) of the type start substrate 21 exposed from the back surface is the back surface. In the active region 1, in n^-First p-type silicon carbide epitaxial layers 11, which will be described later, are selectively provided therein⁺ Type region 37, secondDi (p)⁺And a molding region 38. n is^-Of type-SiC epitaxial layer 11 other than the first p⁺Type region 37, second p⁺The portion other than the type region 38 is n^- A drift region 22.

In the active region 1, n is selectively provided in each of the surface regions of the p-type silicon carbide epitaxial layer 12 (the surface layer of the front surface 13a of the semiconductor substrate 10)⁺ Source regions 24 and p⁺And a pattern contact region 25. n is⁺The source region 24 is formed by ion implantation of an n-type impurity such as phosphorus (P) into the P-type silicon carbide epitaxial layer 12. p is a radical of⁺ Type contact region 25 and p⁺The type high concentration region 51 is formed by ion implantation of a p-type impurity such as aluminum (Al) into the p-type silicon carbide epitaxial layer 12. Of p-type silicon carbide epitaxial layer 12 other than n⁺Source region 24, p⁺ Type contact region 25 and p⁺The portion other than the type high concentration region 51 is the p-type base region 23.

The p-type base region 23 extends outward from the active region 1 and terminates at an inclined portion 13b of a step 13, which will be described later, located in the vicinity of the boundary between the boundary region 3 and the edge termination region 2. Hereinafter, the portion of p-type base region 23 outside active region 1 is referred to as p-type base region extension portion 23'. Specifically, p-type base region extension portion 23' is a ratio n of p-type base region 23 in first direction X described later⁺The outer periphery of source region 24 is located at the outer side. p-type base region extension portion 23' is a portion of p-type base region 23 that is outside of outermost trench 26 in second direction Y described later. p-type base region extension portion 23' surrounds active region 1 in a substantially rectangular shape.

The trench 26 penetrates n from the front surface 13a of the semiconductor substrate 10 in the depth direction Z⁺ A source region 24 and a p-type base region 23 to reach n^- A drift region 22. The grooves 26 are arranged in a stripe shape extending in a direction (hereinafter referred to as a first direction) X parallel to the front surface 13a of the semiconductor substrate 10 so that both end portions are located near opposite sides of the semiconductor substrate 10. The end of the trench 26 extends outward from the active region 1 and terminates at the boundary region 3. The end of the groove 26 may reach p⁺The pattern high concentration region 51 (see fig. 3). The grooves 26 may have both ends connected to the ends of the other adjacent grooves 26A substantially annular planar shape.

A gate electrode 28 is provided in the trench 26 with a gate insulating film 27 interposed therebetween. The gate electrode 28 disposed inside the 1 trench 26 and the adjacent mesa regions partitioned by the trench 26 constitute 1 unit cell of the MOSFET. The region provided in the mesa region is electrically insulated from the gate electrode 28 by the gate insulating film 27. Mesa regions refer to the regions between adjacent trenches 26. The unit cells of the MOSFET are arranged in a plurality of stripes extending in the first direction X. I.e. the p-type base region 23, n⁺The source regions 24, the trenches 26, the gate insulating film 27, and the gate electrodes 28 are arranged in a stripe shape extending along the first direction X.

n⁺Source region 24 is provided over the entire mesa region in active region 1 so as to extend from the sidewall of trench 26 to the sidewall of another trench 26 adjacent to trench 26 with the mesa region therebetween. p is a radical of⁺The contact regions 25 may be arranged at predetermined intervals in the first direction X and distributed at n⁺Inside the source region 24. p is a radical of⁺The type contact region 25 has a metal film 30 and n for reducing the thickness⁺Source regions 24 and p⁺The contact resistance of the type contact region 25. By the p⁺The pattern contact region 25 shows ohmic (linear) characteristics of a voltage-current characteristic of a contact (electrical contact) between the metal film 30 and the semiconductor portion. Therefore, the potential difference between the source (first electrode) 31 and the semiconductor portion can be reduced.

By reducing the potential difference between the source 31 and the semiconductor section, n can be prevented⁺And a gate insulating film 27 including the type source region 24, the p-type base region 23, and the n-type drift region 22, which is damaged by the npn parasitic bipolar operation. From the front surface 13a of the semiconductor substrate 10 to n⁺The position on the side of the type starting substrate 21 deeper than the bottom surface of the trench 26 is at n^-The drift regions 22 are selectively provided with first p-type regions therein⁺ Type region 37, second p⁺And a molding region 38. First p⁺The type region 37 is arranged in the direction of n⁺The mold starting substrate 21 side is deeper than the bottom surface of the groove 26, and faces the bottom surface of the groove 26 in the depth direction Z. The bottom surface of the trench 26 may be at the first p⁺The inner end of the land 37.

Second p⁺The land region 38 is arranged in the mesa region in the direction of n⁺The type start substrate 21 side is deeper than the p-type base region 23, and is in contact with the p-type base region 23. Second p⁺The land region 38 is provided separately from the trench 26. First p⁺Type region 37, second p⁺The pattern regions 38 are alternately and repeatedly arranged in a direction (hereinafter referred to as a second direction) Y orthogonal to the first direction X and parallel to the front surface 13a of the semiconductor substrate 10. By setting these first p⁺Type region 37, second p⁺And a type region 38, whereby suppression of an electric field applied to the gate insulating film 27 and improvement of withstand voltage can be achieved at the time of MOSFET turn-off. Can make the first p⁺Type region 37 and second p⁺The impurity concentration ratio n of the n-type JFET regions 22' between the type regions 38^-The impurity concentration of the type drift region 22 is high.

In addition, the first p⁺Type region 37, second p⁺The pattern region 38 extends outward in the first direction X to a corner portion 13c of a step 13 described later, and covers p at the corner portion 13c of the step 13⁺The pattern high concentration region 51. In addition, the second p⁺The land 38 is disposed outside the outermost trench 26 in the second direction Y. A second p arranged outside the outermost trench 26 in the second direction Y⁺The type region 38 is arranged in the direction of n⁺The type start substrate 21 side is deeper than the p-type base extension portion 23 'and is in contact with the p-type base extension portion 23'. And, the second p⁺The land 38 further extends outward in the second direction Y to the corner 13c of the step 13, and the corner 13c of the step 13 is covered with p⁺The pattern high concentration region 51.

The interlayer insulating film 29 is provided on the entire front surface 13a of the semiconductor substrate 10, and covers the gate electrode 28. A first contact hole 29a penetrating the interlayer insulating film 29 in the depth direction Z is provided. In the first contact hole 29a, a mesa region (i.e., n) in the active region 1 is exposed⁺ Source regions 24 and p⁺The type contact region 25) is exposed. The mesa regions are respectively at different first contact holes 29 a. The first contact holes 29a are provided at predetermined intervals in the first direction X, for example, and expose different p⁺And a pattern contact region 25. Inside each first contact hole 29a, on the front surface of the semiconductor substrate 1013a are provided with metal films 30, respectively.

Metal films 30 and n⁺Source regions 24 and p⁺The pattern contact region 25 is in contact with the substrate, and a contact having an ohmic voltage-current characteristic is formed. The metal film 30 is, for example, a nickel silicide (NiSi) film. A source electrode 31 with a metal film 30 and n interposed therebetween⁺Source region 24, p⁺The type contact region 25 is electrically connected to the p-type base region 23. The source electrode 31 covers almost the entire surface of the active region 1 on the front surface 13a of the semiconductor substrate 10. The source 31 doubles as a source pad. The source electrode 31 may extend on the interlayer insulating film 29, terminating at the boundary region 3. The source electrode 31 may be, for example, an aluminum-silicon (Al-Si) film.

Further, on the interlayer insulating film 29 of the active region 1, a gate pad 32 is provided, for example, in the vicinity of the boundary with the boundary region 3 of the active region 1 so as to be separated from the source 31. The gate pad 32 has a planar shape of, for example, a substantially rectangular shape. The gate pad 32 is formed of, for example, the same material as the source electrode 31. The gate pad 32 is electrically connected to all the gate electrodes 28 through a conductive layer 52 and a gate runner 53, which will be described later. The drain (second electrode) 33 is provided on the entire back surface of the semiconductor substrate 10 from the active region 1 to the edge termination region 2. Drain 33 and is n⁺N of type drain region⁺The back surface of the type starting substrate 21 is contacted to form a contact having a voltage-current characteristic showing ohmic properties.

The edge termination region 2 is a region between the boundary region 3 and the end of the semiconductor substrate 10, and surrounds the periphery of the active region 1 in a substantially rectangular shape with the boundary region 3 interposed therebetween. The edge termination region 2 has a function of relaxing electric field concentration at the end of the active region 1 to maintain a predetermined withstand voltage (withstand voltage). The withstand voltage is a limit voltage at which a leakage current does not excessively increase and a malfunction and/or destruction of an element does not occur. By removing the p-type silicon carbide epitaxial layer 12 over the entire edge termination region 2, the edge termination region 2 is formed lower (n-direction) than the active region 1 on the front surface 13a of the semiconductor substrate 10⁺The type start substrate 21 side is recessed) of the step 13. By this step 13, the front surface 13a' of the semiconductor substrate 10 is newly formed in the edge termination region 2.

N is exposed on the front surface 13a' of the semiconductor substrate 10 in the edge termination region 2^-And type silicon carbide epitaxial layer 11. While forming the step difference 13The p-type silicon carbide epitaxial layer 12 and n can be removed at a predetermined depth^-And type silicon carbide epitaxial layer 11. The inclined portion 13b of the step 13 is located, for example, in the boundary region 3. The inclined portion 13b of the step 13 is a surface connecting a front surface 13a (upper surface) of the inner portion of the semiconductor substrate 10 and a front surface 13a' (lower surface) of the outer portion of the semiconductor substrate 10 in the front surface of the semiconductor substrate 10. P described later is exposed at the inclined portion 13b of the step 13⁺The pattern high concentration region 51. The front surface 13a' of the outer portion of the semiconductor substrate 10, which is the lower surface of the step 13, may extend to the boundary region 3.

In the edge termination region 2, a voltage-resistant structure such as a Junction Termination (JTE) structure 40, which is composed of a plurality of p-type regions (here, for example, 2 p-type regions are denoted by reference numerals 41 and 42 in order from the inside) having a lower impurity concentration as the position becomes further outside, is arranged in the surface layer of the front surface 13a' of the semiconductor substrate 10. Innermost p of JTE structure 40^-The type region 41 surrounds the periphery of the active region 1 with the boundary region 3 therebetween. P of JTE structure 40^-- Type region 42 and p^-The outside of the type region 41 is adjacently arranged and surrounds p^-The periphery of the mold region 41. For the depth from the front surface 13a' of the semiconductor substrate 10 in the edge termination region 2, for example, the second p⁺Type region 38 to p^-Type regions 41 and p^--The mold region 42 is deep.

By applying at these p^-Type regions 41 and p^--The internal extension of type region 42 is from the second p at turn-off⁺Type region 38 and n^-The end of the pn junction surface of drift region 22 is a depletion layer extending outward, thereby ensuring a withstand voltage in edge termination region 2. In the edge termination region 2, an n-type channel stopper region 43 is selectively provided in the surface layer of the front surface 13a' of the semiconductor substrate 10, outside the JTE structure 40 and apart from the JTE structure 40. The n-type channel stopper region 43 is exposed at an end portion of the semiconductor substrate 10 (a side surface of the semiconductor substrate 10). In the edge termination region 2, the front surface 13a' of the semiconductor substrate 10 is covered with a field oxide film 44 provided between the semiconductor substrate 10 and the interlayer insulating film 29.

The boundary region 3 is formed by a positive electrode arranged on the semiconductor substrate 10 between the active region 1 and the edge termination region 2P of surface layer of face 13a⁺The pattern high concentration region 51. p is a radical of⁺The high concentration type region 51 is formed in the surface region of the p-type base extension portion 23' by ion implantation of a p-type impurity such as aluminum. p is a radical of⁺The high concentration region 51 is aligned in the first direction X with n of the active region 1⁺ Source region 24 is disposed apart from the sidewall outside outermost trench 26 in second direction Y. In a second direction Y, at p⁺N is not provided between the high concentration region 51 and the outermost trench 26⁺ Source regions 24 and p⁺And a pattern contact region 25.

In a first direction X by p⁺ High concentration regions 51 and n⁺The portion sandwiched by the source region 24 and p in the second direction Y⁺The portion sandwiched between the high concentration type region 51 and the outermost trench 26 is a portion of the p-type base extension portion 23' formed of the p-type epitaxial silicon carbide layer 12, and is exposed on the front surface 13a of the semiconductor substrate 10 along the boundary between the active region 1 and the boundary region 3 (the portion not hatched in fig. 3 (the same applies to fig. 9, 11, 13, 15, and 17)). That is, p-type base extension portions 23' are exposed on the front surface 13a of the semiconductor substrate 10 along the boundary between the active region 1 and the boundary region 3 in a substantially linear shape extending along the pair of sides 1 of the active region 1 having a substantially rectangular planar shape or in a substantially rectangular shape surrounding the periphery of the active region 1 having a substantially rectangular planar shape.

Fig. 3 shows only the corner portions of the semiconductor substrate 10, but the corner portions are along the opposite sides parallel to the second direction Y of the boundary between the active region 1 and the boundary region 3, and n⁺The source region 24 is separately provided with p⁺The state of the type high concentration region 51. P is arranged along the opposite side parallel to the first direction X of the boundary between the active region 1 and the boundary region 3, apart from the outermost trench 26⁺The state of the type high concentration region 51. Thus, p-type base extension portion 23' can be formed of p-type silicon carbide epitaxial layer 12 having no crystal defects and can be p-type in first direction X⁺ High concentration regions 51 and n⁺The portion sandwiched by source regions 24, or the portion constituting p in the second direction Y⁺The portion sandwiched by the type high concentration region 51 and the outermost trench 26,or constitute both parts.

From p in a first direction X⁺A type high concentration region 51 to n⁺The first distance X1 of the source region 24 may be set to be, for example, 0.6 μm or more. From p in a second direction Y⁺The second distance Y1 from the high concentration type region 51 to the outermost trench 26 may be set to be, for example, about 0.6 μm or more. The first distance X1 and the second distance Y1 satisfy at least one condition, and the effects of the present invention described later can be obtained. When both the first distance X1 and the second distance Y1 are satisfied, the first distance X1 and the second distance Y1 are equal to each other (X1 — Y1). When viewed from the front surface 13a side of the semiconductor substrate 10, the periphery of the active region 1 is surrounded by a p-type base extension portion 23 'having a width of 0.6 μm or more, and the periphery of the p-type base extension portion 23' is surrounded by p⁺The type high concentration region 51 surrounds.

Thus, in source regions 1 and p⁺Between the high concentration regions 51, p-type base extension portions 23' composed of the p-type silicon carbide epitaxial layer 12 are disposed. Thus, even if the gate voltage Vg that is negatively biased with respect to the potential of the source 31 is applied to the gate electrode 28 for a long time under a high temperature condition (for example, about 125 ℃ or higher) (gate voltage Vg < 0: gate negative bias), the amount of change Δ Vg of the gate voltage Vg from the initial state corresponding to a predetermined current amount of the drain current Id can be reduced. Thus, by applying the gate negative bias under high temperature conditions, the period during which the characteristics of the gate threshold voltage Vth are unstable, that is, the period during NBTI can be shortened. Even if a gate negative bias is applied to the gate electrode 28 for a long time under a high temperature condition, the amount of drain off current (drain current) Idss can be made close to that in the initial state.

The change Δ Vg of the gate voltage Vg from the initial state is a value (difference) obtained by subtracting the gate voltage Vg in the state where the gate negative bias is applied from the gate voltage Vg in the initial state. The power-on state is a state in which a gate voltage Vg (gate voltage Vg ≧ 0: gate positive bias) that is positively biased with respect to the potential of the source 31 is applied to the gate electrode 28 to increase the gate voltage Vg, and the gate voltage Vg becomes equal to or higher than the gate threshold voltage Vth. The drain current Id starts to flow after the energization, and increases with an increase in the gate voltage Vg. The initial state refers to a state in which a gate negative bias is not applied to the gate electrode 28, that is, a state in which the total time for which the gate negative bias is applied to the gate electrode 28 is 0 (zero) V.

In addition, p⁺The high-concentration region 51 is exposed at the front surface 13a of the semiconductor substrate 10 in the boundary region 3. And, p⁺The high concentration type region 51 extends from the inclined portion 13b and the corner portion 13c of the step 13 to the front surface 13a' of the outer portion of the semiconductor substrate 10, which is the lower surface of the step 13. The corner portion 13c of the step 13 is a boundary between the front surface 13a' of the outer portion of the semiconductor substrate 10, which is the lower surface of the step 13, and the inclined portion 13b of the step 13. p is a radical of⁺The high concentration region 51 is located at the corner 13c of the step 13 in the first direction X and n^-Drift region 22 and first p⁺Type region 37, second p⁺The type region 38 is in contact with the second p in the second direction Y⁺The pattern areas 38 are in contact.

p⁺The high concentration region 51 is aligned with the innermost p of the JTE structure 40 in the first direction X and the second direction Y^-The pattern regions 41 are in contact. p is a radical of⁺The type high concentration region 51 may be oriented more than the first p⁺Type region 37, second p⁺The more outside position of the land 38 extends. At this time, p⁺The high concentration region 51 is in the first p⁺Type region 37, second p⁺P of type region 38 and JTE structure 40^-Between the type regions 41 and n^-The drift region 22 contacts. p is a radical of⁺The entire surface of the type high concentration region 51 is covered with an insulating film composed of the gate insulating film 27, the interlayer insulating film 29, and the field oxide film 44. I.e. p⁺The high concentration region 51 may be in direct contact with the metal film 30. p is a radical of⁺The type high concentration region 51 is electrically connected to the source electrode 31 via the p-type base region extension portion 23' (i.e., the p-type base region 23).

In addition, p⁺The impurity concentration of the type high concentration region 51 is higher than that of the p-type base region 23. p is a radical of⁺The high concentration region 51 has a function of lowering the resistance of the p-type base region 23. By lowering the resistance of the p-type base region 23, the vicinity of the boundary between the edge termination region 2 and the boundary region 3 or the end of the active region 1, in which the electric field is mainly concentrated by avalanche breakdown at the time of turn-off, can be preventedThe potential of p-type base extension portion 23' (i.e., p-type base region 23) increases when the hole current generated in the portion is extracted to source electrode 31. This can alleviate the electric field applied to the thin gate insulating film 27, prolong the life of the gate insulating film 27, and prevent dielectric breakdown of the gate insulating film 27.

In the boundary region 3, a conductive layer 52 made of polysilicon (poly-Si:) and a gate runner 53 made of the same material as the source 31, for example, are provided on the field oxide film 44 (see fig. 2). The conductive layer 52 is electrically connected to all the gate electrodes 28 at the portions not shown. The conductive layer 52 is covered with the interlayer insulating film 29. The gate runner 53 is connected to the conductive layer 52 via a second contact hole 29b penetrating the interlayer insulating film 29 in the depth direction. The conductive layer 52 and the gate runner 53 surround the periphery of the source region 1 in a substantially rectangular shape. The gate runner 53 is connected to the gate pad 32 (see fig. 1).

Although not particularly limited, for example, when the MOSFET of embodiment 1 has a breakdown voltage of 1200V class, the dimensions of each portion and the impurity concentration have the following values. n is⁺The impurity concentration of the type starting substrate 21 is, for example, 1X 10¹⁸/cm³Left and right. n is^-The thickness t11 of type silicon carbide epitaxial layer 11 is, for example, 10 μm. n is^-Type silicon carbide epitaxial layer 11 (n)^-Type drift region 22) has an impurity concentration of, for example, 5 × 10¹⁵/cm³Above and 2X 10¹⁶/cm³Left and right. The impurity concentration of the n-type JFET region 22' is, for example, 1X 10¹⁷/cm³Left and right.

First p⁺The thickness t1 of the pattern region 37 may be, for example, about 0.5 μm. First p⁺The pattern region 37 reaches a depth of about 2 μm from the front surface 13a of the semiconductor substrate 10, for example. Second p⁺The thickness t2 of the pattern region 38 may be, for example, about 1 μm. Second p⁺The type region 38 reaches a depth of about 2 μm from the front surface 13a of the semiconductor substrate 10, for example. First p⁺Type region 37, second p⁺The impurity concentration of the type region 38 is, for example, 1 × 10¹⁷/cm³Above and 1 × 10¹⁹/cm³The following degree may be, for example, 1 × 10¹⁸/cm³Left and right.

The thickness t12 of the p-type silicon carbide epitaxial layer 12 is, for example, about 1 μm. The impurity concentration of the p-type silicon carbide epitaxial layer 12 (p-type base region 23) is, for example, 1 × 10¹⁶/cm³Above and 3 × 10¹⁸/cm³The following degree may be, for example, 1 × 10¹⁷/cm³Left and right. n is⁺The impurity concentration of the source region 24 is, for example, 1 × 10²¹/cm³Left and right. p is a radical of⁺The thickness t3 of the high concentration region 51 is, for example, about 0.5 μm. p is a radical of⁺The impurity concentration of the high concentration region 51 is, for example, 5X 10¹⁸/cm³1X 10 above²¹/cm³The following degrees.

Next, the operation of the silicon carbide semiconductor device according to embodiment 1 will be described. In a state where a positive voltage (source-drain voltage) with respect to the source 31 is applied to the drain 33, a gate voltage Vg smaller than the gate threshold voltage Vth is applied to the gate electrode 28. Thus, the pn junction between p-type base region 23 and n-type drift region 22 is in a reverse bias state, so that the reverse withstand voltage of source region 1 is ensured and leakage current Id does not flow. That is, the MOSFET maintains an off state. At this time, for example, by applying a negative gate bias to the gate electrode 28, the MOSFET can be reliably turned off.

On the other hand, if a gate voltage Vg equal to or higher than the gate threshold voltage Vth is applied to the gate electrode 28 in a state where the source-drain voltage is applied, the channel n of the p-type base region 23 is increased⁺ Source regions 24 and n^-An n-type inversion layer (channel) is formed in a portion of the drift region 22 along the trench 26. Thus, at n⁺ Type starting substrate 21, n^-Drift region 22, surface inversion layer of p-type base region 23, and n⁺The path of source region 24 flows, and the MOSFET is turned on. Thus, the MOSFET can be switched by controlling the gate voltage Vg.

A method for manufacturing a silicon carbide semiconductor device according to embodiment 1 will be described. Fig. 6 and 7 are sectional views showing states in the process of manufacturing the silicon carbide semiconductor device according to embodiment 1. First, at n⁺Front surface of the type starting substrate 21 is n^-The type silicon carbide epitaxial layer 11 is epitaxially grown. Next, by photolithography and ion implantation,at n^-The first p is selectively formed inside the type silicon carbide epitaxial layer 11⁺ Type region 37, second p⁺And a molding region 38. Next, n is increased by epitaxial growth^-Thickness of type silicon carbide epitaxial layer 11, n^-The type silicon carbide epitaxial layer 11 is thickened to a predetermined thickness t 11.

Next, by photolithography and ion implantation, at n^-The surface layer of the type silicon carbide epitaxial layer 11 is formed to be the second p⁺P of type region 38⁺Type region, thereby making the second p⁺Mold region 38 is thickened to a predetermined thickness t 2. n is^-Of type-SiC epitaxial layer 11 other than the first p⁺Type region 37, second p⁺Type region 38 and p formed in subsequent processes^-Type region 41, p^--N is a part other than the n-type region 42 and the n-type channel stop region 43^-A drift region 22. Next, at n^-The surface of the type silicon carbide epitaxial layer 11 epitaxially grows a p-type silicon carbide epitaxial layer 12.

Next, the p-type silicon carbide epitaxial layer 12 is removed over the entire edge termination region 2, and a step 13 is formed on the front surface 13a of the semiconductor substrate 10 so that the edge termination region 2 is lower than the active region 1. Thereby, n is exposed on the front surface 13a' of the semiconductor substrate 10 in the edge termination region 2^-And type silicon carbide epitaxial layer 11. Next, ion implantation is performed using different oxide film masks, thereby selectively forming n in each of the predetermined regions described above⁺ Source region 24, p⁺ Type contact region 25, p⁺ High concentration region 51, JTE structure 40 (p)^- Type region 41, p^--Type region 42) and n-type channel stop region 43.

n⁺Source region 24, p⁺ Type contact region 25, p⁺The formation order of the type high concentration region 51, the JTE structure 40, and the n-type channel stop region 43 may be variously changed. In addition, p⁺The type high concentration region 51 may be in contact with p⁺The type contact region 25 is formed simultaneously. For example, in the formation of n⁺P-type source region 24, JTE structure 40, and n-type channel stop region 43 are then formed⁺ Type contact region 25 and p⁺In the case of the high concentration region 51, first, as shown in fig. 6, the semiconductor substrate 10 is provided with the high concentration regionThe oxide film 61 is deposited over the entire front surface (i.e., the front surfaces 13a and 13a' of the semiconductor substrate 10 and the inclined portion 13b of the step 13).

Next, the oxide film 61 is removed of p by photolithography and etching⁺Formation regions 61a and p of type contact region 25⁺The formation region 61b of the high concentration region 51 corresponds to a portion. Next, ion implantation 62 of a p-type impurity such as aluminum is performed using the remaining portion of the oxide film 61 as a mask (fig. 6). P is formed in a predetermined region of the active region 1 by the ion implantation 62⁺A contact region 25 formed in a predetermined region of the boundary region 3⁺The pattern high concentration region 51 (fig. 7). The conditions for the ion implantation 62 can be set to 350keV for the maximum acceleration energy and 5.15X 10 for the total dose of p-type impurities, as in the conventional case¹⁵/cm²。

Next, a heat treatment (activation annealing) for activating all the impurities subjected to the ion implantation is performed at a temperature of, for example, about 1700 ℃ for about 10 minutes. Next, a trench gate structure is formed by the trench 26, the gate insulating film 27, and the gate electrode 28 using a usual method. After the gate insulating film 27 is formed by, for example, thermal Oxidation, POA (Post Oxidation Anneal) for improving the interface characteristics between the gate insulating film 27 and the semiconductor section may be performed. Next, the field oxide film 44, the interlayer insulating film 29, the metal film 30, the conductive layer 52, the source electrode 31, the gate pad 32, the gate runner 53, and the drain electrode 33 are formed by a usual method, thereby completing the MOSFET shown in fig. 1 to 5.

Next, for the active regions 1 and p as described above⁺The reason why the p-type base extension portion 23' composed of the p-type silicon carbide epitaxial layer 12 is disposed between the high concentration regions 51 will be described. First, a mechanism in which a gain curve (see fig. 26) of the drain current Id in the conventional silicon carbide semiconductor device (see fig. 21 to 25, hereinafter referred to as a conventional structure) is greatly shifted in a negative direction of the gate voltage Vg from an initial state will be described. It is estimated that the shift of the gain curve of the drain current Id is caused by the following 5 items.

Item 1 is a case where p is formed in the p-type silicon carbide epitaxial layer 112⁺The ion implantation of the p-type impurity of the type high concentration region 151 generates a point defect in the p-type silicon carbide epitaxial layer 112. Item 2 is that point defects in the p-type silicon carbide epitaxial layer 112 are not only in p⁺The formation region of the high concentration region 151 is diffused toward the p ratio⁺The outer side of the high concentration region 151 is diffused in a range of several μm in a direction parallel to the front surface of the semiconductor substrate 10 (i.e., a radial direction including the first direction X and the second direction Y).

The 3 rd item is that the point defects in the p-type silicon carbide epitaxial layer 112 become hole traps in the gate insulating film 127 by thermal oxidation (including POA) for forming the gate insulating film 127. The 4 th item is that holes are accumulated at the interface between the p-type base region 123 and the gate insulating film 127 by applying a gate negative bias (for example, the gate voltage Vg is-5V) to the gate electrode 128 of the MOSFET manufactured by the process including the above items under the condition that the semiconductor substrate 110 is at a high temperature (for example, about 125 ℃.

The 5 th item is that a part of holes accumulated at the interface between the p-type base region 123 and the gate insulating film 127 tunnel through and are trapped by hole traps in the gate insulating film 127. Thereby, the gain curve of the drain current Id is greatly shifted in the negative direction of the gate voltage Vg as compared with the initial state. These 5 items are in the vicinity of the electrical connection position between the gate electrode 128 and the gate runner 153 for applying the gate voltage Vg to the gate electrode 128, that is, n⁺The vicinity of the outer periphery of source region 124 is conspicuously present.

Since the above 5 items are in n⁺The vicinity of the outer periphery of the source region 124 is significantly reflected, so that the gain curve of the drain current Id is shifted only in the rising region of the drain current Id. Therefore, in the 3 rd item, p can be made to be p as in the present invention with respect to the diffusion length of the point defect including the 2 nd item so that the point defect does not diffuse into the gate insulating film 27⁺ High concentration regions 51 and n⁺The source region 24 is sufficiently separated from the active region 1 by p⁺The p-type silicon carbide epitaxial layer 12 having no crystal defects is disposed between the high concentration regions 51.

(example 1)

Next, the first distance to the silicon carbide semiconductor device n of embodiment 1 is setAnd verifying by X1 and a second distance Y1. Fig. 8 is a characteristic diagram showing the result of verification of the first distance in example 1. The horizontal axis of FIG. 8 is the slave p in the first direction X⁺A type high concentration region 51 to n⁺The vertical axis of the first distance X1 of the source region 24 is the maximum value of the change Δ Vg of the gate positive bias voltage generated within a predetermined time period in which the temporal change of the gate positive bias voltage is observed. First, a plurality of n-channel MOSFETs each having a trench gate structure and having the structure of the silicon carbide semiconductor device according to embodiment 1 described above are manufactured (hereinafter, referred to as example 1). The first distances X1 of the samples of example 1 were different from each other. P is to be⁺The aluminum dose of the type high concentration region 51' was set to 5.15X 10¹⁵/cm²。

For each sample of example 1, a gate voltage Vg of-5V (gate negative bias) was applied to the gate electrode 28 for a predetermined application time in a high-temperature atmosphere of 200 ℃ with the source 31 and the drain 33 grounded. Then, a gate negative bias was applied to the gate electrode 28 for an arbitrary application time, and a gate positive bias was applied to the gate electrode 28 in a room temperature atmosphere to apply current thereto, and the gate positive bias was measured, whereby the change with time from the initial state of the gate positive bias was observed for 1000 hours. The application time of the gate negative bias applied to the gate electrode 28 increases at a predetermined time from 0 hour (initial state) to 1000 hours.

The current amount of the drain current Id becomes one thousandth of the rated current, I1/I0 (═ 10)^-3) The first measurement point (corresponding to reference numeral 171 in fig. 26) and the current amount Id2/I0 (10 ppm) at which the current amount of the drain current Id becomes one millionth of the current amount of the drain current Id1 at the first measurement point^-9) The second measurement point (corresponding to reference numeral 172 in fig. 26) of (b) is observed as a change with time of the gate positive bias from the initial state. Fig. 8 shows the result of comparing the maximum values of the amount of change Δ Vg of the gate positive bias voltage with respect to the initial state, which corresponds to the current amounts of the drain current Id at the first measurement point and the second measurement point. In FIG. 8, the sample having the first distance X1 of 0.0 μm corresponds to p⁺Type high concentration region 151 and n⁺Conventional structure of source region 124 contact (seeFig. 21 to 25).

From the results shown in FIG. 8, it was confirmed that p was moved in the first direction X from the first measurement point to the second measurement point⁺A type high concentration region 51 to n⁺The first distance X1 of the source region 24 is set to 0.6 μm or more, and the amount of change Δ Vg of the gate positive bias voltage with respect to the initial state corresponding to the current amount of the drain current Id can be reduced as compared with the conventional structure. Decreasing the amount of change Δ Vg of the gate positive bias with respect to the initial state means decreasing the absolute value of the amount of change Δ Vg of the gate positive bias with respect to the initial state. Specifically, if the first distance X1 is set to 0.6 μm or more, for example, even at the second measurement point where the gate positive bias is closer to the gate threshold voltage Vth than the first measurement point, the amount of change Δ Vg of the gate positive bias with respect to the initial state according to the current amount of the drain current Id can be reduced from-1.45V (sample of the data point indicated by the symbol 71) to about-0.8V (sample of the data point surrounded by the circle of the symbol 72) in the conventional configuration.

Although not shown, even though p is to be the second direction Y⁺The same results as those shown in fig. 8 were obtained even when the second distance Y1 between the high concentration type region 51 and the outermost trench 26 was set to 0.6 μm or more.

As described above, according to embodiment 1, n is aligned with n in the first direction⁺The p constituting the boundary region between the active region and the edge termination region is arranged separately from the source region, separately from the outermost trench in the second direction, or separately from both of them⁺And a high concentration region. In a first direction by p⁺A high concentration region and n⁺The part sandwiched by the source region, or p in the second direction⁺The portion sandwiched between the type high concentration region and the outermost trench or both portions are exposed on the front surface of the semiconductor substrate in the p-type silicon carbide epitaxial layer. Thus, the portion of the p-type base region extension portion adjacent to the gate insulating film is a p-type silicon carbide epitaxial layer free from crystal defects. Therefore, generation of hole traps due to crystal defects in the gate insulating film can be suppressed at the time of thermal oxidation of the gate insulating film.

By suppressing the generation of hole traps in the gate insulating film in this manner, when a gate negative bias is applied to the gate electrode under high temperature conditions, accumulation of holes at the interface between the p-type base region and the gate insulating film can be suppressed. Thus, even if a gate negative bias is applied to the gate electrode in order to maintain the off state under a high temperature condition, the amount of change in the gate positive bias corresponding to a predetermined amount of current of the leakage current from that in the initial state can be reduced. Further, when the gate voltage of 0V or less is applied to the gate electrode and the off state is maintained, the amount of drain off current can be made close to that in the initial state. Therefore, the gain curve of the leakage current can be suppressed from shifting in the negative direction of the gate voltage compared to the initial state, and the current controllability by the gate voltage control can be improved.

(embodiment mode 2)

Next, the structure of the silicon carbide semiconductor device according to embodiment 2 will be described. Fig. 9 is a plan view showing a layout of a part of the silicon carbide semiconductor device according to embodiment 2 as viewed from the front surface side of the semiconductor substrate. Fig. 9 shows a state in the vicinity of the boundary between the active region 1 and the boundary region 3 in the vicinity of the corner of the semiconductor substrate 10 surrounded by a rectangular frame whose vertex B, B' in fig. 1 is a diagonal vertex. The positions of the vertices B and B' corresponding to the semiconductor substrate 10 are the same as those in embodiment 1. The sectional structure at the cutting line C-C 'of fig. 9 is a structure of fig. 4 obtained by replacing the symbol X1 with X1'. The sectional structure at the cutting line D-D' of fig. 9 is the same as that of fig. 5.