阅读说明：本技术 超大规模集成电路工艺的后道互连寄生电容电阻的建模方法 (Modeling method for back-end interconnection parasitic capacitance resistance of super-large-scale integrated circuit process ) 是由 禚越 田明 王昌锋 李相龙 刘人华 孙亚宾 李小进 石艳玲 廖端泉 曹永峰 于 2019-09-25 设计创作，主要内容包括：本发明公开了一种超大规模集成电路工艺的后道互连寄生电容电阻的建模方法,互连技术文档(ITF)是表征晶体管制备过程中工艺波动的文件,包含不同金属层数、不同线宽、不同间距和不同密度条件下的厚度尺寸与线宽尺寸等波动因素。该方法在提取后道寄生电容的波动参数部分,结合Raphael工具仿真数据与晶圆测试中值,通过StarRC工具校准提取出电容相关厚度与线宽尺寸波动参数。在提取后道寄生电阻的波动参数部分,将在寄生电容提取过程中得到的厚度与线宽尺寸波动代入到寄生电阻的提取中,然后对电阻的电阻率值进行计算、校准拟合。结果显示,本发明对于后道电容电阻的波动尺寸因素实现了一致性匹配,有效降低了后道电容电阻的StarRC抽取值与晶圆测试中值的误差。(The invention discloses a modeling method of a back-end interconnection parasitic capacitance resistor of a super-large-scale integrated circuit process, wherein an interconnection technology document (ITF) is a file for representing process fluctuation in a transistor preparation process and comprises fluctuation factors such as thickness sizes, line width sizes and the like under the conditions of different metal layer numbers, different line widths, different intervals and different densities. According to the method, in the part of extracting fluctuation parameters of the subsequent parasitic capacitance, the fluctuation parameters of the capacitance related thickness and the line width size are extracted through the StarRC tool calibration by combining Raphael tool simulation data and a wafer test median value. And substituting the fluctuation of the thickness and the line width obtained in the parasitic capacitance extraction process into the extraction of the parasitic resistance in the fluctuation parameter part of the extracted subsequent parasitic resistance, and then calculating, calibrating and fitting the resistivity value of the resistance. The result shows that the method realizes the consistency matching of the fluctuation size factor of the subsequent capacitance resistor, and effectively reduces the error between the StarRC extraction value of the subsequent capacitance resistor and the wafer test median value.)

1. A modeling method for a back-end interconnection parasitic capacitance resistance of a very large scale integrated circuit process is characterized by comprising the following specific steps:

step 1: designing and extracting a test structure of the same-layer parasitic layer and the adjacent-layer parasitic layer of the next metal interconnection layer, manufacturing a test structure of the parasitic capacitance resistance of the next metal interconnection layer, measuring the electrical characteristics of the capacitance resistance of the test structure of the metal interconnection layer, and obtaining data called a wafer test median value;

step 2: extracting process fluctuation parameters of a subsequent interconnection parasitic capacitance part

Reducing a test structure of a metal interconnection layer by using a RaphaelRC2 tool, collecting the fluctuation information reference of a subsequent interconnection process by combining a transmission electron microscope slice, adjusting the process fluctuation size of thickness size fluctuation and line width size fluctuation at different line widths and intervals, writing in a RaphaelRC2 file, and performing simulation on a same-layer parasitic capacitance structure and an adjacent-layer parasitic capacitance structure to solve the capacitance value; recording the size process fluctuation of the metal interconnection layer and the process fluctuation of the thickness of the intermetallic medium layer, and writing the size process fluctuation and the process fluctuation into an interconnection technology document;

and step 3: capacitance extraction of interconnect technology documents using StarRC and comparison to wafer test median

For the test structure with the deviation larger than 10%, carrying out calibration fitting on the process size fluctuation corresponding to the test structure again, repeating the step 2, reducing the error between the capacitance data extracted by the StarRC and the wafer test median value to at most 10%, and determining the size process fluctuation of the metal interconnection layer and the process fluctuation of the thickness of the intermetallic dielectric layer;

and 4, step 4: extracting process fluctuation parameters of a back-end interconnection parasitic resistance part

Directly adopting thickness dimension fluctuation and line width dimension fluctuation parameters obtained in the parasitic capacitance correcting process in the step 3, taking a wafer test median value of resistance structures with different metal line widths and intervals as a target value of resistance modeling, substituting size information of the resistance, metal thickness dimension fluctuation and line width dimension fluctuation values, calculating to obtain the resistivity corrected by considering fluctuation factors, and writing the resistivity into an interconnection technology document;

and 5: resistance extraction of interconnect technology documents using StarRC and comparison to wafer test median

And (4) performing calibration fitting on the resistivity fluctuation corresponding to the test structure again for the test structure with the deviation larger than 10%, repeating the step 4, reducing the error between the resistance data extracted by the StarRC and the wafer test median value to at most 10%, and determining the dimensional process fluctuation of the metal interconnection layer and the process fluctuation of the metal resistivity.

2. The method for modeling the parasitic capacitance and resistance of the subsequent interconnect according to claim 1, wherein the calculating in step 4 to obtain the resistivity corrected in consideration of the fluctuation factor specifically comprises:

the metal sheet resistance was calculated according to equation (1):

R_square＝R_es*(WIDTH-2*ETCH)/L (1)

in the formula (1), R_squareIs a metal square resistor, R_esThe method comprises the following steps of (1) obtaining actual test data of a key test case, wherein WIDTH is the metal line WIDTH of the key test case, ETCH is line WIDTH size fluctuation, and L is the metal length of the key test case;

the post-fluctuation corrected resistivity is calculated according to equation (2):

RHO＝R_square*T*(1-THICKNESS) (2)

in the formula (2), RHO is the metal resistivity, T is the metal layer thickness, and THICKNESS is the thickness dimensional fluctuation.

3. The method as claimed in claim 1, wherein in the step 5, the thickness size fluctuation and the line width size fluctuation are not modified during the calibration and fitting of the resistivity fluctuation, the calculated resistivity is used as a parameter to perform the comparison and calibration of the StarRC extracted value and the wafer test median value, and the thickness size fluctuation and the line width size fluctuation extracted from the parasitic capacitance and the calibrated resistivity are used to represent the fluctuation of the parasitic resistance of the next interconnect.

Technical Field

The invention belongs to the field of preparation technology and technology fluctuation parameter representation and extraction in a Complementary Metal Oxide Semiconductor (CMOS) very large scale integrated circuit (VLSI), and particularly relates to a modeling method of a subsequent interconnection parasitic capacitance resistor of a very large scale integrated circuit technology.

Background

Extraction of Parasitic parameters (LPE) of an integrated circuit Layout is a key step of design and verification of an integrated circuit, and objects extracted by the Extraction are mainly classified into two types: firstly, aiming at a front-end process, parasitic active devices such as parasitic field effect transistors and the like possibly existing in a layout are identified and extracted; and the other type is to identify and extract equivalent parasitic resistance, parasitic capacitance and the like of the interconnection line in the layout aiming at the back-end process. The related tool for extracting the parasitic parameters of the integrated circuit layout calculates the values of the parasitic components by reading the geometric parameters and the fluctuation parameters of the layout, outputs netlist files in formats of SPICE and the like, and provides the netlist files for integrated circuit simulation software to carry out circuit simulation. With the continuous updating of the technology generation, the time delay of the interconnection line in the nanoscale integrated circuit is gradually increased, and the time delay exceeding the time delay of a semiconductor device becomes a main factor influencing the time sequence of the integrated circuit. Therefore, accurate fitting of the delay of the multilayer interconnection lines is crucial to correctly evaluating the performance of a high-end chip, and the accuracy of the parameter extraction method greatly affects the accuracy of circuit simulation, so that the accuracy of extraction of parasitic parameters of the interconnection lines is increasingly critical. As integrated circuits enter the nanometer era, the critical dimensions of integrated circuits are becoming smaller and smaller, and the feature sizes of integrated circuit interconnects are also becoming smaller. This continued scaling has resulted in an increasing number of process parameters for interconnect lines, including metal interconnect resistivity, dielectric constant of dielectric layers, and the like. At the same time, integrated circuit interconnects are more susceptible to process fluctuations in semiconductor chip fabrication.

Conventional methods for extracting RC parasitic parameters of interconnection lines generally define typical values of process parameters (such as metal layer thickness, dielectric layer thickness, etc.) one by one in an interconnection technology document, and generate extraction rules based on the typical values. Under the condition that the parasitic capacitance and the parasitic resistance are extracted in the back channel, the fluctuation of the parasitic resistance and the parasitic capacitance can be extracted according to the measured data of the silicon chip and the calculation data of the StarRC. Therefore, by adopting the traditional method, under the same set of process conditions, the thickness size fluctuation and the line width size fluctuation based on the parasitic capacitance and the thickness size fluctuation and the line width size fluctuation based on the parasitic resistance are obtained, and the thickness size fluctuation of the parasitic capacitance and the thickness size fluctuation of the parasitic resistance are different, so that the problem of unmatched fluctuation of the parasitic resistance and the parasitic capacitance is also generated.

Disclosure of Invention

The invention aims to provide a new modeling method aiming at the improvement of parameter extraction flow in the current modeling method of the back-end interconnection parasitic capacitance resistor of the super-large-scale integrated circuit process, which overcomes the problem of unmatched size parameters of capacitance resistor fluctuation of the original method, and simultaneously realizes better matching between StarRC extracted simulation data and silicon wafer measurement data according to the interconnection technical document extracted by the method.

The specific technical scheme for realizing the purpose of the invention is as follows:

a modeling method for a back-end interconnection parasitic capacitance resistance of a very large scale integrated circuit process is characterized by comprising the following specific steps:

step 1: designing and extracting a test structure of the same-layer parasitic layer and the adjacent-layer parasitic layer of the next metal interconnection layer, manufacturing a test structure of the parasitic capacitance resistance of the next metal interconnection layer, measuring the electrical characteristics of the capacitance resistance of the test structure of the metal interconnection layer, and obtaining data called a wafer test median value;

step 2: extracting process fluctuation parameters of a subsequent interconnection parasitic capacitance part

Reducing a test structure of a metal interconnection layer by using a RaphaelRC2 tool, collecting the fluctuation information reference of a subsequent interconnection process by combining a transmission electron microscope slice, adjusting the process fluctuation size of thickness size fluctuation and line width size fluctuation at different line widths and intervals, writing in a RaphaelRC2 file, and performing simulation on a same-layer parasitic capacitance structure and an adjacent-layer parasitic capacitance structure to solve the capacitance value; recording the size process fluctuation of the metal interconnection layer and the process fluctuation of the thickness of the intermetallic medium layer, and writing the size process fluctuation and the process fluctuation into an interconnection technology document;

and step 3: capacitance extraction of interconnect technology documents using StarRC and comparison to wafer test median

For the test structure with the deviation larger than 10%, carrying out calibration fitting on the process size fluctuation corresponding to the test structure again, repeating the step 2, reducing the error between the capacitance data extracted by the StarRC and the wafer test median value to at most 10%, and determining the size process fluctuation of the metal interconnection layer and the process fluctuation of the thickness of the intermetallic dielectric layer;

and 4, step 4: extracting process fluctuation parameters of a back-end interconnection parasitic resistance part

Directly adopting thickness dimension fluctuation and line width dimension fluctuation parameters obtained in the parasitic capacitance correcting process in the step 3, taking a wafer test median value of resistance structures with different metal line widths and intervals as a target value of resistance modeling, substituting size information of the resistance, metal thickness dimension fluctuation and line width dimension fluctuation values, calculating to obtain the resistivity corrected by considering fluctuation factors, and writing the resistivity into an interconnection technology document;

and 5: resistance extraction of interconnect technology documents using StarRC and comparison to wafer test median

And (4) performing calibration fitting on the resistivity fluctuation corresponding to the test structure again for the test structure with the deviation larger than 10%, repeating the step 4, reducing the error between the resistance data extracted by the StarRC and the wafer test median value to at most 10%, and determining the dimensional process fluctuation of the metal interconnection layer and the process fluctuation of the metal resistivity.

According to the method, after the wafer test median is obtained, the fluctuation parameters of the subsequent interconnection capacitor are preferentially extracted without adopting a mode of respectively extracting the fluctuation parameters of the capacitor and the resistor.

And (4) directly applying the thickness size fluctuation and the line width size fluctuation obtained by extracting the capacitance of the subsequent metal interconnection layer obtained in the step (3) to the fluctuation parameter extraction of the subsequent parasitic resistance.

And 4, calculating to obtain the resistivity corrected by considering the fluctuation factor, wherein the calculation specifically comprises the following steps:

the metal sheet resistance was calculated according to equation (1):

R_square＝R_es*(WIDTH-2*ETCH)/L (1)

in the formula (1), R_squareIs a metal square resistor, R_esThe method comprises the following steps of (1) obtaining actual test data of a key test case, wherein WIDTH is the metal line WIDTH of the key test case, ETCH is line WIDTH size fluctuation, and L is the metal length of the key test case;

the post-fluctuation corrected resistivity is calculated according to equation (2):

RHO＝R_square*T*(1-THICKNESS) (2)

in the formula (2), RHO is the metal resistivity, T is the metal layer thickness, and THICKNESS is the thickness dimensional fluctuation.

And 5, when the resistivity fluctuation is calibrated and fitted, the thickness size fluctuation and the line width size fluctuation are not modified, the calculated resistivity is used as a parameter to carry out comparison and calibration of a StarRC extraction value and a wafer test median value, and the fluctuation of the subsequent interconnection parasitic resistance is represented by the thickness size fluctuation, the line width size fluctuation and the calibrated resistivity extracted by the parasitic capacitance.

According to the modeling method for the back-end interconnection parasitic capacitance resistance of the super-large-scale integrated circuit process, after the wafer test median value is obtained, the modeling mode for the capacitance and the resistance is not adopted independently, but the modeling for the back-end interconnection capacitance is preferentially carried out. According to the thickness size fluctuation and the line width size fluctuation extracted from the subsequent interconnection capacitance, the result is substituted into the modeling of the subsequent parasitic resistance, the fluctuation of the subsequent interconnection parasitic resistance is represented by the thickness size fluctuation and the line width size fluctuation extracted from the parasitic capacitance and the calibrated resistivity by calculating the resistivity and calculating and calibrating the resistivity, and therefore the problem that the capacitance size fluctuation and the resistance size fluctuation are inconsistent when the parasitic capacitance resistance is extracted independently for modeling originally is solved. The result shows that in the back-end parasitic resistance modeling, the fluctuation factors extracted by the method are written into the interconnection technology document, and the error between the StarRC simulation data of the back-end parasitic resistance and the wafer test median is effectively reduced.

Drawings

FIG. 1 is a flow chart of the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and examples.