阅读说明：本技术 用于减少闪存存储器系统中字线和控制栅极线之间的耦合的方法和装置 (Method and apparatus for reducing coupling between word lines and control gate lines in a flash memory system ) 是由 钱晓州 K.M.岳 罗光燕 于 2018-06-15 设计创作，主要内容包括：用于减少闪存存储器系统中字线和控制栅极线之间的耦合的方法和装置。本发明公开了一种方法和装置,以用于减少由于寄生电容和寄生电阻而导致闪存存储器系统中的字线和控制栅极线之间原本可能出现的耦合。所述闪存存储器系统包括被组织成行和列的闪存存储器单元的阵列,其中每行被耦合到字线和控制栅极线。(Methods and apparatus for reducing coupling between word lines and control gate lines in a flash memory system. A method and apparatus for reducing coupling that may otherwise occur between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system includes an array of flash memory cells organized into rows and columns, where each row is coupled to a word line and a control gate line.)

1. A flash memory system, comprising:

an array of flash memory cells, wherein the flash memory cells are organized into rows and columns, and each flash memory cell includes a word line terminal, a control gate terminal, and a floating gate;

a plurality of word lines, each word line of the plurality of word lines coupled to the word line terminals of the flash memory cells in a row of the array;

a plurality of control gate lines, each control gate line of the plurality of control gate lines coupled to the control gate line terminals of the flash memory cells in a row of the array; and

a decoupling circuit that couples control gate lines of a selected row for a read operation to a first voltage source and couples control gate lines of an unselected row for the read operation to a second voltage source, wherein a voltage generated by the second voltage source is less than the voltage generated by the first voltage source by an amount of Δ V;

wherein Δ V is approximately equal to an increase in voltage of the control gate line of the selected row, the increase in voltage being generated due to parasitic capacitance between the control gate line of the selected row and the word line of the selected row when the word line of the selected row is driven high.

2. The flash memory system of claim 1, wherein the decoupling circuit comprises a first switch to selectively couple the first voltage source to a selected row of a read operation and a second switch to selectively couple the second voltage source to one or more unselected rows of a read operation.

3. The flash memory system of claim 1, wherein the flash memory cells are split gate flash memory cells.

4. The flash memory system of claim 2, wherein the flash memory cells are split gate flash memory cells.

5. A method of decoupling a control gate line from an adjacent word line in a flash memory system during a read operation, the flash memory system comprising: an array of flash memory cells organized into rows and columns; a plurality of word lines, wherein each word line of the plurality of word lines is coupled to the word line terminals of the flash memory cells in a row of the array; and a plurality of control gate lines, wherein each control gate line of the plurality of control gate lines is coupled to the control gate line terminals of the flash memory cells in a row of the array, each flash memory cell including a word line terminal, a control gate terminal, and a floating gate, the method comprising:

coupling the control gate lines of the selected row for a read operation to a first voltage source;

coupling control gate lines of unselected rows for the read operation to a second voltage source, wherein the voltage generated by the second voltage source is less than the voltage generated by the first voltage source by an amount Δ V; and

coupling a word line of the selected row for the read operation to a third voltage source;

wherein the voltage of the control gate line for the selected row increases by an amount approximately equal to Δ V after the word line for the selected row is coupled to the third voltage source due to parasitic capacitance between the control gate line for the selected row and the word line for the selected row.

6. The method of claim 5, wherein the step of coupling a control gate line of a selected row for a read operation to a first voltage source comprises closing a switch between the control gate line of the selected row for a read operation and the first voltage source.

7. The method of claim 6, wherein the step of coupling control gate lines of an unselected row for a read operation to a second voltage source comprises closing a switch between the control gate lines of the unselected row for a read operation and the second voltage source.

8. The method of claim 5, wherein the flash memory cell is a split gate flash memory cell.

9. The method of claim 6, wherein the flash memory cell is a split gate flash memory cell.

10. The method of claim 7, wherein the flash memory cell is a split gate flash memory cell.

Technical Field

A method and apparatus for reducing coupling that may otherwise occur between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.

Background

Digital non-volatile memories are well known. For example, fig. 1 depicts a four gate split gate flash memory cell comprising a source region 101, a drain region 102 (coupled to a bit line 24), a floating gate 103 over a first portion of a channel region 104, a word line terminal 105 (typically coupled to a word line) over a second portion of the channel region 104, a substrate 108, a control gate 106 (typically coupled to a control gate line) over the floating gate 103, and an erase gate 107 (typically coupled to an erase gate line) over the source region 101. Such a configuration is disclosed in U.S. patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates except the floating gate 103, which means that they are electrically connected or connectable to a voltage source. Programming of the memory cell 100 occurs by injecting heated electrons from the channel region 104 into the floating gate 103. The erasure of the memory cell 100 occurs by tunneling electrons from the floating gate 103 to the erase gate 107.

Table 1 depicts typical voltage ranges that may be applied to the terminals of the memory cell 100 to perform read, erase and program operations:

table 1: operation of the flash memory cell 100 of FIG. 1

	WL	BL	CG	EG	SL
						Reading	1.0-2V	0.6-2V	0-2.6V	0-2.6V	0V
Erasing	-0.5V/0V	0V	0V/-8V	8-12V	0V
						Programming	1V	1μA	8-11V	4.5-9V	4.5-5V

Fig. 2A shows a prior art flash memory system 200 including a cell array 100 arranged in rows and columns. Only two rows and six columns are shown here, but it should be understood that the array may include any number of rows and any number of columns. The cell 100 in this example is of the type shown in figure 1.

In the first row of cells shown in FIG. 2A, a word line 201 is connected to each word line terminal 105 of each cell 100 in the row, a control gate line 202 is connected to each control gate terminal 106 of each cell 100 in the row, and an erase gate 203 is connected to each erase gate terminal 107 of each cell 100 in the row.

In the second row of cells shown in FIG. 2A, word line 205 is connected to each word line terminal 105 of each cell 100 in the row, control gate line 204 is connected to each control gate terminal 106 of each cell 100 in the row, and erase gate 203 is connected to each erase gate terminal 107 of each cell 100 in the row. Notably, the erase gate line 203 is connected to the erase gate terminal 107 of each cell 100 in the first and second rows.

Referring to fig. 2B, the close proximity of the word lines, control gate lines, and floating gates creates parasitic effects. Specifically, parasitic capacitances will exist between adjacent word lines and control gate lines, such as between word line 201 and control gate line 202, and between word line 205 and control gate line 204, and parasitic capacitances will also exist between word line 201 and the floating gate of each cell 100 in the first row, and between word line 205 and the floating gate of each cell 100 in the second row.

The parasitic capacitance can be modeled in the following way: (1) a parasitic capacitor 210 located within each cell 100 with one terminal connected to a word line and one terminal connected to a control gate line, and (2) a parasitic capacitor 220 located within each cell 100 with one terminal connected to a word line and one terminal connected to the floating gate 103 within the cell.

The effect of the parasitic capacitor 210 is that there is a voltage coupling between adjacent word lines and control gate lines that is responsive to voltage changes on the word lines and/or control gate lines. The effect of the parasitic capacitor 220 is that there is a voltage coupling between the word line and the floating gate within each cell 100 that is responsive to voltage variations on the word line and/or floating gate.

The parasitic capacitors 210 and 220 will cause the word and control gate lines to take longer to charge to a particular voltage and discharge longer. During discharge, the parasitic capacitance has the undesirable effect of changing the current through each cell 100, which can lead to read errors. As a result, the error margin of the read sensing operation is reduced. The problem is exacerbated as the switching speeds of the word and control gate lines increase.

In addition, each word line and control gate line will have a significant parasitic resistance. This resistance is due to the relatively small size and line width of the device. The parasitic resistance can be modeled with parasitic resistors 230 located between the cells 100 in each row.

Fig. 3 provides an example of the negative effects of such parasitic capacitance and parasitic resistance. In this example, word line 201 is selected for a read operation and driven high. The voltage on control gate line 202 is driven from V due to coupling with word line 201_CGIncrease to V_CG+ Δ V, then discharge down to V_CG. After the word line 201 discharges, the control gate 202 discharges to V_CGΔ V, then charge back to V_CG。

The additional Δ V on control gate line 202 causes an increase in cell current during a read operation. If the read operation fails to provide enough time for the control gate line 202 to go from V_CGDischarge of- Δ V to V_CGThen the selected cell storing a "0" may be misinterpreted as containing a "1". To avoid this problem, the switching speed must allow a discharge period of about 10 nanoseconds. Therefore, parasitic capacitance and parasitic resistance will result in a less accurate system.

What is needed is a flash memory system that reduces parasitic capacitance between word lines and control gate lines and between word lines and floating gates in a flash memory system.

Disclosure of Invention

A method and apparatus for reducing the coupling that may occur between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.

Drawings

Fig. 1 depicts a cross section of a prior art flash memory cell.

Fig. 2A depicts a portion of a prior art flash memory cell array.

Fig. 2B depicts parasitic capacitance and parasitic resistance in the prior art flash memory cell array of fig. 2A.

Fig. 3 depicts exemplary waveforms illustrating the effects of parasitic capacitance and parasitic resistance on control gate lines during a read operation.

Fig. 4 depicts an embodiment of a decoupling circuit.

Fig. 5 depicts exemplary waveforms of the system of fig. 4.

Fig. 6 depicts another embodiment of a decoupling circuit.

Detailed Description

Fig. 4 depicts a flash memory system 400. Flash memory system 400 is similar to flash memory system 200, but with the addition of decoupling circuit 410. Decoupling circuit 410 includes switches 401 and 402. During a read operation, the control gate of the selected rowThe line is coupled to a voltage V through a switch 401_CGAnd the control gate lines of the unselected rows are coupled to a voltage V through a switch 402_CG-ΔV。

The effect of the decoupling circuit 410 is depicted in fig. 5. In this example, word line 201 is selected for a read operation and driven high. Switch 401 is closed and the voltage of control gate line 202 is driven down to V_CG. When the word line 201 is driven high, the control gate line 202 is driven from V_CGΔ V is driven to V_CGΔ V + Δ V (which equals V)_CG) This is the desired voltage level of the control gate line for the selected row during the read operation. After the word line 201 discharges, the control gate line 202 will discharge back to V_CG-ΔV。

Another embodiment is shown in fig. 6. Decoupling circuit 600 (which may be used in place of decoupling circuit 410) includes switches 601, 602, 603, 604, 605 and 606 and inverter 607. During a read operation involving a row of word lines 201 and control gates 202, the word lines 201 will be driven high. The switch 602 will remain open. The output of inverter 607 will go low and switch 601 will close. Switches 604 and 605 will also be closed, so that a voltage V is provided_CGTo the control gate line 202.

In the case where a row of word lines 201 and control gates 202 is not selected, word lines 201 will go low. Switch 602 will be closed. The output of inverter 607 will go high and switch 601 will be open. Switches 604 and 605 will also be closed, so that a voltage V is provided_CGΔ V to the control gate line 202.

During a programming operation, switches 603 and 604 will be closed such that a voltage vep (hv) will be provided to the control gate line 202.

During an erase operation, the switch 606 will be closed so that the control gate line 202 will be pulled to ground.

It should be noted that, as used herein, the terms "over.. and" on.. include both "directly over.. above" (with no intervening material, element, or space disposed therebetween) and "indirectly over.. above" (with intervening material, element, or space disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space disposed therebetween) and "indirectly adjacent" (intermediate material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intermediate material, element, or space disposed therebetween) and "indirectly mounted to" (intermediate material, element, or space disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intermediate material or element therebetween that electrically connects the elements together) and "indirectly electrically coupled to" (intermediate material or element therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intervening materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials/elements therebetween.