阅读说明：本技术 源极和漏极上具有不同硅化物的纳米线mosfet (Nanowire MOSFET with different silicides on source and drain ) 是由 让-皮埃尔·科林格 林正堂 江国诚 卡洛斯·H.·迪亚兹 于 2014-02-08 设计创作，主要内容包括：本发明提供了一种纳米线场效应晶体管(FET)器件以及用于形成纳米线FET器件的方法。形成包括源极区和漏极区的纳米线FET。纳米线FET还包括连接源极区和漏极区的纳米线。在源极区上形成源极硅化物,并且在漏极区上形成漏极硅化物。源极硅化物由第一材料组成,该第一材料不同于漏极硅化物包括的第二材料。本发明提供了源极和漏极上具有不同硅化物的纳米线MOSFET。(The invention provides a nanowire Field Effect Transistor (FET) device and a method for forming the nanowire FET device. A nanowire FET is formed that includes a source region and a drain region. The nanowire FET further comprises a nanowire connecting the source region and the drain region. A source silicide is formed on the source region and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material that the drain silicide comprises. The present invention provides nanowire MOSFETs with different suicides on the source and drain.)

1. A method for forming a nanowire field effect transistor device, the method comprising:

forming a nanowire field effect transistor comprising a nanowire, wherein the nanowire comprises a protrusion of a source region and a drain region;

forming a spacer layer on sidewalls of the nanowire;

forming a source silicide on the source region;

removing the spacer from all nanowires to expose sidewalls of the nanowires and form a space between the protrusion and the source silicide; and

a drain silicide is formed on the drain region.

2. The method for forming a nanowire field effect transistor device of claim 1, wherein the source silicide comprises a first material different from a second material of which the drain silicide comprises.

3. The method for forming a nanowire field effect transistor device of claim 1, further comprising:

forming the source silicide in a first time period;

forming a gate stack after the first time period, wherein the gate stack surrounds a portion of the nanowire and forms the gate stack within a second time period; and

forming the drain silicide after the second time period, wherein a higher thermal budget is applied to the source silicide than to the drain silicide.

4. The method of claim 1, wherein the first material is MoSi₂、WSi₂、TiSi₂、TaSi₂Or NiCoSi₂。

5. The method of claim 1, wherein the second material is NiSi₂Or PtSi₂。

6. The method for forming a nanowire field effect transistor device of claim 1, further comprising:

masking the drain region; and

forming the source silicide on the source region, wherein the masking prevents the source silicide from forming on the drain region.

7. The method for forming a nanowire field effect transistor device of claim 1, further comprising:

masking the source region; and

forming the drain silicide on the drain region, wherein the masking prevents the drain silicide from forming on the source region.

8. The method for forming a nanowire field effect transistor device of claim 1, wherein the nanowire field effect transistor is a first vertical nanowire field effect transistor, the method further comprising:

forming a well of a first conductivity type in a semiconductor substrate;

forming the nanowire with: i) a first end, and ii) a second end opposite the first end, the nanowire extending perpendicularly from the well at the first end;

masking a second end of the nanowire; and

forming the source silicide, wherein the masking prevents the source silicide from forming at the second end of the nanowire and the drain region is adjacent the second end of the nanowire.

9. The method for forming a nanowire field effect transistor device of claim 8, further comprising:

a nitride hard mask is used to mask the second end of the nanowire.

10. The method for forming a nanowire field effect transistor device of claim 8, further comprising:

forming the well, wherein the first conductivity type of the well is P-type;

performing a doping implant to form source and drain regions of the first vertical nanowire field effect transistor, the doping implant causing the source and drain regions to have an N-type conductivity type, wherein the doping implant:

forming the drain region at a second end of the nanowire,

forming a first portion of the source region at a first end of the nanowire, and

forming a second portion of the source region in the well; forming the source silicide on the second portion of the source region, wherein the source silicide is not formed on the first portion of the source region; and

forming the drain silicide on the drain region, wherein the drain silicide is disposed on top of the nanowire at the second end and has a geometry that is different from a geometry of the source silicide.

11. The method for forming a nanowire field effect transistor device of claim 10, further comprising:

forming a gate stack, wherein the gate stack surrounds a portion of the nanowire; and

forming a dielectric layer disposed above or below the gate stack, wherein the gate stack or the dielectric layer prevents the drain silicide from forming on the source region.

12. The method for forming a nanowire field effect transistor device of claim 10, further comprising:

forming a second vertical nanowire field effect transistor, wherein the second vertical nanowire field effect transistor comprises a second source region, a second drain region, a second nanowire connecting the second source region and the second drain region, a second source silicide, and a second drain silicide;

forming a gate stack, wherein the gate stack surrounds a first portion of the nanowires of the first vertical nanowire field effect transistor and the second vertical nanowire field effect transistor;

forming a first dielectric layer disposed below the gate stack, wherein the first dielectric layer surrounds a second portion of the nanowires of the first vertical nanowire field effect transistor and the second vertical nanowire field effect transistor;

forming a second dielectric layer disposed over the gate stack, wherein the second dielectric layer surrounds a third portion of the nanowires of the first and second vertical nanowire field effect transistors; and

forming a metal layer over the second dielectric layer, wherein the metal layer is in contact with drain silicides of the first and second vertical nanowire field effect transistors and electrically connects the drain region and the second drain region through the metal layer.

13. The method for forming a nanowire field effect transistor device of claim 1, wherein the second material of the drain silicide is disposed on top of the nanowire.

14. The method of claim 1, wherein the first material of the source silicide is configured to withstand a higher thermal budget.

15. A method for forming a plurality of nanowire field effect transistors, the method comprising:

forming a well of a first conductivity type in a semiconductor substrate;

forming a plurality of nanowires having i) a first end and ii) a second end opposite the first end, each of the nanowires extending perpendicularly from the well at the first end;

disposing a hard mask over the plurality of nanowires, wherein the hard mask is adjacent to the second ends of the nanowires;

performing a doping implant to form source and drain regions of the plurality of nanowire field effect transistors, wherein the drain region is disposed at a second end of the nanowire and the source region comprises a portion of the well doped to a second conductivity type as a result of the doping implant, the source region further comprising a protrusion disposed at the first end;

forming a spacer layer on sidewalls of the nanowire;

forming a source silicide over a portion of the well including the source region, wherein the hard mask prevents the source silicide from forming on the drain region;

removing the spacer from all nanowires to expose sidewalls of the nanowires and form a space between the protrusion and the source silicide;

forming a gate stack and one or more dielectric layers over the well, wherein the gate stack and the one or more dielectric layers surround the plurality of nanowires; and

a drain silicide is formed over the drain region.

16. The method for forming a plurality of nanowire field effect transistors of claim 15, wherein the drain silicide comprises a first material different from a second material of which the source silicide comprises.

17. The method for forming a plurality of nanowire field effect transistors of claim 15, further comprising:

forming the one or more dielectric layers, wherein the drain silicide is exposed at a top surface of the one or more dielectric layers; and

forming a metal layer over the one or more dielectric layers, wherein the metal layer is in contact with the exposed drain silicide and electrically connects drain regions of the plurality of nanowire field effect transistors through the metal layer.

18. The method for forming a plurality of nanowire field effect transistors of claim 15, further comprising:

forming a drain silicide over the drain region, the forming comprising:

forming a metal layer over the gate stack and the one or more dielectric layers, wherein,

the metal layer is also formed over the drain region;

depositing amorphous silicon or amorphous germanium over the metal layer; and

and annealing the metal layer and the amorphous silicon or the amorphous germanium to form the drain silicide.

Technical Field

The described technology relates generally to nanowire-based devices and, more particularly, to nanowire-based Field Effect Transistors (FETs) and techniques for their fabrication.

Background

Full Gate All Around (GAA) nanowire channel Field Effect Transistors (FETs) enable component scaling beyond current planar Complementary Metal Oxide Semiconductor (CMOS) technologies. Nanowire channel FETs are also of interest because of their electrostatic properties, which may be superior to those of conventional FET devices. Fabrication of the nanowire channel FET may include creating a batch of nanowires and placing them in desired locations (e.g., a bottom-up approach) or may include various lithographic patterning approaches (e.g., a top-down approach).

Disclosure of Invention

The invention relates to nanowire Field Effect Transistor (FET) devices and methods of forming nanowire FET devices. In a method for forming a nanowire FET device, a nanowire FET is formed that includes a source region and a drain region. The nanowire FET further comprises a nanowire connecting the source region and the drain region. A source silicide is formed on the source region and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material that the drain silicide comprises.

In another example, in a method for forming a nanowire FET device, a well of a first conductivity type is formed in a semiconductor substrate. Forming a plurality of nanowires, wherein the nanowires have: i) a first end, and ii) a second end opposite the first end. Each nanowire extends vertically from the well at the first end. A hard mask is provided over the plurality of nanowires, wherein the hard mask is adjacent to the second ends of the nanowires. A doping implant is performed to form source and drain regions of the plurality of nanowire FETs. The drain region is disposed at the second end of the nanowire, and the source region comprises a portion of a well that is doped to the second conductivity type as a result of the doping implant. A source silicide is formed over a portion of the well including the source region, wherein the hard mask prevents the first silicide from forming on the drain region. A gate stack and one or more dielectric layers are formed over the well, wherein the gate stack and the one or more dielectric layers surround the plurality of nanowires. A drain silicide is formed over the drain region, wherein the drain silicide is comprised of a first material that is different from a second material comprised by the source silicide.

In yet another example, a nanowire FET device includes a source region and a drain region. The nanowire FET device further comprises a nanowire formed in the semiconductor material, wherein the nanowire comprises a channel connecting the source region and the drain region. The nanowire FET further comprises a source silicide formed on the source region and a drain silicide formed on the drain region. The source silicide is comprised of a first material that is different from a second material that the drain silicide comprises.

To address the deficiencies of the prior art, according to one aspect of the present invention, there is provided a method for forming a nanowire Field Effect Transistor (FET) device, the method comprising: forming a nanowire FET comprising a source region and a drain region, wherein the nanowire FET further comprises a nanowire connecting the source region and the drain region; forming a source silicide on the source region; and forming a drain silicide on the drain region, wherein the source silicide comprises a first material different from a second material that the drain silicide comprises.

The method further comprises the following steps: forming the source silicide in a first time period; forming a gate stack after the first time period, wherein the gate stack surrounds a portion of the nanowire and forms the gate stack within a second time period; and forming the drain silicide after the second time period, wherein a higher thermal budget is applied to the source silicide than to the drain silicide.

In the method, the first material is MoSi₂、WSi₂、TiSi₂、TaSi₂Or NiCoSi₂。

In the method, the second material is NiSi₂Or PtSi₂。

The method further comprises the following steps: masking the drain region; and forming the source silicide on the source region, wherein the masking prevents the source silicide from forming on the drain region.

The method further comprises the following steps: masking the source region; and forming the drain silicide on the drain region, wherein the masking prevents the drain silicide from forming on the source region.

In the method, the nanowire FET is a first vertical nanowire FET, the method further comprising: forming a well of a first conductivity type in a semiconductor substrate; forming the nanowire with: i) a first end, and ii) a second end opposite the first end, the nanowire extending perpendicularly from the well at the first end; masking a second end of the nanowire; and forming the source silicide, wherein the masking prevents the source silicide from forming at the second end of the nanowire and the drain region is adjacent the second end of the nanowire.

The method further comprises the following steps: a nitride hard mask is used to mask the second end of the nanowire.

The method further comprises the following steps: forming the well, wherein the first conductivity type of the well is P-type; performing a doping implant to form source and drain regions of the first vertical nanowire FET, the doping implant causing the source and drain regions to have an N-type conductivity type, wherein the doping implant: forming the drain region at the second end of the nanowire, a first portion of the source region at the first end of the nanowire, and a second portion of the source region in the well; forming the source silicide on the second portion of the source region, wherein the source silicide is not formed on the first portion of the source region; and forming the drain silicide on the drain region, wherein the drain silicide is disposed on top of the nanowire at the second end and has a geometry that is different from a geometry of the source silicide.

The method further comprises the following steps: forming a gate stack, wherein the gate stack surrounds a portion of the nanowire; and forming a dielectric layer disposed above or below the gate stack, wherein the gate stack or the dielectric layer prevents the drain silicide from forming on the source region.

The method further comprises the following steps: forming a second vertical nanowire FET, wherein the second vertical nanowire FET comprises a second source region, a second drain region, a second nanowire connecting the second source region and the second drain region, a second source silicide, and a second drain silicide; forming a gate stack, wherein the gate stack surrounds a first portion of the nanowires of the first vertical nanowire FET and the second vertical nanowire FET; forming a first dielectric layer disposed below the gate stack, wherein the first dielectric layer surrounds a second portion of the nanowires of the first vertical nanowire FET and the second vertical nanowire FET; forming a second dielectric layer disposed over the gate stack, wherein the second dielectric layer surrounds a third portion of the nanowires of the first and second vertical nanowire FETs; and forming a metal layer over the second dielectric layer, wherein the metal layer is in contact with drain silicides of the first and second vertical nanowire FETs and electrically connects the drain region and the second drain region through the metal layer.

In the method, the second material of the drain silicide is disposed on top of the nanowire.

In the method, the first material of the source silicide is configured to withstand a higher thermal budget.

According to another aspect of the present invention, there is provided a method for forming a plurality of nanowire Field Effect Transistors (FETs), the method comprising: forming a well of a first conductivity type in a semiconductor substrate; forming a plurality of nanowires having i) a first end and ii) a second end opposite the first end, each of the nanowires extending perpendicularly from the well at the first end; disposing a hard mask over the plurality of nanowires, wherein the hard mask is adjacent to the second ends of the nanowires; performing a doping implant to form source and drain regions of the plurality of nanowire FETs, wherein the drain region is disposed at a second end of the nanowire and the source region comprises a portion of the well doped to a second conductivity type as a result of the doping implant; forming a source silicide over a portion of the well including the source region, wherein the hard mask prevents the source silicide from forming on the drain region; forming a gate stack and one or more dielectric layers over the well, wherein the gate stack and the one or more dielectric layers surround the plurality of nanowires; and forming a drain silicide over the drain region, wherein the drain silicide comprises a first material different from a second material that the source silicide comprises.

The method further comprises the following steps: forming the one or more dielectric layers, wherein the drain silicide is exposed at a top surface of the one or more dielectric layers; and forming a metal layer over the one or more dielectric layers, wherein the metal layer is in contact with the exposed drain silicide and electrically connects drain regions of the plurality of nanowire FETs through the metal layer.

The method further comprises the following steps: forming a drain silicide over the drain region, the forming comprising: forming a metal layer over the gate stack and the one or more dielectric layers, wherein the metal layer is also formed over the drain region; depositing amorphous silicon or amorphous germanium over the metal layer; and annealing the metal layer and the amorphous silicon or the amorphous germanium to form the drain silicide.

According to still another aspect of the present invention, there is provided a nanowire Field Effect Transistor (FET) device, including: a source region; a drain region; a nanowire formed in a semiconductor material, the nanowire comprising a channel connecting the source region and the drain region; a source silicide formed on the source region; and a drain silicide formed on the drain region, wherein the source silicide comprises a first material different from a second material of the drain silicide.

The nanowire FET device further comprises: a gate stack surrounding a portion of the nanowire, wherein the source silicide is formed within a first time period, the gate stack is formed after the first time period and within a second time period, the drain silicide is formed after the second time period, a higher thermal budget is imposed on the source silicide than the drain silicide, and the first material of the source silicide is configured to withstand the higher thermal budget.

In the nanowire FET device, the first material is MoSi₂、WSi₂、TiSi₂、TaSi₂Or NiCoSi₂And the second material is NiSi₂Or PtSi₂。

The nanowire FET device further comprises: a well of a first conductivity type formed in a semiconductor substrate, wherein the nanowire includes a first end at which the nanowire vertically extends from the well and a second end opposite the first end, the drain region is formed at the second end of the nanowire, and the source region includes: i) a first portion located at a first end of the nanowire and ii) a second portion located in the well.

In the nanowire FET device, the source silicide is formed on the second portion of the source region and not on the first portion of the source region, the drain silicide is formed on the drain region and disposed on top of the nanowire at the second end, a geometry of the drain silicide is different from a geometry of the source silicide, and a second material of the drain silicide is disposed on top of the nanowire.

Drawings

Fig. 1A and 1B illustrate a vertical nanowire Field Effect Transistor (FET) having a source silicide and a drain silicide, wherein the source silicide and the drain silicide are composed of different materials.

Fig. 1C shows a plurality of vertical nanowire FETs, each of which uses two silicide materials.

Figure 2A shows a nanowire extending vertically from a well formed in a substrate.

Figure 2B shows a hard mask formed substantially on top of the nanowire.

Fig. 2C illustrates a vertical doping implantation and diffusion process for forming source and drain regions of a nanowire FET.

Fig. 2D illustrates a tilted doping implant for forming a channel along the nanowire, wherein the channel electrically connects the source and drain regions.

Figure 2E shows spacer material formed along the nanowires.

Fig. 2F illustrates the formation of a source silicide substantially over a portion of the source region.

Fig. 2G shows the structure after removal of the spacer material.

Figure 2H shows a first interlayer dielectric (ILD) layer and a gate stack surrounding the nanowire.

Figure 2I shows a second ILD layer formed substantially over the gate stack.

Fig. 2J illustrates the removal of the hard mask from the structure.

Figure 2K illustrates depositing a second metal silicide over the structure, wherein the second metal silicide is formed substantially over the drain region and the second ILD layer.

Fig. 2L shows the drain silicide formed substantially over the drain region.

Fig. 3 illustrates a plurality of nanowire FETs, wherein the nanowire FETs have a drain silicide material that is different from the source silicide material, and a metal layer is formed substantially over the structure to electrically connect the drain regions of the nanowire FETs.

Fig. 4A illustrates depositing a drain metal silicide substantially over the plurality of nanowire FETs, wherein the drain metal silicide is formed substantially over the drain region and the second ILD layer of the structure.

Fig. 4B illustrates the deposition and patterning of an amorphous semiconductor layer, wherein the amorphous semiconductor layer is deposited substantially over the drain metal silicide.

Figure 4C shows the drain silicide formed substantially over the drain region of the nanowire and in the region with the amorphous semiconductor layer.

Fig. 5 is a flow chart illustrating an exemplary method for forming a nanowire Field Effect Transistor (FET) device.

Detailed Description

Fig. 1A and 1B illustrate a vertical nanowire Field Effect Transistor (FET) having a source silicide 108 and a drain silicide 114, where the source silicide 108 and the drain silicide 114 are composed of different materials. As shown in fig. 1A and 1B, the nanowire FET may include a source region 106, a drain region 112, and a nanowire channel 110 connecting the source region 106 and the drain region 112. In other types, the nanowire channel 110 may comprise a silicon nanowire. The nanowire FET may be fabricated substantially above the substrate 102 and may extend in a substantially vertical manner from a well 104 formed in the substrate 102. The substrate 102 may be a bulk P-type silicon substrate and the well 104 formed in the substrate may be a P-type well (e.g., a well with a higher P-type dopant than the substrate 102). The well 104 may be formed by an ion implantation process.

Fig. 1A may show a cross-sectional view of an exemplary intermediate stage in a nanowire FET fabrication process, and fig. 1B may show a perspective view of the exemplary intermediate stage. As shown in fig. 1A and 1B, the source region 106 of the nanowire FET may include: i) a first portion located at a first end of the nanowire channel 110, and ii) a second portion located within the well 104. The first and second portions of the source region are further illustrated in fig. 2C, described below, which fig. 2C marks the first portion of the source region 210 located at the first end of the nanowire 206, and the second portion of the source region 210 located within the well 204. A drain region 112 may be formed at a second end of nanowire channel 110 opposite the first end. In a complete state of fabrication, a gate (not shown in fig. 1A and 1B) can surround (e.g., wrap around) nanowire channel 110, where the gate can be used to regulate current flowing through nanowire channel 110 between source region 106 and drain region 112.

As shown in fig. 1A and 1B, the source silicide 108 may be formed substantially over the source region 106. In particular, the source silicide 108 may be formed substantially over the second portion of the source region 106 (i.e., the portion of the source region 106 formed within the well 104) and may not be formed over the first portion of the source region 106 (i.e., the portion of the source region 106 formed at the first end of the nanowire channel 110). A drain silicide 114 may be formed on the drain region 112 such that the drain silicide 114 may be disposed substantially on top of the nanowire. The source silicide 108 and the drain silicide 114 may be of different geometries, where the source silicide 108 may include portions similar to a planar film (e.g., as shown in fig. 1B, the source silicide 108 is shown as a planar film with openings for patterning of the nanowires) and the drain silicide 114 may include only a small region disposed substantially on top of the nanowires. In selecting the material of the source silicide 108 and the drain silicide 114 and other parameters (e.g., thickness, fabrication process, etc.), it may be considered to change the geometry of the silicide 108, the silicide 114.

In addition to being of different geometries, the source silicide 108 and the drain silicide 114 may undergo different processes. For example, as described above, a gate stack (not shown in fig. 1A and 1B) may surround the nanowire channel 110. During fabrication of the structure, the source silicide 108 may be formed during a first time period, the gate stack may be formed during a second time period after the first time period, and the drain silicide 114 may be formed during a third time period after the second time period. Due to this order used in the fabrication process, the source silicide 108 may be exposed to a higher thermal budget (thermal budget) than the drain silicide 114. In selecting the materials and other parameters of the source silicide 108 and the drain silicide 114, it may be considered to impose different thermal budgets on the silicide 108, the silicide 114.

The source silicide 108 may be comprised of a first material and the drain silicide 114 may be comprised of a second material different from the first material. In contrast, in conventional FET fabrication processes, the silicide located on the source and drain of the transistor may be of the same type (i.e., the silicide may have the same chemical composition and may be made of the same material). As described above, in a vertical nanowire transistor (e.g., the vertical nanowire transistor shown in fig. 1A and 1B), the source silicide 108 may be formed prior to forming the gate stack, and the drain silicide 114 may be formed after forming the gate stack. Thus, the source silicide 108 and the drain silicide 114 may be exposed to different thermal budgets. Additionally, as described above, in a vertical nanowire transistor, the geometry (e.g., size and shape) of the source silicide 108 may be different from the geometry of the drain silicide 114. Due to these differences in process and geometry, the optimization requirements for the source silicide 108 and the drain silicide 114 may differ.

By using two different materials for the source suicide 108, the drain suicide 114, device performance optimization may be implemented by taking into account the different thermal budgets and geometries of the suicide 108 and the suicide 114. Such performance optimization is not possible or difficult to achieve if a single silicide material is used for the source silicide 108, the drain silicide 114. The formation and stability of a given silicide may depend on the thermal budget (e.g., during and after silicide formation) and the geometry of the region in which the silicide is formed. The use of two different materials for silicide 108, silicide 114 may increase process flexibility and enable the aforementioned optimization of device performance.

In the example of fig. 1, the source suicide 108 may be optimized for a higher thermal budget. The material of the source silicide 108 that may be configured to withstand the higher thermal budget applied may include MoSi₂、WSi₂、TiSi₂、TaSi₂And NiCoSi₂. The drain silicide 114 may be optimized to be on top of the nanowire. Drain silicide 1 that may be adapted to be located on top of the nanowire14 may include NiSi₂And PtSi₂. It is emphasized that although the example of fig. 1 is described in terms of the source region 106 disposed at the bottom of the nanowire channel 110 and the drain region 108 disposed at the top of the nanowire channel 110, in other examples, the source and drain regions may be switched (e.g., such that the source region is disposed at the top of the nanowire channel 110 and the drain region is disposed at the bottom of the nanowire channel 110). In these other examples, the source silicide material may be optimized to be on top of the nanowire, and the drain silicide material may be optimized for a higher thermal budget.

The positions of the source and drain regions depend on the direction of current flow and the bias voltage applied to the transistor, so that the positions of the source and drain can be switched by changing the bias voltage applied to the transistor. Thus, in view of the fact that in some instances the drain region may be located at the bottom of the transistor, reference to "source silicide" in this disclosure should be more generally understood to refer to "bottom silicide". Similarly, a reference to "drain silicide" in this disclosure should be more generally understood as "top silicide," given that in some instances the source silicide may be located on top of the transistor.

Fig. 1C shows a plurality of vertical nanowire FETs 120, where each FET 120 uses two different silicide materials (i.e., a first material for the source silicide 108 and a second material for the drain silicide 114, where the second material is different from the first material). As with the example in fig. 1A and 1B, nanowire FET 120 of fig. 1C may be fabricated substantially above substrate 102, where the substrate may include well region 104 from which the nanowire extends. In a complete state of fabrication, a gate (not shown in fig. 1C) may surround (e.g., wrap around) the nanowire, where the gate may be used to regulate current flow between the source region 106 and the drain region 112. Fig. 1C may illustrate that the plurality of FETs 120 are formed and configured substantially above the substrate 102 in an array pattern (as shown in fig. 1C) or in various other patterns.

Fig. 2A to 2L are diagrams illustrating an exemplary method of fabricating a nanowire FET with different materials of a source silicide and a drain silicide. In particular, fig. 2A to 2L may show cross-sectional views at exemplary intermediate stages of fabricating a nanowire FET. Figure 2A shows nanowires 206 extending vertically from a well 204 formed in a substrate 202. For example, the substrate 202 may be a bulk silicon substrate, and the well 204 may have the same first conductivity type as the substrate 202. In the example of fig. 2A, the substrate 202 may be a P-type silicon substrate and the well 204 may be a P-type well. In other examples, the substrate 202 may be a bulk N-type silicon substrate and the well 204 may be an N-type well. Various other substrate/well structures may be used (e.g., a structure in which the well 204 has a different conductivity type than the substrate 202). In general, the substrate 202 may be any type of semiconductor substrate on which the well 204 and the nanowire 206 may be formed. In other types, nanowires 206 can comprise silicon nanowires. In one example, nanowires 206 can be formed by masking substrate 202 and/or well 204 and performing an etching process to fabricate nanowires 206.

Figure 2B shows a hard mask 208 formed substantially on top of the nanowires 206. For example, the hard mask 208 may be a nitride hard mask, an oxide hard mask, or various other types of hard masks. As described in further detail below in connection with fig. 2F, the hard mask 208 may be used to prevent a source silicide (e.g., source silicide 218 in the example of fig. 2F) from forming on the drain region of the nanowire. Accordingly, the hard mask 208 may comprise any hard mask material that achieves this end.

Fig. 2C illustrates a vertical dopant implantation and diffusion process (indicated by arrows 209) for forming the source region 210 and the drain region 212 of the nanowire FET. The doping implantation and diffusion process may result in the source region 210 and the drain region 212 having a different conductivity type than the substrate 202 and/or the well 204. Thus, in the example of fig. 2C, where both the substrate 202 and the well 204 in fig. 2C have a first conductivity type that is P-type, the doping implantation and diffusion process may result in the source region 210 and the drain region 212 having a second conductivity type that is N-type. This is illustrated in fig. 2C, where the source region 210, the drain region 212 are shown as being of conductivity type "N + +" in fig. 2C.

The nanowire 206 may have a first end (i.e., proximate to the substrate 202) and a second end opposite the first end (i.e., located at the top of the nanowire 206 and adjacent to the hard mask 208), and the nanowire 206 may extend vertically from the well 204 at the first end. A vertical doping implantation and diffusion process may form a drain region 212 at the second end of nanowire 206. The vertical dopant implantation and diffusion process may also form the source region 210, wherein the source region 210 may include: i) a first portion located at a first end of the nanowire 206, and ii) a second portion located in the well 204. As shown in fig. 2C, forming a second portion of the source region 210 in the well 204 may cause the portion of the well 204 to change from a P-type conductivity type to an N + + conductivity type. The vertical doping implant of fig. 2C may be referred to as a shallow implant.

Fig. 2D illustrates that the angled doping implant used forms a channel 214 along the nanowire, where the channel 214 may electrically connect the source region 210 and the drain region 212. A doping implant (indicated by arrows 213) may be performed at a tilted angle to form a doped channel 214 (e.g., N + doped, N doped, or P doped) along the nanowire. A diffusion process may be used in conjunction with an angled dopant implant to form the N + channel 214.

Fig. 2E shows spacer material 216 formed along the nanowires. For example, the spacer material 216 may be a nitride spacer material, an oxide spacer material, or other types of spacer materials. Although the cross-sectional view of fig. 2E may show the spacer material 216 disposed on only two sides of the nanowire, it should be understood that the perspective view of the structure may show the spacer material 216 as surrounding the perimeter of the nanowire.

Fig. 2F illustrates the formation of a source silicide 218 substantially over a portion of the source region 210. In forming the source silicide 218, a first metal silicide may be deposited substantially over the structure, and the structure may then be annealed to react with the first metal silicide. For example, the first metal silicide of source silicide 218 may be NiCo, Ti, or other metal. In particular, the first metal used to form the source silicide 218 may be a metal configured to withstand a higher thermal budget. As described above with reference to fig. 1A and 1B, the source silicide 218 may be formed prior to forming a gate stack (e.g., gate stack 222 as shown in fig. 2H) and prior to forming a drain silicide (e.g., drain silicide 228 as shown in fig. 2L). The additional process to which the source silicide 218 is subjected may result in a higher thermal budget to be applied to the source silicide 21 than the drain silicide. Thus, in determining the first metal silicide of source silicide 218, a metal may be selected that is configured to withstand a higher thermal budget and maintain stability.

As described above, the first metal silicide may be deposited substantially over the structure, and the structure may then be annealed to react the first metal silicide. The reacted metal may form a source silicide 218 configured to withstand a higher thermal budget, wherein the source silicide 218 may include MoSi₂、WSi₂、TiSi₂、TaSi₂Or NiCoSi₂. Unreacted metal may be stripped from the structure. As shown in fig. 2F, after reacting the first metal suicide and stripping the unreacted metal, a source suicide 218 may be formed only over the second portion of the source region 210 that has been formed in the well 204. The hard mask 208 may be used to prevent the source silicide 218 from forming on the drain region 212 of the nanowire (e.g., the metal deposited on the hard mask 208 or other unreacted surface may be unreacted metal stripped from the structure).

Fig. 2G shows the structure after removal of spacer material 216. Removing spacer material 216 may result in nanowires disposed in the openings of source silicide 218. For example, although the source suicide 218 may be in contact with the source region 210 of the FET, the nanowire itself may not be in physical contact with the source suicide 218 after the spacer material 216 is removed. The opening in the source silicide 218 is shown in the example of fig. 1B, where a circular opening in the source silicide 108 is shown surrounding the nanowire.

Figure 2H shows a first interlayer dielectric (ILD) layer 220 and a gate stack 222 substantially surrounding the nanowire. A first ILD layer 220 may be deposited substantially over the source silicide 218 and planarized by a Chemical Mechanical Planarization (CMP) process. The first ILD layer 220 may be an oxide layer or other suitable interlayer dielectric material. After the CMP process, the gate stack 222 may be formed substantially over the ILD layer 220. Gate stack 222 may comprise oxide, high-k dielectric, TiN, TaN, TaC, polysilicon, tungsten, or aluminum, among other materials, for example. Although the cross-sectional view of fig. 2H shows the first ILD layer 220 and gate stack 222 as only being disposed on both sides of the nanowire, it is understood that the perspective view of the structure may show the ILD layer 220 and gate stack 222 as surrounding the perimeter of the nanowire. Since the gate stack 222 can surround (e.g., wrap) the nanowire in this manner, the nanowire FET of fig. 2A-2L can be referred to as a Gate All Around (GAA) nanowire FET.

Fig. 2I shows a second ILD layer 224 formed substantially over gate stack 222. The second ILD layer 224 may be planarized by a CMP process and may be an oxide layer or other suitable interlayer dielectric material. Although the example of fig. 2I depicts the second ILD layer 224 as being deposited to a thickness such that the second ILD layer 224 is substantially flush with the top surface of the hard mask 208, in other examples, the second ILD layer 224 may be thicker or thinner. In one example, the second ILD layer 224 may have a thickness such that the second ILD layer 224 is substantially planar with the top surface of the drain region 212. In another example, the second ILD layer 224 may have a thickness such that the hard mask 208 is recessed a distance into the ILD layer 224.

Fig. 2J illustrates the removal of the hard mask 208 from the structure. For example, hard mask 208 may be removed by conventional dry etching techniques.

Fig. 2K illustrates depositing a second metal silicide 226 over the structure, wherein the second metal silicide 226 is formed substantially over the drain region 212 and the second ILD layer 224. For example, the second metal silicide 226 of the drain silicide may be Ni or other metal. The second metal silicide 226 used to form the drain silicide may be a metal configured to be placed substantially on top of the nanowire.

Fig. 2L shows a drain silicide 228 formed substantially over the drain region 212. In forming the drain silicide 228, a second metal silicide 226 may be deposited substantially over the structure (e.g., as shown in fig. 2K), and the structure may then be annealed to react the second metal silicide 226. The reacted metal may beForming a drain silicide 228 adapted to be disposed substantially on top of the nanowire, wherein the drain silicide 228 may comprise NiSi, among other materials₂Or PtSi₂. As shown in fig. 2L, unreacted metal may be stripped from the structure such that the drain silicide 228 is formed only over the nanowires. The ILD layer 220, ILD layer 224, and gate stack 222 may prevent the formation of a drain silicide 228 on portions of the source region 210.

In the example of fig. 2A-2L, the material of the source silicide 218 may be different from the material of the drain silicide 228. By using different materials for the silicide 218, 228, the properties of the silicide 218, 228 may be optimized. For example, as described above, the source silicide 218 (e.g., comprising MoSi)₂、WSi₂、TiSi₂、TaSi₂Or NiCoSi₂) May be optimized for a higher thermal budget, and the drain silicide 228 (e.g., including NiSi)₂Or PtSi₂) May be optimized to be on top of the nanowire.

Fig. 3 illustrates a plurality of nanowire FETs, wherein the nanowire FETs have a drain silicide material that is different from the source silicide material, and a metal layer 330 is formed substantially over the structure to electrically connect the drain regions 312 of the nanowire FETs. The regions and layers of the nanowire FET may be similar to those described above with reference to fig. 2A-2L to include the substrate 302, the well region 304, the source region 310, the drain region 312, the nanowire channel 314, the source silicide 318, the first ILD layer 320, the gate stack 322, the second ILD layer 324, and the drain silicide 328. Prior to forming the metal layer 330 substantially over the structure, the structure may be in a suitable state for performing back end of line (BEOL) processes (e.g., depositing additional ILD layers, etching vias, patterning metal layers, etc.).

Metal layer 330 may be deposited substantially over the structure to cause electrical contact between metal layer 330 and drain silicide 328. In the example of fig. 3, the metal used for metal layer 330 may be different from the metal used to form drain silicide 328. Metal layer 330 may be a first metal layer (e.g., copper or aluminum, etc.) of a BEOL process. Since the metal layer 330 may be in contact with the drain silicide 328, the various drain regions 312 of the FET may be electrically connected.

Fig. 4A illustrates depositing a drain metal silicide 426 substantially over the plurality of nanowire FETs, wherein the drain silicide 426 may be formed substantially over the drain region 412 and the second ILD layer 424 of the structure. Fig. 4A may be similar to fig. 2K (i.e., fig. 2K may show a single nanowire FET after deposition of drain metal silicide 226, while fig. 4A may show multiple nanowire FETs after deposition of drain metal silicide 426). For example, the drain metal silicide 426 may be nickel, among other materials. The regions and layers of the plurality of nanowire FETs may be similar to those described above with reference to fig. 2A-2L to include the substrate 402, the well region 404, the source region 410, the drain region 412, the nanowire channel 414, the source silicide 418, the first ILD layer 420, the gate stack 422, and the second ILD layer 424.

Fig. 4B illustrates the deposition and patterning of an amorphous semiconductor layer 434, wherein the amorphous semiconductor layer 434 may be deposited substantially over the drain metal silicide 426. For example, the amorphous semiconductor layer 434 may include amorphous silicon or amorphous SiGe. As shown in fig. 4B, the amorphous semiconductor layer 434 may be patterned such that the layer 434 does not extend to all portions of the structure. Photolithography and etching may be used to pattern the amorphous semiconductor layer 434, and the structure may then be annealed to form a drain silicide (e.g., drain silicide 436 as described below with reference to fig. 4C).

Figure 4C shows a drain silicide 436 formed substantially over the drain region 412 of the nanowire and in the region with the amorphous semiconductor layer 434. The drain silicide 436 may be formed by annealing the structure and then removing the unreacted metal. As shown in fig. 4C, the anneal may cause a drain silicide 436 to form substantially on top of the nanowire (e.g., by reaction between the drain metal silicide 426 and the silicon in the nanowire) and in the region with the amorphous semiconductor layer 434. A drain silicide 436 (which may be formed in the region with the amorphous semiconductor layer 434) may electrically connect the drain regions 412 of the nanowire FETs. As in the previous example, the drain silicide 436 may comprise a different material than the source silicide 418.

Fig. 5 is a flow diagram 500 illustrating an exemplary method for forming a nanowire Field Effect Transistor (FET) device. In step 502, a nanowire FET comprising a source region and a drain region may be formed. In step 504, nanowires may be formed connecting the source and drain regions. In step 506, a source silicide may be formed on the source region. In step 508, a drain silicide may be formed on the drain region, wherein the source silicide may be composed of a first material that is different from a second material comprised by the drain silicide.

This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples. It should be understood that the meaning of "a", "an", and "the" as used in this specification and throughout the claims that follow, includes plural references unless the context clearly dictates otherwise. Further, as used in this specification and throughout the claims that follow, unless the text expressly indicates otherwise, the meaning of "in …" includes "in …" and "on …". In addition, as used in this specification and throughout the claims that follow, the meaning of "each" does not require "each and every" unless the text clearly dictates otherwise. Finally, as used in this specification and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of "and" or "includes both conjunctive and disjunctive and may be used interchangeably; the phrase "other than …" may be used in cases where only a separate meaning is applicable.