阅读说明：本技术 一种混合沟道化合物半导体器件 (Mixed channel compound semiconductor device ) 是由 不公告发明人 于 2018-06-20 设计创作，主要内容包括：本发明专利公开了一种混合沟道化合物半导体器件,其中器件的凹槽状栅电极通过控制垂直和横向两种电子沟道,实现常闭型化合物半导体器件。本器件避免了在功率模块中使用常开型化合物半导体晶体管带来的高压短路风险,能够安全的充分发挥化合物半导体晶体管在功率电子中的高效率、耐高压的优势。(The invention discloses a mixed channel compound semiconductor device, wherein a groove-shaped gate electrode of the device realizes a normally-closed compound semiconductor device by controlling two electronic channels of a vertical channel and a transverse channel. The device avoids the risk of high-voltage short circuit caused by using a normally-open compound semiconductor transistor in a power module, and can safely and fully play the advantages of high efficiency and high voltage resistance of the compound semiconductor transistor in power electronics.)

1. A mixed channel compound field effect transistor comprises a substrate, and a buffer layer, a first channel layer, a first barrier layer, a second channel layer and a second barrier layer which are sequentially stacked on the substrate;

a groove-shaped gate deposition area penetrating to a position not exceeding the lower surface of the first barrier layer is arranged on the upper surface of the second barrier layer, a source deposition area penetrating to a position not exceeding the lower surface of the second barrier layer and a drain deposition area penetrating to a position not exceeding the lower surface of the first barrier layer are respectively arranged on two sides of the gate deposition area;

the mixed channel compound field effect transistor also comprises a gate dielectric layer, a gate layer, a source layer and a drain layer, wherein the gate dielectric layer covers the bottom surface and the side surface of the gate deposition area and extends outwards to the upper part of the second barrier layer;

the grid layer extends from the upper part of the grid dielectric layer on one side of the grid deposition area to the upper part of the grid dielectric layer on the other side along the grid dielectric layer;

the source layer and the drain layer extend from the bottom of the source deposition area and the bottom of the drain deposition area to the upper side of the second barrier layer along the corresponding side surfaces respectively;

the gate layer can control the current in the horizontal direction and the vertical direction of the second channel layer through the gate medium layer by an electric field.

2. The hybrid channel compound field effect transistor of claim 1 having more than one recessed gate and source deposition regions.

3. The hybrid channel compound field effect transistor of claim 1, wherein the source deposition region and the surrounding semiconductor material are separated by the gate deposition region into a two-dimensional array.

4. A two-dimensional array according to claim 3, wherein the horizontal cross-section of the array elements includes, but is not limited to, circular, square, and hexagonal.

5. The hybrid channel compound field effect transistor of claim 1, wherein the first barrier layer has a thickness of 2 nanometers to 100 nanometers.

6. The hybrid channel compound field effect transistor of claim 1, wherein the first barrier layer comprises Al_xGa_1-xN materials, where x is between 0 and 1, including 0 and 1 themselves.

7. The hybrid channel compound field effect transistor of claim 1, wherein the first channel layer comprises a GaN material.

8. The mixed channel compound field effect transistor of claim 1, wherein the material of the first channel layer comprises an impurity doping.

9. The hybrid channel compound field effect transistor of claim 1, wherein the second channel layer comprises a GaN material.

10. The mixed channel compound field effect transistor of claim 1, wherein the second channel layer has a thickness of 2 nanometers to 10 micrometers.

11. The mixed channel compound field effect transistor of claim 1, wherein the material of the second channel layer comprises an impurity doping.

12. The hybrid channel compound field effect transistor of claim 1, wherein the second barrier layer has a thickness of 2 nanometers to 100 nanometers.

13. The hybrid channel compound field effect transistor of claim 1, wherein the second barrier layer comprises an AlxGa1-xN material, where x is between 0 and 1, including 0 and 1 itself.

14. The mixed channel compound fet of claim 1 wherein the gate dielectric is but not limited to one or a combination of SiO2, SiN, Al2O3, AlN, HfO2 and Ga2O3 and has a thickness of 0.5 nm to 100 nm.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a mixed channel compound high-voltage device.

Background

The power electronic switch module is widely applied to power electronics and power supplies, and is a basic functional module in the current direct current/direct current and alternating current/direct current conversion.

Conventional solid-state power electronic switch modules are implemented using silicon materials. The performance of the silicon solar cell module approaches the improvement limit in terms of module efficiency, heat dissipation, speed and the like due to the constraint of the basic properties of silicon materials.

The use of compound semiconductor materials, such as gan, to construct power electronic switch modules has been a trend in the power electronics industry. This is because the compound semiconductor material has the characteristics of high withstand voltage, low resistance, and low capacitance, and has a performance improvement potential hundreds of times higher than that of silicon.

Compound semiconductor power electronic modules face a challenge not present in silicon material modules-normally-off compound semiconductor power transistors are difficult to obtain. Most compound semiconductor transistors are normally-on devices. The disadvantage of constructing a power module using only the normally-open type compound semiconductor device is that module safety is not secured.

Specifically, for a normally-on device, a negative voltage needs to be provided to the control terminal to ensure that the device is turned off. In the natural state, where the system is not yet powered on, the normally-on device is on. This results in that, in the case of a failure of the negative voltage control module, the normally-on device cannot block the high voltage, and a path from the high voltage to the ground is provided, which may cause a dangerous situation such as a system short circuit and burnout.

To solve this problem, one solution is to fabricate a normally-off compound semiconductor transistor. Compound semiconductor device companies are trying this approach to the utmost. For example, US patent specification US8193562B2 describes a structure for achieving a normally-off compound semiconductor power transistor using P-type gate technology.

Disclosure of Invention

Based on this, there is a need to provide an enhancement mode compound high voltage device that can effectively address the positive threshold voltage.

A mixed channel compound field effect transistor comprises a substrate, and a buffer layer, a first channel layer, a first barrier layer, a second channel layer and a second barrier layer which are sequentially stacked on the substrate;

a groove-shaped gate deposition area penetrating to a position not exceeding the lower surface of the first barrier layer is arranged on the upper surface of the second barrier layer, a source deposition area penetrating to a position not exceeding the lower surface of the second barrier layer and a drain deposition area penetrating to a position not exceeding the lower surface of the first barrier layer are respectively arranged on two sides of the gate deposition area;

the mixed channel compound field effect transistor also comprises a gate dielectric layer, a gate layer, a source layer and a drain layer, wherein the gate dielectric layer covers the bottom surface and the side surface of the gate deposition area and extends to the upper part of the second barrier layer from two sides;

the grid layer extends from the upper part of the grid dielectric layer on one side of the grid deposition area to the upper part of the grid dielectric layer on the other side along the grid dielectric layer;

the source electrode layer and the drain electrode layer extend from the bottom of the source electrode deposition area and the bottom of the drain electrode deposition area to the upper side of the barrier layer along the corresponding side faces respectively;

in one embodiment, more than one groove-shaped gate deposition area and source deposition area are arranged on one side of the source deposition area.

In one embodiment, the source deposition regions form a two-dimensional array, and the two-dimensional array is separated by groove-shaped gate deposition regions.

In one embodiment, the source deposition region and the surrounding semiconductor are separated by the recessed gate deposition region into a two-dimensional array with a horizontal cross-section of cells that is, but not limited to, circular, square, and hexagonal.

In one embodiment, the first barrier layer has a thickness of 2 nanometers to 100 nanometers.

In one embodiment, the first barrier layer comprises Al_xGa_1-xN materials, where x is between 0 and 1, including 0 and 1 themselves.

In one embodiment, the first channel layer includes a GaN material.

In one embodiment, the material of the first channel layer includes impurity doping.

In one embodiment, the second channel layer includes a GaN material.

In one embodiment, the second channel layer has a thickness of 2 nanometers to 10 micrometers.

In one embodiment, the material of the second channel layer includes impurity doping.

In one embodiment, the second barrier layer has a thickness of 2 nanometers to 100 nanometers.

In one embodiment, the second barrier layer comprises AlxGa1-xN material, where x is between 0 and 1, including 0 and 1 themselves.

In one embodiment, the gate dielectric is, but not limited to, one or a combination of SiO2, SiN, Al2O3, AlN, HfO2, and Ga2O3, and has a thickness of 0.5 nm to 100 nm.

Due to the implementation of the technical scheme, compared with the prior art, the invention has the following advantages: the compound device has the combination of a longitudinal channel and a transverse channel, and can achieve the effect that the total threshold voltage is positive by controlling the threshold voltages of the two channels. Specifically, a longitudinal channel is introduced by introducing a second channel layer and a groove-shaped gate deposition region, and introducing a path through which electrons flow in a vertical direction of the second channel layer; meanwhile, under the first barrier layer and the second barrier layer, horizontal two-dimensional electron gas is realized in the first channel layer and the second channel layer, respectively, due to a piezoelectric effect, thereby introducing a lateral channel. The threshold voltages of the two channels are controlled by different crystal orientations and surface states of the channel surface.

Drawings

Fig. 1 is a cross-sectional structural view of a mixed channel compound device.

Figure 2 is a cross-sectional view of a hybrid channel compound device having a repeating recessed gate deposition area.

Figure 3 is a top view of a mixed channel compound device with repeating recessed gate deposition areas.

Figure 4 is a top view of a mixed channel compound device with repeating recessed gate deposition areas. Wherein the drain electrode (8) is hexagonal in shape.

Figure 5 is a top view of a mixed channel compound device with repeating recessed gate deposition areas. Wherein the drain electrode (8) is circular in shape.