阅读说明：本技术 占空比校准装置及方法 (Duty ratio calibration device and method ) 是由 周常瑞 杨诗洋 王颀 于 2019-09-17 设计创作，主要内容包括：本发明实施例提供了一种占空比校准装置及方法。其中,所述占空比校准装置包括：占空比检测电路,用于基于时钟信号,生成第一信号和第二信号；所述第一信号承载了所述时钟信号中高电平部分的信息；所述第二信号承载了所述时钟信号中低电平部分的信息；边沿检测电路,用于检测所述第一信号中的第一个变化边沿以及所述第二信号中的第一个变化边沿,得到检测结果；控制电路,用于基于得到的检测结果,生成第一控制信号；占空比调节电路,用于根据所述第一控制信号对所述时钟信号进行校准。如此,能够对高速时钟信号的校准进行快速响应,以实现对高速时钟信号的快速校准。(The embodiment of the invention provides a duty ratio calibration device and method. Wherein the duty calibration device comprises: a duty ratio detection circuit for generating a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal; the edge detection circuit is used for detecting a first change edge in the first signal and a first change edge in the second signal to obtain a detection result; a control circuit for generating a first control signal based on the obtained detection result; and the duty ratio adjusting circuit is used for calibrating the clock signal according to the first control signal. Therefore, the calibration of the high-speed clock signal can be quickly responded, and the quick calibration of the high-speed clock signal is realized.)

1. A duty cycle calibration device, comprising:

a duty ratio detection circuit for generating a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

the edge detection circuit is used for detecting a first change edge in the first signal and a first change edge in the second signal to obtain a detection result;

a control circuit for generating a first control signal based on the obtained detection result;

and the duty ratio adjusting circuit is used for calibrating the clock signal according to the first control signal.

2. The apparatus of claim 1, wherein the edge detection circuit is specifically configured to: detecting a first time when a first changing edge appears in the first signal and a second time when the first changing edge appears in the second signal; obtaining the appearance time sequence relation of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance time based on the first time and the second time;

the control circuit is specifically configured to generate the first control signal based on the obtained precedence relationship between the occurrence times of the first change edge in the first signal and the first change edge in the second signal and the time interval of the occurrence times.

3. The apparatus of claim 1, wherein the edge detection circuit is further configured to: generating a first identification signal after detecting a first change edge in the first signal and a first change edge in the second signal;

the control circuit is further used for generating a second control signal according to the first identification signal;

the duty ratio calibration device further comprises a power switch circuit which is used for responding to the second control signal and closing the power supply of the duty ratio detection circuit.

4. The apparatus of claim 1, wherein the duty cycle detection circuit comprises:

a first duty detection sub-circuit for generating the first signal based on a high level in the clock signal;

a second duty cycle detection sub-circuit to generate the second signal based on a low level in the clock signal.

5. The apparatus of claim 3, wherein the duty cycle detection circuit comprises: the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit; wherein the content of the first and second substances,

the power switch circuit is used for responding to the second control signal and closing the power supply of the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit;

the first duty cycle detection sub-circuit is used for generating the first signal based on a high level in the clock signal;

the second duty detection sub-circuit is configured to generate the second signal based on a low level in the clock signal.

6. A method of duty cycle calibration, the method comprising:

a duty ratio detection circuit of the duty ratio calibration device generates a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

an edge detection circuit of the duty ratio calibration device detects a first change edge in the first signal and a first change edge in the second signal to obtain a detection result;

a control circuit of the duty ratio calibration device generates a first control signal based on the obtained detection result;

and a duty ratio adjusting circuit of the duty ratio calibrating device calibrates the clock signal according to the first control signal.

7. The method of claim 6, wherein the edge detection circuit detects a first changing edge in the first signal and a first changing edge in the second signal to obtain a detection result, comprising:

the edge detection circuit detects a first time when a first changing edge appears in the first signal and a second time when the first changing edge appears in the second signal; obtaining the appearance time sequence relation of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance time based on the first time and the second time;

the control circuit generates a first feedback signal based on the obtained detection result, and the control circuit comprises:

and the control circuit generates the first control signal based on the obtained precedence relationship between the appearance moments of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance moments.

8. The method of claim 6, further comprising:

the edge detection circuit generates a first identification signal after detecting a first change edge in the first signal and a first change edge in the second signal;

the control circuit generates a second control signal according to the first identification signal;

and the power switch circuit of the duty ratio calibration device responds to the second control signal to turn off the power supply of the duty ratio detection circuit.

9. The method of claim 6, wherein the duty cycle detection circuit comprises:

a first duty detection sub-circuit for generating the first signal based on a high level in the clock signal;

a second duty cycle detection sub-circuit to generate the second signal based on a low level in the clock signal.

10. The method of claim 8, wherein the duty cycle detection circuit comprises: the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit; wherein the content of the first and second substances,

the power switching circuit responds to the second control signal to turn off the power supply of the duty ratio detection circuit, and comprises:

the power supply switching circuit responds to the second control signal and turns off the power supply of the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit;

the first duty cycle detection sub-circuit is used for generating the first signal based on a high level in the clock signal;

the second duty detection sub-circuit is configured to generate the second signal based on a low level in the clock signal.

Technical Field

The present invention relates to signal processing technologies, and in particular, to a duty ratio calibration apparatus and method.

Background

Disclosure of Invention

In order to solve the related technical problems, embodiments of the present invention provide a duty ratio calibration apparatus and method, which can perform a fast response to a calibration of a high-speed clock signal to achieve a fast calibration of the high-speed clock signal.

An embodiment of the present invention provides a duty ratio calibration apparatus, including:

a duty ratio detection circuit for generating a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

the edge detection circuit is used for detecting a first change edge in the first signal and a first change edge in the second signal to obtain a detection result;

a control circuit for generating a first control signal based on the obtained detection result;

and the duty ratio adjusting circuit is used for calibrating the clock signal according to the first control signal.

In the foregoing solution, the edge detection circuit is specifically configured to: detecting a first time when a first changing edge appears in the first signal and a second time when the first changing edge appears in the second signal; obtaining the appearance time sequence relation of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance time based on the first time and the second time;

the control circuit is specifically configured to generate the first control signal based on the obtained precedence relationship between the occurrence times of the first change edge in the first signal and the first change edge in the second signal and the time interval of the occurrence times.

In the foregoing solution, the edge detection circuit is further configured to: generating a first identification signal after detecting a first change edge in the first signal and a first change edge in the second signal;

the control circuit is further used for generating a second control signal according to the first identification signal;

the duty ratio calibration device further comprises a power switch circuit which is used for responding to the second control signal and closing the power supply of the duty ratio detection circuit.

In the above aspect, the duty detection circuit includes:

a first duty detection sub-circuit for generating the first signal based on a high level in the clock signal;

a second duty cycle detection sub-circuit to generate the second signal based on a low level in the clock signal.

In the above aspect, the duty detection circuit includes: the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit; wherein the content of the first and second substances,

the power switch circuit is used for responding to the second control signal and closing the power supply of the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit;

the first duty cycle detection sub-circuit is used for generating the first signal based on a high level in the clock signal;

the second duty detection sub-circuit is configured to generate the second signal based on a low level in the clock signal.

The embodiment of the invention also provides a duty ratio calibration method, which comprises the following steps:

a duty ratio detection circuit of the duty ratio calibration device generates a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

an edge detection circuit of the duty ratio calibration device detects a first change edge in the first signal and a first change edge in the second signal to obtain a detection result;

a control circuit of the duty ratio calibration device generates a first control signal based on the obtained detection result;

and a duty ratio adjusting circuit of the duty ratio calibrating device calibrates the clock signal according to the first control signal.

In the above solution, the detecting a first variation edge in the first signal and a first variation edge in the second signal by the edge detecting circuit to obtain a detection result includes:

the edge detection circuit detects a first time when a first changing edge appears in the first signal and a second time when the first changing edge appears in the second signal; obtaining the appearance time sequence relation of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance time based on the first time and the second time;

the control circuit generates a first feedback signal based on the obtained detection result, and the control circuit comprises:

and the control circuit generates the first control signal based on the obtained precedence relationship between the appearance moments of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance moments.

In the above scheme, the method further comprises:

the edge detection circuit generates a first identification signal after detecting a first change edge in the first signal and a first change edge in the second signal;

the control circuit generates a second control signal according to the first identification signal;

and the power switch circuit of the duty ratio calibration device responds to the second control signal to turn off the power supply of the duty ratio detection circuit.

In the above aspect, the duty detection circuit includes:

a first duty detection sub-circuit for generating the first signal based on a high level in the clock signal;

a second duty cycle detection sub-circuit to generate the second signal based on a low level in the clock signal.

In the above aspect, the duty detection circuit includes: the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit; wherein the content of the first and second substances,

the power switching circuit responds to the second control signal to turn off the power supply of the duty ratio detection circuit, and comprises:

the power supply switching circuit responds to the second control signal and turns off the power supply of the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit;

the first duty cycle detection sub-circuit is used for generating the first signal based on a high level in the clock signal;

the second duty detection sub-circuit is configured to generate the second signal based on a low level in the clock signal.

The embodiment of the invention provides a duty ratio calibration device and method. Wherein the duty calibration device comprises: a duty ratio detection circuit for generating a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal; the edge detection circuit is used for detecting a first change edge in the first signal and a first change edge in the second signal to obtain a detection result; a control circuit for generating a first control signal based on the obtained detection result; and the duty ratio adjusting circuit is used for calibrating the clock signal according to the first control signal. According to the scheme of the embodiment of the invention, the distortion condition of the clock signal to be calibrated can be obtained when the first change edge of the first signal of the high-level part information corresponding to the clock signal to be calibrated and the first change edge of the second signal of the low-level part information corresponding to the clock signal to be calibrated are respectively detected, so that the distortion condition can be utilized to carry out quick response on the calibration of the high-speed clock signal, and the quick calibration of the high-speed clock signal can be realized.

Drawings

FIG. 1 is a schematic block diagram of a duty cycle calibration apparatus in the related art;

FIG. 2 is a schematic diagram illustrating a flow chart of an implementation of a duty calibration apparatus in the related art;

FIG. 3 is a schematic diagram of a hardware circuit of a duty cycle detection circuit of a duty cycle calibration apparatus in the related art;

FIG. 4 is a schematic diagram of an output waveform of a duty ratio detection circuit of a duty ratio calibration apparatus in the related art;

FIG. 5 is a first schematic structural diagram of a duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 6 is a schematic block diagram of a duty cycle calibration apparatus according to an embodiment of the present invention;

FIG. 7 is a first schematic diagram of a hardware implementation of an edge detection circuit of a duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 8 is a first schematic diagram illustrating output and input signals of an edge detection circuit of a duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 9 is a first flowchart illustrating a software implementation of an edge detection circuit of a duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 11 is a block diagram illustrating a second hardware implementation of an edge detection circuit of the duty ratio calibration apparatus according to the embodiment of the present invention;

FIG. 12 is a schematic diagram of the output and input signals of the edge detection circuit of the duty ratio calibration apparatus according to the embodiment of the present invention;

FIG. 13 is a second schematic diagram illustrating a software implementation process of an edge detection circuit of a duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 14 is a diagram illustrating a software simulation result of an edge detection circuit of the duty ratio calibration apparatus according to an embodiment of the present invention;

FIG. 15 is a schematic hardware circuit diagram of a power switching circuit of the duty ratio calibration apparatus according to the embodiment of the present invention;

fig. 16 is a schematic flow chart illustrating an implementation process of the duty ratio calibration method according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.

The general duty ratio calibration devices are divided into three types, namely an analog duty ratio calibration device, a digital duty ratio calibration device and a digital-analog mixed duty ratio calibration device; the digital-analog hybrid combines a digital duty ratio calibration device and an analog feedback duty ratio calibration device, so that a good compromise can be achieved between the speed and the calibration precision, but the circuit is relatively complex. The duty ratio calibration device mentioned in the embodiment of the invention is a digital-analog mixed duty ratio calibration device.

As shown in fig. 1, a Duty ratio calibration apparatus in the related art includes a Duty ratio adjusting circuit, a differential circuit, two Duty ratio detection circuits (DCD for short), a frequency detection circuit, and a control circuit. An implementation flow diagram of a DCC device in the related art is shown in fig. 2, and the implementation flow is specifically as follows:

inputting a clock signal CK to be calibrated; CK firstly passes through a differential circuit, and the differential circuit converts a clock signal CK to be calibrated into differential clock signals CK _ P and CK _ PB to be calibrated; CK _ P and CK _ PB enter two duty ratio detection circuits together, and the two duty ratio detection circuits respectively convert the duty ratio information of CK into a signal RCK carrying CK high-level information and a signal RBCK carrying CK low-level information; the RCK and the RBCK enter a frequency detection circuit together, and the frequency detection circuit detects the frequency of the RCK and the RBCK; the frequencies of the RCK and the RBCK enter a control circuit; the control circuit judges whether the CK is distorted, namely the duty ratio of CK is more than 50% or less than 50% according to the frequencies of RCK and RBCK (when the duty ratio of CK is equal to 50%, the duty ratio is a normal value, and at the moment, calibration is not needed).

However, in the related art, the frequency detection circuit needs to detect and analyze the entire waveforms of RCK and RBCK to obtain the frequencies of RCK and RBCK, and therefore, it takes a long time to determine the distortion of the clock signal by using the frequency detection circuit, and the speed of duty calibration by using the duty calibration device of the frequency detection circuit is slow.

In practical application, the principle of the duty ratio detection circuit is combined, and the judgment mode of the CK distortion condition can be optimized. Specifically, the method comprises the following steps:

a hardware composition circuit of the duty ratio detection circuit is shown in fig. 3, and the duty ratio detection circuit includes a mirror switch circuit, a Resistance Capacitance (RC) circuit, and a schmitt trigger; wherein: the mirror switch circuit enables selection of a high level in CK (i.e., a high level in CK _ P and a low level in CK _ PB); the RC circuit and the mirror image switch circuit are used for realizing the charging and discharging of the capacitor; the Schmitt trigger changes the charge-discharge state of the capacitor through the change of the trigger state. Here, RCK is finally generated using the duty detection circuit shown in fig. 3.

It should be noted that the duty ratio detection circuit shown in fig. 3 is the duty ratio detection circuit on the left side in fig. 2, while the duty ratio detection circuit on the right side in fig. 2 needs to adjust the mirror switching circuit shown in fig. 3, so that the adjusted mirror switching circuit can realize the selection of the low level in CK (i.e., the low level in CK _ P and the high level in CK _ PB).

The waveform diagram of the duty cycle detection circuit is shown in fig. 4, in which: CK _ P and CK _ PB are signals input to the mirror switch circuit, respectively; to _ sch and to _ schb are signals at input ends of schmitt triggers of two duty cycle detection circuits (the duty cycle detection circuit on the left side in fig. 2 and the duty cycle detection circuit on the right side in fig. 2), respectively; RCK and RBCK are signals at output terminals of schmitt triggers of two duty ratio detection circuits (the duty ratio detection circuit on the left side in fig. 2 and the duty ratio detection circuit on the right side in fig. 2), respectively.

The principle of converting the duty ratio information of CK into the signal RCK carrying CK high level information and the signal RBCK carrying CK low level information by the specific duty ratio detection circuit will be described below with reference to fig. 3 and 4.

Assuming that the duty ratio of CK is 60%, the high level of CK _ P is 60% and the low level of CK _ PB is 60%. In the first period of CK, CK _ P and CK _ PB are input into the mirror switch circuit in FIG. 3 together, the output of the Schmitt trigger is initialized to a low level (e.g., 0V in FIG. 4), when CK _ PB is at a low level, PMOS1 and PMOS2 are both turned on, capacitor C begins to charge once, but due to the high trigger threshold V of the Schmitt trigger_HThis one charge (CK 60% of one cycle) does not raise the input voltage of the schmitt trigger to the high trigger threshold V relatively high (e.g., 7V in fig. 4)_HAfter one-time charging is finished, the input voltage of the Schmitt trigger is increased (namely the charging voltage of the capacitor C), but the output of the Schmitt trigger is still at a low level; at this time, CK _ P is high and NMOS2 is on, but since the output of the schmitt trigger is low, NMOS1 is off and the discharge circuit of capacitor C is off. When CK _ PB enters a high level, both PMOS1 and PMOS2 are not conductive, and capacitor C cannot be charged; at this time, CK _ P is low, NMOS1 and NMOS2 are not conductive, the discharge circuit of the capacitor C is turned off, and the charge voltage of the capacitor C is maintained. That is, in the first cycle of CK, the capacitor C is charged once for 60% of the cycle of CK, and there is no discharge state. Thus, the state of the capacitor C is repeated in the first period after the first period of CK in N periods (N is an integer larger than or equal to 1) until the charging voltage of the capacitor C rises to the high trigger threshold V of the Schmitt trigger_H。

V after reaching the trigger threshold of the Schmitt trigger_HThe output of the schmitt trigger is high (e.g., 5V in fig. 4). In the next cycle of CK, when CK _ PB is low, PMOS1 is turned on, but since the output of the Schmitt trigger is highPMOS2 is not conductive and capacitor C cannot be charged; at this time, CK _ P is high, NMOS1 and NMOS2 are both turned on, the discharge circuit of the capacitor C is turned on, and the capacitor C starts to discharge once. This one discharge (60% of one cycle of CK) does not bring the input voltage of the schmitt trigger down to the low trigger threshold V_L(e.g., 5V in fig. 4), after a discharge is completed, the output voltage of the schmitt trigger decreases, but the output of the schmitt trigger may still be high. When CK _ PB enters a high level, PMOS1 and PMOS2 are not conducted, and capacitor C cannot be charged; at this time, CK _ P is low, NMOS1 is on, but NMOS2 is off, and the capacitor C cannot be discharged. That is, in this period of CK, the capacitor C has a discharge time of 60% of the CK period and no charge state. Thus, the state is repeated for M (M is an integer greater than or equal to 1) cycles of the capacitor C after the cycle of CK until the charging voltage of the capacitor C is reduced to the low trigger threshold V of the Schmitt trigger_L。

As can be seen from the above analysis, since the CK _ P duty ratio is 60% and the CK _ PB duty ratio is 40%, the charge time per time is 60% and the discharge time is 60% for the duty detection circuit of fig. 3 (the left duty detection circuit in fig. 2); on the other hand, in the duty detection circuit on the right side in fig. 2, since the charge time per charge is 40% and the discharge time is 40%, the output signal RCK of the duty detection circuit on the left side and the output signal RBCK of the duty detection circuit on the left side are represented by: the first trigger time of the Schmitt trigger in the duty ratio detection circuit on the left side is faster, and the change period of the Schmitt trigger is smaller.

Based on this, in the embodiments of the present invention, the frequency detection circuit in the duty ratio calibration apparatus in the related art is replaced with the edge detection circuit, and the edge detection circuit detects the first change edge of RCK and RBCK, and the duty ratio calibration apparatus can obtain the CK distortion by using the detection result. In this way, the duty ratio calibration device in the embodiments of the present invention can reduce the response period of the frequency detection circuit, thereby contributing to the improvement of the calibration speed of the duty ratio.

Fig. 5 is a diagram illustrating a structure of a duty calibration apparatus according to an embodiment of the present invention, and the duty calibration apparatus 500 according to an embodiment of the present invention includes: a duty cycle detection circuit 501, an edge detection circuit 502, a control circuit 503, and a duty cycle adjustment circuit 504; wherein the content of the first and second substances,

the duty ratio detection circuit 501 is configured to generate a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

the edge detection circuit 502 is configured to detect a first changing edge in the first signal and a first changing edge in the second signal to obtain a detection result;

the control circuit 503 is configured to generate a first control signal based on the obtained detection result;

the duty cycle adjusting circuit 504 is configured to calibrate the clock signal according to the first control signal.

In practical application, a functional block diagram of the duty ratio calibration apparatus 500 according to an embodiment of the present invention is shown in fig. 6, where the duty ratio calibration apparatus 500 includes: a differential circuit, two duty cycle detection circuits 501, an edge detection circuit 502, a control circuit 503, and a duty cycle adjustment circuit 504; wherein: the differential circuit converts the clock signal CK into differential signals CK _ P and CK _ PB of the clock signal, so as to facilitate signal processing of the subsequent duty detection circuit 501; the duty ratio detection circuit 501 converts the duty ratio information of CK into a signal RCK carrying CK high level information and a signal RBCK carrying CK low level information by the signal processing principle; the edge detection circuit 502 detects the first change edge of RCK and RBCK and transmits the detection result to the control circuit 503; the control circuit 503 can obtain the distortion condition of CK according to the detection result, and at the same time, formulate a corresponding control instruction for duty ratio adjustment according to the distortion condition, and transmit the control instruction to the duty ratio adjustment circuit 504; the duty cycle adjusting circuit 504 performs corresponding duty cycle calibration according to the control command.

In the case of practical application, the duty detection circuit 501 may be realized by converting the duty information of CK into the signal RCK carrying CK high level information and the signal RBCK carrying CK low level information, and is not limited to the above principle. That is, the duty detection circuit 501 may directly process the CK signal itself without processing the differential signal of CK to obtain RCK and RBCK, or may directly include the differential circuit in the duty detection circuit 501.

The duty ratio detection circuit 501 mainly converts duty ratio information of the clock signal CK into a signal RCK carrying CK high level information and a signal RBCK carrying CK low level information.

Here, the clock signal is a high-speed clock signal to be subjected to duty ratio calibration; the high level refers to a portion of the clock signal with a high voltage, and the low level refers to a portion of the clock signal with a low voltage. In practical applications, the clock signal may be a square wave signal, the high level may be a high voltage portion of the square wave signal, and the low-high level may be a ground voltage portion of the square wave signal.

Here, the specific implementation principle of the duty detection circuit 501 is as described above.

In one embodiment, the duty cycle detection circuit includes: a first duty detection circuit and a second duty detection circuit; wherein the content of the first and second substances,

the first duty cycle detection circuit is used for generating the first signal based on a high level in the clock signal;

the second duty cycle detection circuit is configured to generate the second signal based on a low level in the clock signal.

Here, the first duty detection circuit may be analogized to the duty detection circuit on the left side in fig. 2; the second duty cycle detection circuit may be analogized to the duty cycle detection circuit on the left side in fig. 2. It can be understood that: the first duty detection circuit may enable selection of high level information in CK (i.e., high level in CK _ P and low level in CK _ PB); the second duty cycle detection circuit can enable selection of low level information in CK (i.e., low level in CK _ P and high level in CK _ PB).

The edge detection circuit 502 mainly detects the time when the first change edge of RCK appears and the time when the first change edge of RBCK appears.

It should be noted that, for convenience of understanding in this embodiment, the first change edges are listed as rising edges.

The analysis according to the realization principle of the duty ratio detection circuit can obtain that: when a first change edge appears in RCK (representing CK high level information) and RBCK (representing CK low level information), that is, the schmitt trigger in the duty cycle detection circuit is triggered for the first time, at this time, the sequence of the first change edge of RCK and the first change edge of RBCK can indicate that the duty cycle of CK is more than 50% or less than 50% (who appears first and represents that the duty cycle of CK is large); and, the specific value of the CK duty ratio can be obtained according to the time interval of the first change edge of RCK and the first change edge of RBCK.

Here, the method of obtaining the specific value of the CK duty ratio from the time interval in which the first variation edge of RCK and the first variation edge of RBCK occur is as follows:

t₁-t₂＝Δt (1)

V_H＝E[1-exp(-xt₁/RC)] (2)

V_H＝E[1-exp(-(1-x)t₂/RC)] (3)

wherein, t₁The moment when the first change edge of RCK appears; t is t₂The moment when the first change edge of the RBCK appears; delta t is the time interval of the occurrence of the first change edge of RCK and the first change edge of RBCK; x is the duty cycle of CK; v_HA high trigger threshold for a schmitt trigger in duty cycle detection circuit 501; e is the voltage value of the power supply in the duty ratio detection circuit 501; r is a resistance value in the RC resistor in the duty ratio detection circuit 501; c is a capacitance value in the RC resistor in the duty detection circuit 501.

In formulae 2 and 3, V_HE, R, C all can be from duty cycle detection circuit501, substituting formula 2 and formula 3 into formula 1, and calculating the value of x when Δ t is detected by the edge detection circuit 502, i.e. obtaining the specific value of the CK duty ratio.

Based on this, in an embodiment, the edge detection circuit 502 is specifically configured to: detecting a first time when a first changing edge appears in the first signal and a second time when the first changing edge appears in the second signal; obtaining the appearance time sequence relation of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance time based on the first time and the second time;

the control circuit 503 is specifically configured to generate the first control signal based on the obtained precedence relationship between the occurrence times of the first change edge in the first signal and the first change edge in the second signal and the time interval of the occurrence times.

Here, using the precedence order relationship between the first changing edge in the first signal and the first changing edge in the second signal obtained by the edge detecting circuit 502 and the time interval of the appearance time, the control circuit 503 can obtain the distortion condition of the duty ratio of the clock signal CK (the specific value of the CK duty ratio).

In practical application, a hardware implementation block diagram of the edge detection circuit 502 is shown in fig. 7, where input signals of the edge detection circuit 502 are: the clock signal CLK, the signal RCK carrying CK high level information, the signal RBCK carrying CK low level information of the edge detection circuit 502 and the parameter release signal release of the edge detection circuit 502; the output signals of the edge detection circuit 502 are: CK _ P _ first represents a flag signal that a first change edge in RCK first appears (e.g., the initial value of CK _ P _ first is set to low level 0, when the first change edge in RCK appears earlier than the first change edge in RBCK, CK _ P _ first is set to high level 1 at the time when the first change edge in RCK appears, CK _ P _ first is always low level 0 when the first change edge in RCK appears later than the first change edge in RBCK), CK _ PB _ first represents a flag signal that the first change edge in RBCK first appears (e.g., the initial value of CK _ PB _ first is set to low level 0, when the first change edge in RBCK appears earlier than the first change edge in RCK, CK _ PB _ first is set to high level 1 at the time when the first change edge in RBCK appears, and when the first change edge in RBCK appears later than the first change edge in RCK, CK _ PB _ first is always low 0), count represents the number of counts elapsed between the occurrence of the first changing edge in RCK and the occurrence of the first changing edge in RBCK.

In practical application, the value of count and the triggering relationship between the clock CLK and the counter of the edge detection circuit 502 are used to obtain the time interval Δ t of the first change edge of RCK and the first change edge of RBCK. For example, if a cycle of CLK in the edge detection circuit 502 triggers a count of the counter, Δ t is obtained by multiplying the value of count by the cycle of CLK.

Fig. 8 is a schematic diagram of input and output signals corresponding to a hardware implementation block diagram of the edge detection circuit 502 shown in fig. 7. In fig. 8, the initial value of CK _ P _ first is set to low level 0, the first change edge in RCK appears earlier than the first change edge in RBCK, and CK _ P _ first is set to high level 1 at the time when the first change edge in RCK appears; the initial value of CK _ PB _ first is set to be low level 0, the first change edge in RBCK appears later than the first change edge in RCK, and CK _ PB _ first is set to be low level 0 all the time; count represents the number of counts elapsed between the time of occurrence of the first changing edge in RCK and the time of occurrence of the first changing edge in RBCK.

Fig. 9 is a software flow diagram of a hardware implementation block diagram of the edge detection circuit 502 shown in fig. 7. First, when there is no measurement task, the edge detection circuit 502 is in an idle state; when the RCK and the RBCK are input, the edge detection circuit 502 is reset, when the reset is not completed, the edge detection circuit 502 enters an idle state, and when the reset is not completed, the edge detection circuit 502 starts to perform exclusive or processing on the RCK and the RBCK; when the exclusive or result is 1, it is stated that one of RCK and RBCK has a high level 1, and at this time, if RCK equals 1, CK _ P _ first is set to 1

(the first edge of change to the RCK appears first) and starts the count until RBCK equals 1

(indicating that the first edge of change of RBCK is also present); if RBCK is equal to 1, CK _ PB _ first is set to 1 (it means that the first change edge of RBCK appears first), and count is started until RCK is equal to 1 (it means that the first change edge of RCK also appears), so far, the detection of the time when the first change edge of RCK and the first change edge of RBCK appear has been completed, the parameter release signal release is set to 1, all the parameters are released, that is, CK _ P _ first, CK _ PB _ first, and count are reset to initial values, and the edge detection circuit 502 enters the idle state again.

In practical applications, the edge detection Circuit 502 may be implemented by an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

After obtaining the detection result (i.e. the precedence relationship between the appearance time of the first changing edge in the first signal and the appearance time of the first changing edge in the second signal and the time interval of the appearance time), the edge detection circuit 502 sends the detection result to the control circuit 503.

The control circuit 503 can obtain the distortion condition of CK by receiving the detection result of the edge detection circuit 502, and at the same time, formulate a corresponding control instruction for duty ratio adjustment according to the distortion condition, and transmit the control instruction to the duty ratio adjustment circuit 504.

In practical applications, the control circuit 503 may be a Central Processing Unit (CPU) or a Micro Control Unit (MCU) or other devices with control functions.

After receiving the control command from the control circuit, the duty ratio adjusting circuit 504 performs corresponding duty ratio calibration according to the control command, so that the clock signal CK returns to a normal value (e.g., 50%).

An embodiment of the present invention provides a duty ratio calibration apparatus, including: a duty ratio detection circuit for generating a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal; the edge detection circuit is used for detecting a first change edge in the first signal and a first change edge in the second signal to obtain a detection result; a control circuit for generating a first control signal based on the obtained detection result; and the duty ratio adjusting circuit is used for calibrating the clock signal according to the first control signal. According to the scheme of the embodiment of the invention, the distortion condition of the clock signal to be calibrated can be obtained when the first change edge of the first signal of the high-level part information corresponding to the clock signal to be calibrated and the first change edge of the second signal of the low-level part information corresponding to the clock signal to be calibrated are respectively detected, so that the distortion condition can be utilized to carry out quick response on the calibration of the high-speed clock signal, and the quick calibration of the high-speed clock signal can be realized.

In practical application, the duty ratio calibration device is considered to acquire the distortion condition of the clock signal to be calibrated when detecting the first change edge of the first signal of the high-level part information corresponding to the clock signal to be calibrated and the first change edge of the second signal of the low-level part information corresponding to the clock signal to be calibrated respectively, and at this moment, the calibration work can be completed, so that the duty ratio detection circuit can finish the detection work.

Based on this, the embodiment of the present invention further provides a duty ratio calibration apparatus 1000, and fig. 10 shows a structural composition diagram of the duty ratio calibration apparatus 1000 according to the embodiment of the present invention, where the duty ratio calibration apparatus 1000 includes:

a duty detection circuit 1001 for generating a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

an edge detection circuit 1002, configured to detect a first variation edge in the first signal and a first variation edge in the second signal to obtain a detection result;

a control circuit 1003 configured to generate a first control signal based on the obtained detection result;

a duty cycle adjusting circuit 1004 for calibrating the clock signal according to the first control signal.

Wherein the edge detection circuit 1002 is further configured to: generating a first identification signal after detecting a first change edge in the first signal and a first change edge in the second signal;

the control circuit 1003 is further configured to generate a second control signal according to the first identification signal;

the duty ratio calibration apparatus 1000 further includes a power switch circuit 1005, configured to turn off the power supply of the duty ratio detection circuit 1001 in response to the second control signal.

The duty ratio calibration device 1000 in this embodiment is basically the same as the duty ratio calibration device 500 in the foregoing implementation principle of duty ratio calibration, and the difference is that: the duty ratio calibration device 1000 according to the present embodiment includes a power supply switching circuit 1005, and the power supply switching circuit 1005 controls power supply to the duty ratio detection circuit 1001; meanwhile, the edge detection circuit 1002 is also functionally optimized according to the power switch circuit 1005.

Here, the first identification signal is used to identify that the edge detection circuit 1002 has completed a certain time of edge detection.

The edge detection circuit 1002 in this embodiment is basically the same as the edge detection circuit 502 described above in principle, but different therefrom in that: the edge detector circuit 1002 of this embodiment adds an output signal that identifies the completion of the edge detection operation of the edge detector circuit 1002.

The hardware implementation block diagram of the edge detection circuit 1002 in this embodiment is shown in fig. 11, where input signals of the edge detection circuit 1002 are: a clock signal CLK, a signal RCK carrying CK high level information, a signal RBCK carrying CK low level information of the edge detection circuit 1002 and a parameter release signal release of the edge detection circuit 1002; the output signals of the edge detection circuit 1002 are: the output signals of the edge detection circuit 1002 are: CK _ P _ first represents a flag signal that a first change edge in RCK first appears (e.g., the initial value of CK _ P _ first is set to low level 0, when the first change edge in RCK appears earlier than the first change edge in RBCK, CK _ P _ first is set to high level 1 at the time when the first change edge in RCK appears, CK _ P _ first is always low level 0 when the first change edge in RCK appears later than the first change edge in RBCK), CK _ PB _ first represents a flag signal that the first change edge in RBCK first appears (e.g., the initial value of CK _ PB _ first is set to low level 0, when the first change edge in RBCK appears earlier than the first change edge in RCK, CK _ PB _ first is set to high level 1 at the time when the first change edge in RBCK appears, and when the first change edge in RBCK appears later than the first change edge in RCK, CK _ PB _ first is always low level 0), count represents the number of counts elapsed between the occurrence of the first changing edge in RCK and the occurrence of the first changing edge in RBCK; EN _ PG indicates a flag signal indicating that both the first change edge in RCK and the first change edge in RBCK have occurred (e.g., the initial value of EN _ PG is set to low level 0, and EN _ PG is set to high level 1 when both the first change edge in RCK and the first change edge in RBCK have occurred and the first change edge later occurs).

Fig. 12 is a schematic diagram of input and output signals corresponding to a hardware implementation block diagram of the edge detection circuit 1002 shown in fig. 11. In fig. 12, the initial value of CK _ P _ first is set to low level 0, the first change edge in RCK appears earlier than the first change edge in RBCK, and CK _ P _ first is set to high level 1 at the time when the first change edge in RCK appears; the initial value of CK _ PB _ first is set to be low level 0, the first change edge in RBCK appears later than the first change edge in RCK, and CK _ PB _ first is set to be low level 0 all the time; count represents the number of counts elapsed between the occurrence of the first change edge in RCK and the occurrence of the first change edge in RBCK, the initial value of EN _ PG is set to low level 0, both the occurrence of the first change edge in RCK and the occurrence of the first change edge in RBCK have occurred, and EN _ PG is set to high level 1 at the occurrence of the first change edge in RBCK later.

Fig. 13 is a software flow diagram of a hardware implementation block diagram for implementing the edge detection circuit 1002 shown in fig. 11. First, when there is no measurement task, the edge detection circuit 1002 is in an idle state; when the RCK and the RBCK are input, the edge detection circuit 1002 is reset, when the reset is not completed, the edge detection circuit 1002 enters an idle state, and when the reset is not completed, the edge detection circuit 1002 starts to perform exclusive or processing on the RCK and the RBCK; when the exclusive or result is 1, it indicates that one of RCK and RBCK has a high level 1, and at this time, if RCK equals to 1, CK _ P _ first is set to 1 (which indicates that the first change edge of RCK appears first), and count is started until RBCK equals to 1 (which indicates that the first change edge of RBCK also appears); if RBCK is equal to 1, CK _ PB _ first is set to 1 (it means that the first change edge of RBCK appears first), and count is started until RCK is equal to 1 (it means that the first change edge of RCK also appears), so far, detection of the time when the first change edge of RCK and the first change edge of RBCK appear has been completed, EN _ PG is set to high level 1, then a parameter release signal release is set to 1, all parameters are released, that is, CK _ P _ first, CK _ PB _ first, and count are reset to initial values of 0, and the edge detection circuit 1002 enters the idle state again.

Fig. 14 shows simulation results obtained by using the edge detection circuit 1002 shown in fig. 11, which are consistent with actual analysis.

In practical applications, the edge detection circuit 1002 may be implemented by an ASIC or an FPGA.

When the edge detection circuit 1002 obtains that EN _ PG is set to high level 1, the first identification signal is sent to the control circuit 1003.

The control circuit 1003, when receiving the first identification signal, generates a second control signal for turning off the power supply of the duty ratio detection circuit 1001.

In one embodiment, the duty cycle detection circuit 1001 includes: the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit; wherein the content of the first and second substances,

the power switch circuit 1005 is configured to turn off power supply to the first duty detection sub-circuit and the second duty detection sub-circuit in response to the second control signal;

the first duty cycle detection sub-circuit is used for generating the first signal based on a high level in the clock signal;

the second duty detection sub-circuit is configured to generate the second signal based on a low level in the clock signal.

In practical application, a hardware circuit diagram of the power switch circuit 1005 is shown in fig. 15, and the main implementation principle in fig. 15 is the same as that in fig. 3, except that: a power switch circuit 1005 is added to the hardware circuit shown in fig. 3.

In practical applications, the power switch circuit 1005 may be implemented by using a switch transistor (e.g., a PMOS transistor in fig. 15). When EN _ PG is set to high level 1, the control circuit 503 sends a clear signal, and the power switching circuit turns off the switching tube under the action of the clear signal (low level 0) to turn off the power supplies of the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit (only the first duty ratio detection sub-circuit is shown in fig. 15).

It should be noted that: fig. 15 shows only a part of the power switch circuit 1005 corresponding to the first duty detection sub-circuit, and in practical applications, the power switch circuit 1005 also has a part of the circuit corresponding to the second duty detection sub-circuit, and is used for turning off the power supply of the second duty detection sub-circuit under the action of the clear signal (low level 0).

It should be noted that: after the control circuit 1003 sends the second control signal, after receiving a command input by the upper computer, the control circuit may also send a third control command (a command for turning on the power supply of the duty ratio detection circuit 1001) in a preset period. Here, the power switch circuit 1005 turns on the power supply of the duty detection circuit 1001 in response to the third control signal, so as to facilitate the development of the next duty calibration.

The duty ratio calibration device in the embodiment of the invention can firstly realize the quick calibration of the high-speed clock signal, and secondly, the power supply of the duty ratio detection circuit is turned off when the detection work of the edge detection circuit is completed, so that the duty ratio detector has no power consumption, and the effect of reducing the power consumption of the duty ratio calibration device is achieved.

Based on the above apparatus, an embodiment of the present invention further provides a duty ratio calibration method, as shown in fig. 16, where the duty ratio calibration method includes the following steps:

step 1601: a duty ratio detection circuit of the duty ratio calibration device generates a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal;

step 1602: an edge detection circuit of the duty ratio calibration device detects a first change edge in the first signal and a first change edge in the second signal to obtain a detection result;

step 1603: a control circuit of the duty ratio calibration device generates a first control signal based on the obtained detection result;

step 1604: and a duty ratio adjusting circuit of the duty ratio calibrating device calibrates the clock signal according to the first control signal.

In one embodiment, the detecting the first changing edge in the first signal and the first changing edge in the second signal by the edge detecting circuit to obtain the detecting result includes:

the edge detection circuit detects a first time when a first changing edge appears in the first signal and a second time when the first changing edge appears in the second signal; obtaining the appearance time sequence relation of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance time based on the first time and the second time;

the control circuit generates a first feedback signal based on the obtained detection result, and the control circuit comprises:

and the control circuit generates the first control signal based on the obtained precedence relationship between the appearance moments of the first change edge in the first signal and the first change edge in the second signal and the time interval of the appearance moments.

In an embodiment, the method further comprises:

the edge detection circuit generates a first identification signal after detecting a first change edge in the first signal and a first change edge in the second signal;

the control circuit generates a second control signal according to the first identification signal;

and the power switch circuit of the duty ratio calibration device responds to the second control signal to turn off the power supply of the duty ratio detection circuit.

In one embodiment, the duty cycle detection circuit includes:

a first duty detection sub-circuit for generating the first signal based on a high level in the clock signal;

a second duty cycle detection sub-circuit to generate the second signal based on a low level in the clock signal.

In one embodiment, the duty cycle detection circuit includes: the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit; wherein the content of the first and second substances,

the power switching circuit responds to the second control signal to turn off the power supply of the duty ratio detection circuit, and comprises:

the power supply switching circuit responds to the second control signal and turns off the power supply of the first duty ratio detection sub-circuit and the second duty ratio detection sub-circuit;

the first duty cycle detection sub-circuit is used for generating the first signal based on a high level in the clock signal;

the second duty detection sub-circuit is configured to generate the second signal based on a low level in the clock signal.

The embodiment of the invention provides a duty ratio calibration method, which comprises the following steps: a duty ratio detection circuit of the duty ratio calibration device generates a first signal and a second signal based on a clock signal; the first signal carries information of a high-level part in the clock signal; the second signal carries information of a low level part in the clock signal; an edge detection circuit of the duty ratio calibration device detects a first change edge in the first signal and a first change edge in the second signal to obtain a detection result; a control circuit of the duty ratio calibration device generates a first control signal based on the obtained detection result; and a duty ratio adjusting circuit of the duty ratio calibrating device calibrates the clock signal according to the first control signal. According to the scheme of the embodiment of the invention, the distortion condition of the clock signal to be calibrated can be obtained when the first change edge of the first signal of the high-level part information corresponding to the clock signal to be calibrated and the first change edge of the second signal of the low-level part information corresponding to the clock signal to be calibrated are respectively detected, so that the distortion condition can be utilized to carry out quick response on the calibration of the high-speed clock signal, and the quick calibration of the high-speed clock signal can be realized.

It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.