阅读说明：本技术 驱动电路 (Driving circuit ) 是由 林志轩 黄绍璋 陈俊智 邱华琦 于 2018-06-25 设计创作，主要内容包括：本发明提供一种驱动电路,包括一检测电路、一第一控制电路、一第二控制电路以及一驱动晶体管。检测电路耦接于一第一电源端以及一第二电源端之间,并根据第一及第二电源端的电压产生一检测信号。第一控制电路根据检测信号产生一第一控制信号。第二控制电路根据检测信号产生一第二控制信号。驱动晶体管耦接于一输入输出垫与第二电源端之间。当检测信号为一第一位准时,驱动晶体管根据第一控制信号而导通。当检测信号为一第二位准时,驱动电路根据第二控制信号而动作。第一位准不同于第二位准。本发明的驱动电路具有静电放电保护。(The invention provides a driving circuit, which comprises a detection circuit, a first control circuit, a second control circuit and a driving transistor. The detection circuit is coupled between a first power end and a second power end and generates a detection signal according to the voltages of the first power end and the second power end. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input/output pad and a second power source terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving circuit acts according to the second control signal. The first level is different from the second level. The driving circuit of the invention has electrostatic discharge protection.)

1. A driver circuit, comprising:

the detection circuit is coupled between a first power supply end and a second power supply end and generates a detection signal according to the voltages of the first power supply end and the second power supply end;

a first control circuit for generating a first control signal according to the detection signal;

a second control circuit for generating a second control signal according to the detection signal; and

and a driving transistor coupled between an input/output pad and the second power terminal, wherein the driving transistor is turned on according to the first control signal when the detection signal is at a first level, and operates according to the second control signal when the detection signal is at a second level, the first level being different from the second level.

2. The driving circuit of claim 1, wherein the driving transistor is an N-type transistor.

3. The driving circuit of claim 2, wherein the detection circuit comprises a resistor coupled between the first power source terminal and a common node, and a capacitor coupled between the common node and the second power source terminal.

4. The driving circuit of claim 3, wherein the first control circuit comprises:

a voltage generating circuit for generating an output voltage according to the voltages of the first power terminal and the input/output pad; and

a first P-type transistor having a gate coupled to the common node, a source coupled to the I/O pad, a drain coupled to the gate of the N-type transistor, and a body receiving the output voltage.

5. The driving circuit as recited in claim 4, wherein the output voltage is equal to the voltage of the first power terminal when the voltage of the first power terminal is higher than the voltage of the I/O pad, and the output voltage is equal to the voltage of the I/O pad when the voltage of the I/O pad is higher than the voltage of the first power terminal.

6. The driving circuit of claim 4, wherein the voltage generating circuit comprises:

a second P-type transistor having a gate coupled to the I/O pad, a source coupled to the first power terminal, and a drain and a body coupled to the body of the first P-type transistor; and

a third P-type transistor having a gate coupled to the first power terminal, a source coupled to the I/O pad, and a drain and a body coupled to the body of the first P-type transistor.

7. The driving circuit of claim 1, wherein the driving transistor is a P-type transistor.

8. The driving circuit as claimed in claim 7, wherein the detecting circuit comprises a first capacitor and a resistor, the first capacitor is coupled between the first power source terminal and a common node, and the resistor is coupled between the common node and the second power source terminal.

9. The driving circuit of claim 8, wherein the first control circuit comprises:

an N-type transistor having a gate coupled to the common node, a drain coupled to the gate of the P-type transistor, a source coupled to the I/O pad, and a body coupled to the first power terminal; and

and a coupling element coupled between the gate of the P-type transistor and the input/output pad.

10. The driving circuit of claim 9, wherein the coupling element is a second capacitor.

11. The driving circuit of claim 1, wherein the second control circuit comprises:

and a transmission gate coupled between the gate of the driving transistor and a core circuit, wherein when the detection signal is at the second level, the transmission gate provides an output signal generated by the core circuit as the second control signal to the driving transistor, and when the detection signal is at the first level, the transmission gate stops providing the output signal as the second control signal.

12. The driving circuit of claim 11, wherein the second control signal is a floating level when the detection signal is at the first level.

13. The driving circuit of claim 1, wherein the second control circuit comprises:

and the transmission gate is coupled between the grid of the driving transistor and a core circuit, and provides an output signal generated by the core circuit as the second control signal to the driving transistor when the detection signal is at the first level, and stops using the output signal as the second control signal when the detection signal is at the second level.

14. The driving circuit of claim 13, wherein the second control signal is a floating level when the detection signal is at the second level.

Technical Field

The present invention relates to a driving circuit, and more particularly, to a driving circuit with electrostatic discharge (ESD) protection.

Background

Device damage due to electrostatic discharge has become one of the most important reliability issues for integrated circuit products. Particularly, as the size of the integrated circuit is continuously reduced to the deep submicron level, the gate oxide layer of the metal oxide semiconductor is thinner and thinner, and the integrated circuit is more likely to be damaged by the electrostatic discharge phenomenon.

Disclosure of Invention

The invention provides a driving circuit, which comprises a detection circuit, a first control circuit, a second control circuit and a driving transistor. The detection circuit is coupled between a first power end and a second power end and generates a detection signal according to the voltages of the first power end and the second power end. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input/output pad and a second power source terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving circuit acts according to the second control signal. The first level is different from the second level.

The driving circuit of the invention has electrostatic discharge protection.

Drawings

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a voltage generating circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a control circuit according to an embodiment of the invention.

Fig. 4 is another possible schematic diagram of the driving circuit of the present invention.

Fig. 5 is another possible schematic diagram of the control circuit of the present invention.

Reference numerals

100. 400: a drive circuit;

110. 410: a detection circuit;

111. 411: a resistance;

112. 412: a capacitor;

113. 413: a common node;

120. 130, 420, 430: a control circuit;

121. 210, 220, 320, 520: a P-type transistor;

122: a voltage generating circuit;

140. 440, a step of: a drive transistor;

141. 441: a diode;

151. 152, 451, 452: a power supply terminal;

153. 453: an input-output pad;

160. 460: a core circuit;

310. 421, 510: an N-type transistor;

330. 530: an inverter;

422: a coupling element;

SO: outputting the signal;

SG1, SG 4: detecting a signal;

SG2, SG3, SG5, SG 6: a control signal;

VO: and outputting the voltage.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of the elements in the embodiments is for illustration and not for limitation. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the invention. As shown, the driving circuit 100 is coupled to the power source terminals 151 and 152 and an input/output pad 153. When the power source terminal 151 receives a high operating voltage (e.g., 5V) and the power source terminal 152 receives a low operating voltage (e.g., 0V), the driving circuit 100 operates in a normal mode. In the normal mode, the driving circuit 100 generates the output signal S according to the core circuit 160_OA driving coupling is connected with the input/output pad153, such as an array device (array device).

However, when the power source terminal 152 receives a ground voltage and the power source terminal 151 is in a floating state, the driving circuit 100 enters a protection mode. In the protection mode, the driving circuit 100 has a discharging capability for discharging the ESD current from the I/O pad 153 or the power source terminal 152. For example, when a positive ESD voltage is generated on the I/O pad 153 and the power source 152 is grounded, the driving circuit 100 discharges an ESD current from the I/O pad 153 to the power source 152. When a negative ESD voltage occurs on the I/O pad 153 and the power terminal 152 is grounded, the driving circuit 100 discharges an ESD current from the power terminal 152 to the I/O pad 153.

In the present embodiment, the driving circuit 100 includes a detecting circuit 110, control circuits 120 and 130, and a driving transistor 140. The detecting circuit 110 is coupled between the power source terminals 151 and 152, and generates a detecting signal S according to the voltages of the power source terminals 151 and 152_G1. In one embodiment, the detection circuit 110 sets the detection signal S when the voltage of the power terminal 152 is at a ground voltage and the power terminal 151 is in a floating state_G1Is at a first level (e.g., low). In another possible embodiment, the detection circuit 110 sets the detection signal S when the power source terminal 151 receives an operating voltage (e.g., 5V) and the power source terminal 152 receives a ground voltage_G1At a second level (e.g., high level).

The present invention does not limit the circuit architecture of the detection circuit 110. In the present embodiment, the detection circuit 110 includes a resistor 111 and a capacitor 112. The resistor 111 is coupled between the power source 151 and a common node 113. The capacitor 112 is coupled between the common node 113 and the power source terminal 152. In this case, when the power source terminal 152 receives a ground voltage and the power source terminal 151 is in a floating state, the level of the common node 113 is a low level, i.e., the detection signal S_G1Is low. In another embodiment, when the power source terminal 151 receives a first operating voltage (e.g., 5V) and the power source terminal 152 receives a second operating voltage (e.g., ground voltage), the level of the common node 113 is a high level, i.e., the level is highDetecting the signal S_G1Is high.

The control circuit 120 is based on the detection signal S_G1Generating a control signal S_G2. For example, when detecting the signal S_G1When the level is the first level (e.g. low level), the control circuit 120 sets the control signal S_G2At a third level. In one possible embodiment, the third level may be equal to the level of the input/output pad 153. However, when the signal S is detected_G1When the level is the second level (e.g. high level), the control circuit 120 stops providing the control signal S_G2. At this time, the control signal S_G2May be a floating level.

The present invention is not limited to the circuit architecture of the control circuit 120. In one embodiment, the control circuit 120 includes a P-type transistor 121 and a voltage generation circuit 122. The P-type transistor 121 has a gate coupled to the common node 113, a source coupled to the input/output pad 153, a drain coupled to the gate of the driving transistor 140, and a body receiving an output voltage V_O. In one possible embodiment, the output voltage V_OIs a high voltage. For example, the output voltage V_OMay be approximately equal to the level of the input-output pad 153.

The voltage generating circuit 122 is used to generate a high voltage to the body of the P-type transistor 121 to prevent the P-type transistor 121 from generating a leakage current. In a possible embodiment, the voltage generating circuit 122 generates the output voltage V according to the voltages of the power source terminal 151 and the input/output pad 153_O. For example, when the voltage of the power source terminal 151 is higher than the voltage of the i/o pad 153, the voltage generating circuit 122 outputs the voltage of the power source terminal 151 to the substrate of the P-type transistor 121. When the voltage of the input/output pad 153 is higher than the voltage of the power source terminal 151, the voltage generating circuit 122 provides the voltage of the input/output pad 153 to the substrate of the P-type transistor 121. The present invention is not limited to the circuit architecture of the voltage generating circuit 122. One possible implementation architecture of the voltage generation circuit 122 will be described later using fig. 2.

The control circuit 130 is based on the detection signal S_G1Generating a control signal S_G3. In the present embodiment, the control circuit 130 is coupled between the detection circuit 110 and the core circuit 160,and provides a control signal S_G3To the gate of the drive transistor 140. When detecting the signal S_G1When the level is the second level (e.g. high level), the control circuit 130 outputs the output signal S generated by the core circuit 160_OAs a control signal S_G3Is provided to the driving transistor 140. When detecting the signal S_G1When the level is the first level (e.g. low level), the control circuit 130 stops outputting the signal S_OAs a control signal S_G3. At this time, the control signal S_G3May be a floating level.

The present invention does not limit the circuit architecture of the control circuit 130. In one possible embodiment, the control circuit 130 includes a transmission gate (transmission gate). In this example, when the signal S is detected_G1When the level is high, the transmission gate is turned on to output the signal S_OAs a control signal S_G3Is provided to the driving transistor 140. When detecting the signal S_G1At low level, the transmission gate is not turned on to prevent an ESD current from entering the core circuit 160. In other embodiments, the control circuit 130 may be omitted if the core circuit 160 has a protection circuit for blocking the ESD voltage. In this example, the core circuit 160 is directly coupled to the driving transistor 140.

In addition, the present invention is not limited to the circuit architecture of the core circuit 160. In one possible embodiment, when the signal S is output_OWhen the high level is reached, the control signal S_G3Also high. When outputting the signal S_OWhen the level is low, the control signal S_G3Also low. In other embodiments, the signal S is output_OIs opposite to the control signal S_G3The level of (c). For example, when outputting the signal S_OWhen the high level is reached, the control signal S_G3Is low. When outputting the signal S_OWhen the level is low, the control signal S_G3Is high.

The driving transistor 140 is coupled between the input/output pad 153 and the power source terminal 152. When the power source terminal 152 receives a ground voltage and the power source terminal 151 is in a floating state, the detection signal S_G1Is low. When the level of the input/output pad 153 is higher than the detection signal S_G1When the level of (1) is high, P-typeTransistor 121 is turned on. At this time, when the input/output pad 153 receives a positive ESD voltage, the control signal S_G2Is high. Therefore, the driving transistor 140 is turned on to discharge an ESD current from the I/O pad 153 to the power source 152. However, if the input/output pad 153 receives a negative ESD voltage and the power terminal 152 receives a ground voltage, the parasitic diode 141 of the driving transistor 140 is turned on to discharge an ESD current.

When the power source terminal 151 receives a first operating voltage (e.g., 5V) and the power source terminal 152 receives a second operating voltage (e.g., ground voltage), the detection signal S_G1At a second level (e.g., high). At this time, the control signal S_G2Is not controlled by the control circuit 120, and the driving transistor 140 is driven according to the control signal S_G3And acts. For example, when the control signal S_G3At a fourth timing, the driving transistor 140 is not turned on. When the control signal S_G3At a fifth level, the driving transistor 140 is turned on to provide a driving current (not shown). The driving transistor 140 has a large driving capability due to its large channel size. In the present embodiment, the driving transistor 140 is an N-type transistor. The driving transistor 140 has a gate coupled to the control circuits 120 and 130, a source coupled to the input/output pad 153, and a drain and a body coupled to the power source terminal 152.

Fig. 2 is a schematic diagram of a voltage generating circuit according to an embodiment of the invention. In the present embodiment, the voltage generation circuit 122 includes P-type transistors 210 and 220. The P-type transistor 210 has a gate coupled to the input/output pad 153, a source coupled to the power source 151, and a drain and body coupled to the body of the P-type transistor 121. When the voltage of the input/output pad 153 is lower than the voltage of the power terminal 151, the P-type transistor 210 is turned on to use the voltage of the power terminal 151 as the output voltage V_O。

The P-type transistor 220 has a gate coupled to the power source terminal 151, a source coupled to the input/output pad 153, and a drain and body coupled to the body of the P-type transistor 121. In the present embodiment, when the voltage of the power source terminal 151 is lower than the voltage of the input/output pad 153, the P-type transistor 220 is turned on to couple the inputThe voltage of the output pad 153 is taken as the output voltage V_O。

Fig. 3 is a schematic diagram of a control circuit 130 according to an embodiment of the invention. As shown, the control circuit 130 includes an N-type transistor 310, a P-type transistor 320, and an inverter 330. The gate of the N-type transistor 310 is coupled to the input terminal of the inverter 330 and receives the detection signal S_G1. The drain of the N-type transistor 310 receives the output signal S_OIts source is coupled to the gate of the driving transistor 140, and its body is coupled to the power source terminal 152. In the present embodiment, when the signal S is detected_G1Is at a second level (e.g., high level) and outputs a signal S_OWhen the level is low, the N-type transistor 310 is turned on to output the signal S_OAs a control signal S_G3Is provided to the driving transistor 140. However, when the signal S is detected_G1At a first level (e.g., low level), the N-type transistor 310 is turned off.

The P-type transistor 320 has a gate coupled to the output terminal of the inverter 330, and a source receiving the output signal S_OIts drain is coupled to the gate of the driving transistor 140, and its body is coupled to the power source terminal 151. In the present embodiment, when the signal S is detected_G1Is at a second level (e.g., high level) and outputs a signal S_OWhen high, the P-type transistor 320 is turned on to output the signal S_OAs a control signal S_G3Is provided to the driving transistor 140. However, when the signal S is detected_G1At a first level (e.g., low level), the P-type transistor 320 is turned off.

Fig. 4 is another possible embodiment of the driving circuit of the present invention. As shown, the driving circuit 400 is coupled to the power terminals 451 and 452 and an input/output pad 453. When the power source terminal 451 receives a high operating voltage (e.g., 5V) and the power source terminal 452 receives a low operating voltage (e.g., 0V), the driving circuit 400 operates in a normal mode. In the normal mode, the driving circuit 400 generates the output signal S according to the core circuit 460_ODriving a load (not shown). However, when the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, the driving circuit 400 operates in a protection mode. In the protection mode, when an ESD event occurs on the power terminal 451 or the I/O pad453, the driving circuit 400 discharges the ESD current from the power terminal 451 or the I/O pad 453.

In the present embodiment, the driving circuit 400 includes a detecting circuit 410, control circuits 420 and 430, and a driving transistor 440. The detection circuit 410 is coupled between the power terminals 451, 452, and generates a detection signal S according to the voltages of the power terminals 451, 452_G4. In one embodiment, the detection circuit 410 sets the detection signal S when the power source terminal 451 receives a first operating voltage (e.g., 5V) and the power source terminal 452 receives a second operating voltage (e.g., ground voltage)_G4Is at a first level (e.g., low). In another embodiment, the detection circuit 410 sets the detection signal S when the voltage of the power terminal 451 is at a ground voltage and the power terminal 452 is in a floating state_G4At a second level (e.g., high).

The present invention does not limit the circuit architecture of the detection circuit 410. In one embodiment, the detection circuit 410 includes a resistor 411 and a capacitor 412. The resistor 411 is coupled between the power source 452 and a common node 413. The capacitor 412 is coupled between the common node 413 and the power source terminal 451. In this example, when the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, the level of the common node 413 is the second level (e.g., high level). Thus, the signal S is detected_G4Also at the second level. In another embodiment, when the power source terminal 451 receives a first operating voltage (e.g., 5V) and the power source terminal 452 receives a second operating voltage (e.g., ground voltage), the level of the common node 413 is at the first level (e.g., low level). In this example, the signal S is detected_G4Is at a first level.

The control circuit 420 is based on the detection signal S_G4Generating a control signal S_G5. For example, when detecting the signal S_G4At the first level, if the input/output pad 453 receives a negative ESD voltage, the control circuit 420 sets the control signal S_G5At a third level (e.g., a low level). In one possible embodiment, the third level may be equal to the level of the input/output pad 453. However, when the power supply terminal 451 receives a first operating voltage (e.g., 5V) and the power supply terminal 452 receivesWhen a second operating voltage (e.g., ground voltage) is applied, the control circuit 420 stops providing the control signal S_G5. At this time, the control signal S_G5May be a floating level.

The present invention is not limited to the circuit architecture of the control circuit 420. In one embodiment, the control circuit 420 includes an N-type transistor 421 and a coupling element 422. The N-type transistor 421 has a gate coupled to the common node 413, a source coupled to the input/output pad 453, a drain coupled to the gate of the driving transistor 440, and a body coupled to the power source terminal 452. The coupling element 422 is coupled between the gate of the driving transistor 440 and the input/output pad 453. In one embodiment, the coupling element 422 is a capacitor. When the input/output pad 453 receives a negative ESD voltage, the coupling element 422 pulls the control signal S low_G5The level of (c). In another possible embodiment, the N-type transistor 421 is turned on, and the control signal S is pulled down_G5The level of (c). In one possible embodiment, the control signal S_G5Approximately equal to the level of the input/output pad 453.

The control circuit 430 detects the signal S_G4Generating a control signal S_G6. In the embodiment, the control circuit 430 is coupled between the gate of the driving transistor 440 and the detection circuit 410, and receives the output signal S generated by the core circuit 460_O. In one embodiment, the power source 452 is grounded, so that the detection signal S_G4At a first level (e.g., low). At this time, if the ESD event does not occur, the control circuit 430 outputs the output signal S generated by the core circuit 460_OAs a control signal S_G6Is provided to the driving transistor 440. However, when the signal S is detected_G4When the level is at the second level (e.g., high level) and an ESD event occurs at the I/O pad 453, the control circuit 430 stops outputting the signal S_OAs a control signal S_G6. At this time, the control signal S_G6May be in a floating state. The present invention does not limit the circuit architecture of the control circuit 430. A possible circuit architecture of the control circuit 430 will be explained later by means of fig. 5. In addition, the characteristics of the core circuit 460 are similar to those of the core circuit 160 in fig. 1, and thus are not described again.

The driving transistor 440 is coupled between the input/output pad 453 and the power source terminal 451. When the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, the control signal S_G4At a first level (e.g., low). At this time, if the input/output pad 453 receives a negative ESD voltage, the N-type transistor 421 is turned on because the source voltage of the N-type transistor 421 is lower than the gate voltage of the N-type transistor 421, and the coupling element 422 pulls down the control signal S_G5The level of (c). Due to the control signal S_G5At a low level, the driving transistor 440 is turned on to discharge an ESD current. However, if the input/output pad 453 receives a positive ESD voltage and the power terminal 151 receives a ground voltage, the parasitic diode 441 of the driving transistor 440 is turned on to discharge an ESD current to ground.

When the power supply terminal 451 receives a first operating voltage (e.g., 5V) and the power supply terminal 452 receives a second operating voltage (e.g., ground), the gate and body of the N-type transistor 421 are approximately equal to the second operating voltage. The N-type transistor 421 is therefore non-conductive. At this time, the control signal S_G5Is a floating level. In this example, the driving transistor 440 is based on the control signal S_G6And acts. For example, when the control signal S_G6At a fourth level (e.g., high level), the driving transistor 440 is not turned on. When the control signal S_G6At a fifth level (e.g., low level), the driving transistor 440 is turned on. The driving transistor 440 has a large driving capability due to its large channel size.

In the present embodiment, the driving transistor 440 is a P-type transistor. The driving transistor 440 has a gate coupled to the control circuits 420 and 430, a drain coupled to the input/output pad 453, and a source and a body coupled to the power source terminal 451.

Fig. 5 is a schematic diagram of a possible embodiment of the control circuit 430 in fig. 4. The control circuit 430 includes an N-type transistor 510, a P-type transistor 520, and an inverter 530. The input of inverter 530 receives control signal S_G4. The output terminal of the inverter 530 is coupled to the gate of the N-type transistor 510. The drain of the N-type transistor 510 receives the output signal S_OWhich isThe source is coupled to the gate of the driving transistor 440, and the body is coupled to the power source terminal 452. The P-type transistor 520 has a gate coupled to the input of the inverter 530, and a source receiving the output signal S_OIts drain is coupled to the gate of the driving transistor 440, and its body is coupled to the power source terminal 451.

When detecting the signal S_G4At a first level (e.g., a low level), the N-type transistor 510 and the P-type transistor 520 are turned on to output the signal S_OAs a control signal S_G6Is provided to the driving transistor 440. When detecting the signal S_G4At a second level (e.g., high level), the N-type transistor 510 and the P-type transistor 520 are turned off. At this time, the control signal S_G6May be a floating level.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the system, apparatus or method of embodiments of the present invention may be implemented in physical embodiments of hardware, software or a combination of hardware and software. Therefore, the protection scope of the present invention is subject to the claims.