阅读说明：本技术 一种旁路代路通道切换有效性检测电路、装置和方法 (Bypass substitute path switching validity detection circuit, device and method ) 是由 孙迪飞 罗振华 蔡松昆 王英民 王掬涵 钟振兴 罗步升 罗韩华 李伟强 于 2021-09-27 设计创作，主要内容包括：本发明公开了一种旁路代路通道切换有效性检测电路、装置和方法,包括输入模块、控制模块和输出模块,在旁路代路时由输入模块根据接收到的测试指令切换相应的开关状态和时间参数；由控制模块根据测试指令对开关状态和时间参数进行逻辑判断,基于逻辑判断结果控制输出模块切换至相应的工作状态；由输出模块模拟输出旁路代路中的跳闸信号,以对光纤接口装置的发信指示灯和保护装置的收信开入量进行验证。通过对输入的开关状态与时间参数的逻辑判断结果控制输出模块的工作状态,以模拟输出相应的跳闸信号,对旁路代路中的光纤接口装置以及保护装置的收发信指示进行验证,实现高效便捷的旁路代路通道切换有效性测试,提高旁路代路通道切换的可靠性。(The invention discloses a bypass route-replacing channel switching effectiveness detection circuit, a device and a method, wherein the bypass route-replacing channel switching effectiveness detection circuit comprises an input module, a control module and an output module, wherein the input module switches corresponding switch states and time parameters according to a received test instruction when a bypass is used for replacing a route; the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result; the output module simulates and outputs a tripping signal in the bypass path to verify the receiving input of the transmitting indicator light of the optical fiber interface device and the protection device. The working state of the output module is controlled through the logic judgment result of the input switch state and the time parameter so as to output a corresponding tripping signal in a simulation mode, the transceiving indication of the optical fiber interface device and the protection device in the bypass route replacement is verified, the efficient and convenient bypass route replacement switching effectiveness test is realized, and the reliability of bypass route replacement switching is improved.)

1. A bypass route-replacing channel switching effectiveness detection circuit is characterized by comprising an input module, a control module and an output module, wherein when a bypass route is replaced, the input module switches corresponding switch states and time parameters according to a received test instruction; the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result; and the output module simulates and outputs a tripping signal in the bypass route to verify the receiving input of the transmitting indicator light of the optical fiber interface device and the protection device.

2. The bypass substitute path switching validity detection circuit according to claim 1, further comprising a sampling module and a delay module, wherein the sampling module samples an input voltage and outputs the sampled voltage to the control module, the delay module sets a delay time of a preset loop according to a received test instruction, and the control module is further configured to perform a logic determination on the switch state, the time parameter, the sampled voltage, and the delay time of the preset loop according to the test instruction, and control the output module to switch to a corresponding operating state based on a logic determination result.

3. The bypass routing channel switching validity detection circuit of claim 2, wherein the input module comprises a first input switch, a control switch, and a second input switch, the first input switch, the control switch, and the second input switch are all connected to the control module, wherein the first input switch is a single-position input switch, and the second input switch is a two-position input switch;

when a first test instruction is received, the first input switch is switched to a closed state and first reset time is set; when a second test instruction is received, the first input switch is switched to a closed state and second reset time is set; when a third test instruction is received, the first input switch is switched to be in a closed state, the control switch is switched to be in the closed state in a delayed mode, and third reset time and a voltage threshold value are set; and when a fourth test instruction is received, the second input switch is switched to a preset level combination.

4. The bypass routing channel switch validity detection circuit of claim 3, wherein the output module includes a first output switch, a second output switch, a third output switch, and a fourth output switch, and the first output switch, the second output switch, the third output switch, and the fourth output switch are all connected to the control module.

5. The bypass proxy channel switching validity detection circuit of claim 4, wherein the control module is specifically configured to, when receiving a first test instruction, determine whether the first input switch is closed, and if so, control the first output switch to be synchronously closed and reset after keeping a first reset time;

when a second test instruction is received, whether the first input switch is closed or not is confirmed, if yes, the second output switch is controlled to be synchronously closed, timing is started when the first input switch is detected to reset, and the second output switch is controlled to reset when a timing value is larger than or equal to second reset time;

when a third test instruction is received, whether the first input switch is closed or not is confirmed, if yes, the third output switch is controlled to be synchronously closed, timing is started when the first input switch is detected to be reset, the control switch is closed after the delay time, and the sampling voltage is greater than or equal to a voltage threshold value, and the third output switch is controlled to be reset when a timing value is greater than or equal to a third reset time;

and when a fourth test instruction is received, whether the second input switch is switched to the first level combination is determined, if so, the fourth output switch is controlled to be closed, and the fourth output switch is controlled to be reset until the second input switch is switched to the second level combination.

6. The bypass routing channel switching validity detection circuit of claim 2, wherein the sampling module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a first inductor, a second inductor, an optocoupler, and a first operational amplifier;

one end of the first resistor is connected with a voltage input end, and the other end of the first resistor is connected with one end of the third resistor and one end of the fourth resistor through the second resistor; the other end of the third resistor is grounded; the other end of the fourth resistor is connected with a No. 2 pin of the optocoupler and one end of a second capacitor; one end of the fifth resistor is connected with a 7 th pin of the optocoupler and one end of the third capacitor, and the other end of the fifth resistor is connected with a non-inverting input end of the first operational amplifier, one end of the seventh resistor and one end of the eighth resistor; one end of the sixth resistor is connected with a pin 6 of the optocoupler and one end of the fourth capacitor, and the other end of the sixth resistor is connected with the inverting input end of the first operational amplifier, one end of the sixth capacitor, one end of the ninth resistor and one end of the tenth resistor; the other end of the seventh resistor is grounded; the other end of the eighth resistor is connected with a reference signal end; the other end of the ninth resistor is connected with the other end of the sixth capacitor, the other end of the tenth resistor, one end of the eleventh resistor and the output end of the first operational amplifier; the other end of the eleventh resistor is connected with a sampling voltage output end and one end of the ninth capacitor; one end of the first capacitor is connected with a No. 1 pin and a first power supply end of the optocoupler, and the other end of the first capacitor, the other end of the second capacitor, the other end of the third capacitor and the other end of the fourth capacitor are all grounded; one end of the fifth capacitor is connected with the 8 th pin of the optocoupler and one end of the first inductor, and the other end of the fifth capacitor is grounded; the positive electrode of the seventh capacitor is connected with the positive power supply end of the first operational amplifier, one end of an eighth capacitor and one end of a second inductor, and the negative electrode of the seventh capacitor is connected with the other end of the eighth capacitor and the ground; the other end of the ninth capacitor is grounded; the other end of the first inductor is connected with a second power supply end; the other end of the second inductor is connected with a third power supply end.

7. The bypass proxy channel switching validity detection circuit of claim 6, wherein the delay module comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a tenth capacitor, a second operational amplifier, a diode, and a relay;

one end of the twelfth resistor is connected with the cathode of the diode, the second power supply end and the first connection end of the thirteenth resistor, and the other end of the twelfth resistor is connected with the anode of the diode, one end of the tenth capacitor and the non-inverting input end of the second operational amplifier; a second connection end of the thirteenth resistor is grounded, and a control end of the thirteenth resistor is connected with an inverting input end of the second operational amplifier; one end of the fourteenth resistor is connected with the output end of the second operational amplifier, and the other end of the fourteenth resistor is connected with the coil anode of the relay; one end of the fifteenth resistor is connected with a normally open end of the relay, and the other end of the fifteenth resistor is connected with a coil cathode of the relay, a cathode of a voltage source and the ground; and the common end of the coil is connected with the anode of a voltage source, and the other end of the tenth capacitor is grounded.

8. The bypass routing channel switching validity detection circuit of any one of claims 1-7, wherein the control module employs a microcontroller of model number STM32F103RBT 6.

9. A method for detecting the switching effectiveness of a bypass routing channel is characterized by comprising the following steps:

when the bypass is used for routing, the input module switches corresponding switch states and time parameters according to the received test instruction;

the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result;

and the output module simulates and outputs a tripping signal in the bypass route to verify the receiving input of the transmitting indicator light of the optical fiber interface device and the protection device.

10. A bypass substitute path switching validity detection device, comprising a shell, wherein a PCB board is arranged in the shell, and the bypass substitute path switching validity detection device is characterized in that the PCB board is provided with the bypass substitute path switching validity detection circuit as claimed in any one of claims 1 to 8.

Technical Field

The invention relates to the technical field of power equipment, in particular to a bypass substitute path switching validity detection circuit, a bypass substitute path switching validity detection device and a bypass substitute path switching validity detection method.

Background

In an electric power system, when a line switch bypass in a traditional transformer substation of 110kV or above is replaced, a receiving and transmitting channel switching handle needs to be switched from a local line to the bypass, so that a receiving and transmitting loop is switched from main protection to bypass protection, and the protection function of the receiving and transmitting loop and opposite side protection communication is achieved.

In the actual bypass substitute operation, occasionally, the condition that the integrity of the protection transmitting loop is damaged due to the fact that the channel switching handle is not switched in place occurs, so that the transmitting and receiving contact cannot be conducted, and further communication is interrupted. To avoid communication interruption caused by channel switching failing to reach bit.

The existing solution is to increase the test pressing plate by adopting the protection screen, and to check the integrity of the loop by switching the test pressing plate, but the method needs to use a large amount of spare pressing plates, and needs the telephone communication cooperation of operators on two sides of the circuit protection to switch the pressing plate in and out when checking the integrity of the loop, so that the time consumption is long, and the problem of low detection efficiency of bypass channel switching effectiveness exists.

Disclosure of Invention

In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a circuit, an apparatus and a method for detecting validity of bypass substitute path switching, which aim to solve the problem of low efficiency of detecting validity of bypass substitute path switching in the prior art.

The technical scheme of the invention is as follows:

a bypass route-replacing channel switching effectiveness detection circuit comprises an input module, a control module and an output module, wherein when a bypass route is replaced, the input module switches corresponding switch states and time parameters according to a received test instruction; the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result; and the output module simulates and outputs a tripping signal in the bypass route to verify the receiving input of the transmitting indicator light of the optical fiber interface device and the protection device.

In one embodiment, the device further comprises a sampling module and a delay module, wherein the sampling module samples an input voltage and outputs the sampled voltage to the control module, the delay module sets a delay time of a preset loop according to a received test instruction, and the control module is further configured to perform logic judgment on the switch state, the time parameter, the sampled voltage and the delay time of the preset loop according to the test instruction, and control the output module to switch to a corresponding working state based on a logic judgment result.

In one embodiment, the input module comprises a first input switch, a control switch and a second input switch, wherein the first input switch, the control switch and the second input switch are all connected with the control module, the first input switch is a single-position input switch, and the second input switch is a double-position input switch;

when a first test instruction is received, the first input switch is switched to a closed state and first reset time is set; when a second test instruction is received, the first input switch is switched to a closed state and second reset time is set; when a third test instruction is received, the first input switch is switched to be in a closed state, the control switch is switched to be in the closed state in a delayed mode, and third reset time and a voltage threshold value are set; and when a fourth test instruction is received, the second input switch is switched to a preset level combination.

In one embodiment, the output module comprises a first output switch, a second output switch, a third output switch and a fourth output switch, and the first output switch, the second output switch, the third output switch and the fourth output switch are all connected with the control module.

In one embodiment, the control module is specifically configured to, when a first test instruction is received, determine whether the first input switch is closed, and if so, control the first output switch to be synchronously closed and reset after a first reset time is kept;

when a second test instruction is received, whether the first input switch is closed or not is confirmed, if yes, the second output switch is controlled to be synchronously closed, timing is started when the first input switch is detected to reset, and the second output switch is controlled to reset when a timing value is larger than or equal to second reset time;

when a third test instruction is received, whether the first input switch is closed or not is confirmed, if yes, the third output switch is controlled to be synchronously closed, timing is started when the first input switch is detected to be reset, the control switch is closed after the delay time, and the sampling voltage is greater than or equal to a voltage threshold value, and the third output switch is controlled to be reset when a timing value is greater than or equal to a third reset time;

and when a fourth test instruction is received, whether the second input switch is switched to the first level combination is determined, if so, the fourth output switch is controlled to be closed, and the fourth output switch is controlled to be reset until the second input switch is switched to the second level combination.

In one embodiment, the sampling module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a first inductor, a second inductor, an optocoupler, and a first operational amplifier;

one end of the first resistor is connected with a voltage input end, and the other end of the first resistor is connected with one end of the third resistor and one end of the fourth resistor through the second resistor; the other end of the third resistor is grounded; the other end of the fourth resistor is connected with a No. 2 pin of the optocoupler and one end of a second capacitor; one end of the fifth resistor is connected with a 7 th pin of the optocoupler and one end of the third capacitor, and the other end of the fifth resistor is connected with a non-inverting input end of the first operational amplifier, one end of the seventh resistor and one end of the eighth resistor; one end of the sixth resistor is connected with a pin 6 of the optocoupler and one end of the fourth capacitor, and the other end of the sixth resistor is connected with the inverting input end of the first operational amplifier, one end of the sixth capacitor, one end of the ninth resistor and one end of the tenth resistor; the other end of the seventh resistor is grounded; the other end of the eighth resistor is connected with a reference signal end; the other end of the ninth resistor is connected with the other end of the sixth capacitor, the other end of the tenth resistor, one end of the eleventh resistor and the output end of the first operational amplifier; the other end of the eleventh resistor is connected with a sampling voltage output end and one end of the ninth capacitor; one end of the first capacitor is connected with a No. 1 pin and a first power supply end of the optocoupler, and the other end of the first capacitor, the other end of the second capacitor, the other end of the third capacitor and the other end of the fourth capacitor are all grounded; one end of the fifth capacitor is connected with the 8 th pin of the optocoupler and one end of the first inductor, and the other end of the fifth capacitor is grounded; the positive electrode of the seventh capacitor is connected with the positive power supply end of the first operational amplifier, one end of an eighth capacitor and one end of a second inductor, and the negative electrode of the seventh capacitor is connected with the other end of the eighth capacitor and the ground; the other end of the ninth capacitor is grounded; the other end of the first inductor is connected with a second power supply end; the other end of the second inductor is connected with a third power supply end.

In one embodiment, the delay module comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a tenth capacitor, a second operational amplifier, a diode and a relay;

one end of the twelfth resistor is connected with the cathode of the diode, the second power supply end and the first connection end of the thirteenth resistor, and the other end of the twelfth resistor is connected with the anode of the diode, one end of the tenth capacitor and the non-inverting input end of the second operational amplifier; a second connection end of the thirteenth resistor is grounded, and a control end of the thirteenth resistor is connected with an inverting input end of the second operational amplifier; one end of the fourteenth resistor is connected with the output end of the second operational amplifier, and the other end of the fourteenth resistor is connected with the coil anode of the relay; one end of the fifteenth resistor is connected with a normally open end of the relay, and the other end of the fifteenth resistor is connected with a coil cathode of the relay, a cathode of a voltage source and the ground; and the common end of the coil is connected with the anode of a voltage source, and the other end of the tenth capacitor is grounded.

In one embodiment, the control module employs a microcontroller of model STM32F103RBT 6.

Another embodiment of the present invention further provides a method for detecting the effectiveness of bypass routing channel switching, including:

when the bypass is used for routing, the input module switches corresponding switch states and time parameters according to the received test instruction;

the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result;

and the output module simulates and outputs a tripping signal in the bypass route to verify the receiving input of the transmitting indicator light of the optical fiber interface device and the protection device.

The invention further provides a bypass route-substituting channel switching effectiveness detection device, which comprises a shell, wherein a PCB is arranged in the shell, and the PCB is provided with the bypass route-substituting channel switching effectiveness detection circuit.

Has the advantages that: compared with the prior art, the embodiment of the invention controls the working state of an output module through the logic judgment result of the input switch state and the time parameter so as to simulate and output a corresponding trip signal and verify the transceiving indication of an optical fiber interface device and a protection device in the bypass route, thereby realizing the efficient and convenient bypass route-replacement switching effectiveness test and improving the reliability of the bypass route-replacement switching.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

fig. 1 is a block diagram of a bypass proxy channel switching validity detection circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an input module and an output module in a bypass substitute path switching validity detection circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a working state switching of an output module in a bypass substitute path switching validity detection circuit according to an embodiment of the present invention;

fig. 4 is a circuit diagram of a sampling module in a bypass substitute path switching validity detection circuit according to an embodiment of the present invention;

fig. 5 is a circuit diagram of a delay module in a bypass substitute path switching validity detection circuit according to an embodiment of the present invention;

fig. 6 is a flowchart of a method for detecting validity of bypass proxy channel switching according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Embodiments of the present invention will be described below with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a block diagram illustrating an embodiment of a bypass proxy channel switching validity detection circuit according to the present invention. When the bypass channel switching validity detection circuit is applied specifically, the bypass channel switching validity detection circuit is connected with the optical fiber interface device and the protection device in the pilot protection channel, so that whether a channel switching handle is switched in place and whether a communication loop is normal or not when the bypass channel is replaced is verified. As shown in fig. 1, the bypass substitute path switching validity detection circuit includes an input module 11, a control module 12 and an output module 13, wherein the input module 11 and the output module 13 are both connected to the control module 12, and the input module 11 switches corresponding switch states and time parameters according to a received test instruction when a bypass substitute path is performed; the control module 12 performs logic judgment on the switch state and the time parameter according to the test instruction, and controls the output module 13 to switch to the corresponding working state based on the logic judgment result; the output module 13 simulates and outputs the trip signal in the bypass path to verify the sending indicator light of the optical fiber interface device and the receiving input of the protection device.

In this embodiment, when performing bypass route-replacing protection, an operator may input a corresponding test instruction according to test requirements, the input module 11 switches a corresponding switch state and time parameter according to the received test instruction, the control module 12, after detecting the currently set switch state and time parameter, performs logic judgment on the current switch state and actual parameter according to the test instruction, controls the output module 13 to switch to a corresponding working state based on the logic judgment result, so that the output module 13 can simulate and output a trip signal in the bypass route-replacing, and verifies the sending indicator of the optical fiber interface device and the incoming amount of the received signal of the protection device by using the trip signal, that is, when the trip signal is simulated and output, it can verify whether the sending indicator of the optical fiber interface device is turned on and whether the incoming amount of the received signal of the protection device is shifted normally, therefore, the loop integrity of the bypass circuit-replacing switching channel is verified, the validity is confirmed in a mode of efficiently simulating and outputting a trip signal, and the reliability of channel switching during bypass circuit replacement is ensured. The specific control module 12 may adopt a microcontroller of the model STM32F103RBT6, however, in other embodiments, other controllers with the same function may also be adopted, and the present embodiment is not limited thereto.

In an embodiment, the bypass substitute path switching validity detection circuit further includes a sampling module 14 and a delay module 15, where the sampling module 14 and the delay module 15 are both connected to the control module 12, the sampling module 14 samples the input voltage and outputs the sampled voltage to the control module 12, the delay module 15 sets a delay time of the preset loop according to the received test instruction, and the control module 12 is further configured to perform a logic determination on the switch state, the time parameter, the sampled voltage, and the delay time of the preset loop according to the test instruction, and control the output module 13 to switch to a corresponding working state based on a logic determination result.

In this embodiment, in order to implement a more diversified test scheme to be compatible with different test scenarios, the sampling module 14 samples the input voltage to obtain a corresponding sampling voltage, and the delay module 15 controls the delay output of a corresponding preset loop according to the test instruction during the test, so that the control module 12 can further perform logic judgment by combining the sampling voltage and the delay time of the preset loop on the basis of the currently set switch state and time parameter, and further control the switching of the operating state of the output module 13, so that the output module 13 outputs a corresponding trip signal under more diversified test conditions to perform the validity test of channel switching, thereby enriching the test scenarios of the validity test, widening the application range of the validity test circuit, and ensuring the loop integrity of the bypass circuit under different test scenarios.

In one embodiment, as shown in fig. 2, the input module 11 includes a first input switch 111, a control switch 112, and a second input switch 113, and the first input switch 111, the control switch 112, and the second input switch 113 are all connected to the control module 12, wherein the first input switch 111 is a single-position input switch, and the second input switch 113 is a two-position input switch, specifically, the first input switch 111 includes a single-position 1-way switch, i.e., switch K, the control switch 112 includes a single-position 1-way switch, i.e., switch ST, and the second input switch 113 includes a two-position 2-way switch, i.e., switch K1 and switch K2.

When receiving the first test instruction, the first input switch 111 is switched to a closed state and sets a first reset time; when a second test instruction is received, the first input switch 111 is switched to a closed state and a second reset time is set; when a third test instruction is received, the first input switch 111 is switched to a closed state, the switch 112 is controlled to be switched to the closed state in a delayed mode, and a third reset time and a voltage threshold value are set; when receiving the fourth test command, the second input switch 113 switches to the preset level combination. That is, in this embodiment, the operator may issue different test instructions according to the test requirement, and different test instructions may adjust corresponding input parameters, including switch states and time parameters, for example, under the first test instruction and the second test instruction, different reset times may be set, and under the third test instruction, not only different reset times may be set, but also the operating state and the voltage threshold of the switch ST may be further set, and under the fourth test instruction, a preset level combination of the switch K1 and the switch K2 may be set, so as to implement state changes of two-position switch input, for example, the switch K1 is set to 1, the switch K2 is set to 0, or the switch K1 is set to 0, the switch K2 is set to 1, and thus, when performing an effectiveness test, multi-path signal input may be implemented to provide a diversified test scenario, and the compatibility of the effectiveness detection circuit is improved.

In one embodiment, as shown in fig. 2, the output module 13 includes a first output switch 131, a second output switch 132, a third output switch 133 and a fourth output switch 134, the first output switch 131, the second output switch 132, the third output switch 133 and the fourth output switch 134 are all connected to the control module 12, specifically, the output module 13 includes output switches corresponding to different test instructions, and each output switch can further perform extended output on the input switches to meet the signal output requirement of the multi-phase transceiver loop test in the validity test, specifically, the first output switch 131 is a 4-way extended switch including a switch KM1, a switch KM2, a switch KM3 and a switch KM4, the second output switch 132 is a 1-way switch including a switch KM5, the third output switch 133 is a 1-way switch including a switch KM6, the fourth output switch 134 is a 3-way switch, the circuit testing device comprises a switch KM7, a switch KM8 and a switch KM9, wherein the output module 13 is subjected to expanded output through the output module 13, when different testing instructions are received, the working state of each switch in the output module 13 can be controlled after the control module 12 carries out corresponding logic operation according to input parameters, so that tripping signals under different testing scenes in a bypass circuit are simulated and output, and efficient, flexible and diverse circuit validity verification is realized.

In an embodiment, the control module 12 is specifically configured to, when receiving the first test instruction, determine whether the first input switch 111 is closed, and if so, control the first output switch 131 to be synchronously closed and reset after keeping the first reset time;

when a second test instruction is received, whether the first input switch 111 is closed or not is confirmed, if yes, the second output switch 132 is controlled to be synchronously closed, timing is started when the first input switch 111 is detected to reset, and the second output switch 132 is controlled to reset when the timing value is larger than or equal to second reset time;

when a third test instruction is received, whether the first input switch 111 is closed or not is confirmed, if yes, the third output switch 133 is controlled to be synchronously closed, timing is started when the first input switch 111 is detected to reset, the control switch 112 is closed after delay time, and the sampling ST voltage is greater than or equal to a voltage threshold value, and the third output switch 133 is controlled to reset when a timing value is greater than or equal to third resetting time;

when a fourth test instruction is received, whether the second input switch 113 is switched to the first level combination is determined, if yes, the fourth output switch 134 is controlled to be closed, and the fourth output switch 134 is controlled to be reset until the second input switch 113 is switched to the second level combination.

In this embodiment, a corresponding test instruction may be input according to a test requirement to adjust a corresponding input parameter, and the control module 12 performs logic judgment on the set input parameter according to the currently received test instruction and then controls a working state of a corresponding output switch, so as to implement analog output of a corresponding trip signal, and further perform validity verification on a transmission loop of the optical fiber interface device and a reception loop of the protection device through the trip signal, as shown in fig. 3, in a specific implementation, the working state switching diagram of the input module 11 exemplarily shows actions of the input module 11 and the output module 13 under three different test instructions.

When a first test instruction of single-position unconditional output is received, at this time, the first input switch 111, namely the switch K, is switched to a closed state and the first reset time t is set, so that the control module 12 controls the first output switch 131 (the switches KM1 to KM 4) to perform real-time extended output after confirming that the switch K is switched on, namely, the switches KM1 to KM4 are synchronously switched on, and reset is performed after keeping the first reset time t, and a first trip signal is output;

when a second test instruction of unit self-holding output is received, at this time, the first input switch 111, that is, the switch K, should be switched to a closed state and the second reset time t1 is set, so that the control module 12 controls the second output switch 132 (the switch KM 5) to perform extended output after confirming that the switch K is switched on, that is, the switch KM5 is switched on synchronously, and starts to perform timing when the switch K is reset, controls the switch KM5 to perform reset when the timing value is greater than or equal to the second reset time t1, outputs a second trip signal, that is, the switch KM5 is self-held and reset after a certain time (the second reset time t 1) after the switch K is reset, and of course, can also perform manual reset when the timing value is less than the second reset time t1 according to actual requirements;

when a third test instruction with a reset condition self-holding output at a single position is received, at this time, the first input switch 111K should be switched to a closed state and the switch ST is switched to the closed state in a delayed manner, and a third reset time t2 and a voltage threshold (vthreshold) are also set, so that the control module 12 controls the third output switch 133 (switch KM 6) to perform extended output after confirming that the switch K is switched on, that is, the switch KM6 is synchronously switched on, further detects whether the switch ST is switched on and whether the sampled voltage Vs is greater than or equal to the voltage threshold after the switch K is reset, starts timing only when the switch ST is switched on and the sampled voltage Vs is greater than or equal to the voltage threshold after the switch K is reset, and controls the switch KM6 to reset when the timing value is greater than or equal to the third reset time t2, and outputs a third trip signal;

when a fourth test instruction expanded by the two-position relay J1 is received, at this time, the second input switch 113 includes a switch K1 and a switch K2 which are switched to a preset level combination, specifically, when the control module 12 confirms that the switch K1 and the switch K are switched to the first level combination, the fourth output switch 134 (the switches KM7 to KM 9) is controlled to be switched on and output, the switch-on state is maintained until the control module 12 detects that the switch K1 and the switch K are switched to the second level combination, the switches KM7 to KM9 are controlled to be reset, and a fourth trip signal is output, specifically, the first level combination is the switch K1 set 1 and the switch K2 set 0, and the second level combination is the switch K1 set 0 and the switch K2 set 1, or the switch K1 set 1 and the switch K2 set 1. Therefore, in the embodiment, by flexibly inputting test instructions under different conditions and setting corresponding input parameters, the extended output state of the output switch can be controlled after the input parameters are logically judged, so that tripping signals under different test scenes can be simulated, the test requirements on the effectiveness of the bypass route-replacing transceiving loop under different conditions can be met, and the reliability of the bypass route-replacing channel switching can be improved.

In one embodiment, as shown in fig. 4, the sampling module 14 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a first inductor L1, a second inductor L2, an optical coupler U1, and a first operational amplifier a 1;

one end of the first resistor R1 is connected to the voltage input terminal V1, and the other end of the first resistor R1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 through the second resistor R2; the other end of the third resistor R3 is grounded; the other end of the fourth resistor R4 is connected with the 2 nd pin of the optocoupler U1 and one end of the second capacitor C2; one end of a fifth resistor R5 is connected with a pin 7 of the optocoupler U1 and one end of a third capacitor C3, and the other end of the fifth resistor R5 is connected with the non-inverting input end of the first operational amplifier A1, one end of a seventh resistor R7 and one end of an eighth resistor R8; one end of a sixth resistor R6 is connected with the 6 th pin of the optocoupler U1 and one end of a fourth capacitor C4, and the other end of the sixth resistor R6 is connected with the inverting input end of the first operational amplifier A1, one end of a sixth capacitor C6, one end of a ninth resistor R9 and one end of a tenth resistor R10; the other end of the seventh resistor R7 is grounded; the other end of the eighth resistor R8 is connected with a reference signal end VREF 2.5; the other end of the ninth resistor R9 is connected with the other end of the sixth capacitor C6, the other end of the tenth resistor R10, one end of the eleventh resistor R11 and the output end of the first operational amplifier A1; the other end of the eleventh resistor R11 is connected with the sampling voltage output end AD-U1 and one end of the ninth capacitor C9; one end of a first capacitor C1 is connected with a1 st pin of the optocoupler U1 and a first power supply end VCC4.5V, and the other end of the first capacitor C1, the other end of the second capacitor C2, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are all grounded; one end of a fifth capacitor C5 is connected with the 8 th pin of the optocoupler U1 and one end of the first inductor L1, and the other end of the fifth capacitor C5 is grounded; the positive electrode of the seventh capacitor C7 is connected to the positive power supply end of the first operational amplifier a1, one end of the eighth capacitor C8 and one end of the second inductor L2, and the negative electrode of the seventh capacitor C7 is connected to the other end of the eighth capacitor C8 and the ground; the other end of the ninth capacitor C9 is grounded; the other end of the first inductor L1 is connected with a second power supply terminal VCC + 5V; the other end of the second inductor L2 is connected to a third power supply terminal VCC 3.3.

In this embodiment, the sampling module 14 samples the input voltage in the loop, so that when a third test command is detected, the sampled sampling voltage Vs can be compared with a set voltage threshold, and the control module 12 controls the switch KM6 for extended output, specifically, when the sampling module 14 shown in fig. 4 is an adder, the sampling module 14 collects voltages at two ends of V1-Gnd, and isolates and amplifies a voltage signal about 8 times through the AMC1200 opto-coupler U1, the seventh resistor R7 plays a role of raising the voltage, so that the sampling range of the sampling module 14 is-2.5V- +2.5V, the collected voltage passes through the first operational amplifier a1 and is amplified (R9// R10)/R6 times (specifically, the amplification may be set according to actual requirements, for example, the amplification is 1 time, etc.), the amplified signal is filtered through the RC filter circuit, and the obtained sampling voltage signal of the AD-U1 is output to the control module 12, so that accurate voltage sampling is realized.

In one embodiment, as shown in fig. 5, the delay module 15 includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a tenth capacitor C10, a second operational amplifier a2, a diode D1, and a relay J1;

one end of the twelfth resistor R12 is connected with the cathode of the diode D1, the second power supply end and the first connection end of the thirteenth resistor R13, and the other end of the twelfth resistor R12 is connected with the anode of the diode D1, one end of the tenth capacitor C10 and the non-inverting input end of the second operational amplifier A2; a second connection end of the thirteenth resistor R13 is grounded, and a control end of the thirteenth resistor R13 is connected with the inverting input end of the second operational amplifier A2; one end of a fourteenth resistor R14 is connected with the output end of the second operational amplifier A2, and the other end of the fourteenth resistor R14 is connected with the coil anode of the relay J1; one end of a fifteenth resistor R15 is connected with the normally open end of the relay J1, and the other end of the fifteenth resistor R15 is connected with the coil cathode of the relay J1, the cathode of a voltage source and the ground; the common end of the coil is connected with the anode of the voltage source, and the other end of the tenth capacitor C10 is grounded.

In this embodiment, the delay module 15 may control a part of loops that need delayed output, for example, when receiving a fourth test command, may delay a closing time of the switch ST and/or a time when the sampling module 14 starts to sample voltage, so that the switch ST is closed again within a certain time after the switch K is reset and the sampled voltage is judged to be large, thereby realizing trip signal output control of more input conditions, specifically, in the delay module 15, taking delayed voltage sampling as an example, the twelfth resistor R12 and the tenth capacitor C10 form an RC charging circuit, the tenth capacitor C10 enters a charging state at the moment of the switch K, when a voltage at the non-inverting input end of the second operational amplifier a2 (i.e., a voltage at two ends of the tenth capacitor C10) is greater than a voltage at the inverting input end (determined by the adjustable resistor thirteenth resistor R13, the voltage at the inverting input end may be changed by adjusting a resistance value of the thirteenth resistor R13, thereby changing the length of the delay time), at this time, the output state of the second operational amplifier a2 changes, namely changes from low level to high level, at this time, the current flows through the coil of the relay J1, the switch of the relay J1 is attracted, at this time, the sampling loop can sample the input voltage and compare and judge with the set voltage threshold, when the voltage threshold is more than or equal to, the loop of the extended output is conducted, and the delay output control is realized.

It can be known from the above embodiments that the bypass substitute path switching validity detection circuit provided by the present invention controls the working state of the output module by the logical judgment result of the input switch state and the time parameter to output a corresponding trip signal in a simulation manner, verifies the transceiving indication of the optical fiber interface device and the protection device in the bypass substitute path, realizes an efficient and convenient bypass substitute path switching validity test, and improves the reliability of bypass substitute path switching.

Another embodiment of the present invention provides a method for detecting validity of bypass routing channel switching, as shown in fig. 6, the method includes the following steps:

s100, when a bypass is used for routing, the input module switches corresponding switch states and time parameters according to the received test instruction;

s200, the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result;

and S300, the output module simulates and outputs a tripping signal in the bypass route to verify the receiving input quantity of the transmitting indicator light and the protection device of the optical fiber interface device.

For a detailed implementation, please refer to the corresponding product embodiments, which are not described herein again. It should be noted that, a certain sequence does not necessarily exist between the above steps, and those skilled in the art can understand, according to the description of the embodiments of the present invention, that in different embodiments, the above steps may have different execution sequences, that is, may also be executed in parallel, may also be executed interchangeably, and the like.

Another embodiment of the present invention provides a bypass proxy channel switch validity detection apparatus, the apparatus comprising a housing, the shell is internally provided with a PCB board which is provided with the bypass substitute path switching validity detection circuit, the bypass substitute path switching validity detection device is connected into the protection transceiving loop, provides a logic judgment result of the input switch state and the time parameter to control the working state of the output module so as to simulate and output a corresponding trip signal, the receiving and sending instructions of the optical fiber interface device and the protection device in the bypass substitute path are verified, the high-efficiency and convenient bypass substitute path switching effectiveness test is realized, the reliability of the bypass substitute path switching is improved, since the bypass proxy channel switching validity detection circuit has been described in detail above, it is not described in detail here.

In summary, the bypass substitute path switching validity detection circuit, apparatus and method disclosed in the present invention includes a boost conversion module, an inversion control module and an inversion output module; when the bypass is used for routing, the input module switches corresponding switch states and time parameters according to the received test instruction; the control module carries out logic judgment on the switch state and the time parameter according to the test instruction and controls the output module to be switched to a corresponding working state based on a logic judgment result; the output module simulates and outputs a tripping signal in the bypass path to verify the receiving input of the transmitting indicator light of the optical fiber interface device and the protection device. The working state of the output module is controlled through the logic judgment result of the input switch state and the time parameter so as to output a corresponding tripping signal in a simulation mode, the transceiving indication of the optical fiber interface device and the protection device in the bypass route replacement is verified, the efficient and convenient bypass route replacement switching effectiveness test is realized, and the reliability of bypass route replacement switching is improved.

Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by instructing relevant hardware (such as a processor, a controller, etc.) through a computer program, which may be stored in a non-volatile computer-readable storage medium, and the computer program may include the processes of the above method embodiments when executed. The storage medium may be a memory, a magnetic disk, a floppy disk, a flash memory, an optical memory, etc.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.