阅读说明：本技术 储存装置、存储器件及操作该存储器件的方法 (Storage device, memory device and method of operating the memory device ) 是由 成镇溶 李俊相 于 2019-02-22 设计创作，主要内容包括：储存装置、存储器件及操作该存储器件的方法。在具有改进的数据接收速率的储存装置中,所述储存装置包括：多个存储器件,所述多个存储器件各自包括多个选择信号焊盘；以及存储控制器,所述存储控制器用于通过所述多个选择信号焊盘提供表示所述多个存储器件中的被选存储器件的多个选择信号,其中,所述多个选择信号中的一些选择信号包括指示由所述存储控制器控制的所述多个存储器件的数量的层叠信息。(A memory device, a memory device and a method of operating the memory device are provided. In a storage device having an improved data reception rate, the storage device comprising: a plurality of memory devices each including a plurality of selection signal pads; and a memory controller for providing a plurality of selection signals representing selected ones of the plurality of memory devices through the plurality of selection signal pads, wherein some of the plurality of selection signals include stacking information indicating a number of the plurality of memory devices controlled by the memory controller.)

1. A storage device, the storage device comprising:

a plurality of memory devices each including a plurality of selection signal pads; and

a memory controller configured to provide a plurality of select signals representing selected ones of the plurality of memory devices through the plurality of select signal pads,

wherein some of the plurality of select signals include tier information indicating a number of the plurality of memory devices controlled by the memory controller.

2. The storage device of claim 1, wherein the selected memory device comprises:

a delay tuning circuit configured to generate a delay tuning signal for determining a delay amount to be applied to a data signal provided from the memory controller based on the stack information; and

a data tuner configured to delay the data signal according to the delay tuning signal.

3. The storage device according to claim 2, wherein the number indicated by the stack information is any one of eight, four, and two.

4. The storage apparatus according to claim 2, wherein the delay tuning circuit generates the delay tuning signal in such a manner that a larger number of the plurality of memory devices indicated by the stack information decreases a delay amount determined by the delay tuning signal.

5. The storage device as set forth in claim 1,

wherein the plurality of selection signals include first to sixth selection signals, and

wherein the first to third selection signals among the first to sixth selection signals respectively identify the plurality of memory devices.

6. The storage device according to claim 5, wherein fourth to sixth selection signals of the first to sixth selection signals include the stack information.

7. The storage device of claim 2, wherein the delay tuning circuit comprises:

an input signal generator configured to generate internal control signals according to the delay tuning command and the select signals provided by the memory controller;

a delay tuning signal generator configured to generate different stack register signals according to different numbers of memory devices in response to the internal control signal; and

a delay tuning signal output component configured to output the delay tuning signal based on the stack register signal and the delay tuning command.

8. A memory device, the memory device comprising:

a plurality of selection signal pads configured to receive a plurality of selection signals, respectively;

a plurality of data signal pads configured to receive a data signal;

a delay tuning circuit in communication with the plurality of select signal pads and the plurality of data signal pads, the delay tuning circuit configured to determine an amount of delay to be applied to the data signal as a function of some of the plurality of select signals; and

a data storage configured to generate a tuned data signal by applying the determined delay amount to the data signal and to store the tuned data signal according to a reference clock.

9. The memory device of claim 8, further comprising an input driver configured to receive the data signal input through the plurality of data signal pads.

10. The memory device of claim 9, wherein the input driver generates the internal data signal having a high state or a low state based on a comparison of the data signal to a reference voltage.

11. The memory device of claim 10, wherein the delay tuning circuit generates a delay tuning signal for determining the delay amount based on stack information represented by the select signals.

12. The memory device of claim 11, wherein the tier information indicates a number of memory devices commonly coupled to the plurality of data signal pads.

13. The memory device of claim 12, wherein the delay tuning circuit generates the delay tuning signal in such a manner that a greater number of memory devices coupled in common to the plurality of data signal pads results in a smaller delay amount determined by the delay tuning signal.

14. The memory device of claim 13, further comprising a data tuner configured to delay the internal data signal in response to the delay tuning signal.

15. A method for operating a memory device having a plurality of select signal pads and a plurality of data signal pads, said method comprising the steps of:

receiving a delay tuning command from a memory controller;

acquiring stack information from some of a plurality of selection signals input through the plurality of selection signal pads in response to the delay tuning command; and

generating a delay tuning signal for determining a delay amount to be applied to a data signal input through the plurality of data signal pads according to the stack information.

16. The method of claim 15, wherein the tier information indicates a number of memory devices commonly coupled to the plurality of data signal pads.

17. The method of claim 16, wherein the delay tuning signal is generated in such a way that the greater the number of memory devices commonly coupled to the plurality of data signal pads, the smaller the delay amount determined by the delay tuning signal.

18. The method of claim 15, wherein the first and second light sources are selected from the group consisting of,

wherein the plurality of selection signals include first to sixth selection signals, and

wherein the first to third selection signals among the first to sixth selection signals respectively identify a plurality of memory devices.

19. The method of claim 18, wherein fourth through sixth selection signals of the first through sixth selection signals include the stack information.

20. The method of claim 15, further comprising the steps of:

the data signal is delayed by the determined delay amount and the delayed data signal is stored.

Technical Field

The present disclosure relates generally to electronic devices, and more particularly, to a storage device and an operating method of the storage device.

Background

The storage device stores data under the control of a host device such as a computer, smart phone, or smart tablet. Examples of the storage device include a Hard Disk Drive (HDD), and a Solid State Drive (SSD) or a memory card.

The storage device may include a memory device for storing data and a memory controller for controlling the memory device. The memory device may be a volatile memory device or a nonvolatile memory device. Examples of non-volatile storage devices include read-only memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable and programmable ROM (eeprom), flash memory, phase-change ram (pram), magnetic ram (mram), resistive ram (rram), ferroelectric ram (fram), and the like.

Disclosure of Invention

Drawings

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, the elements and features of the invention may be configured or arranged in a manner different from that disclosed herein. Accordingly, the present invention is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. It should also be noted that throughout the specification, references to "an embodiment," "another embodiment," and so forth, are not necessarily to one embodiment only, and different references to any such phrase are not necessarily to the same embodiment.

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

FIG. 1 is a block diagram illustrating an exemplary storage device.

Fig. 2 is a diagram illustrating signals input to and output from the memory device in fig. 1.

Fig. 3 is a diagram illustrating a phenomenon occurring when the number of memory devices in a storage apparatus increases.

Fig. 4 is a diagram illustrating a coupling relationship between a memory controller and a memory device.

Fig. 5 is a diagram illustrating selection signals input to a plurality of selection signal pads described with reference to fig. 4.

Fig. 6 is a graph illustrating a delay amount to be applied according to an embodiment of the present disclosure.

Fig. 7 is a block diagram illustrating a configuration of the control logic of fig. 4.

Fig. 8 is a circuit diagram illustrating the delay tuning circuit in fig. 7.

Fig. 9 is a diagram illustrating a delay tuning signal generated by the delay tuning circuit in fig. 8 according to an embodiment of the present disclosure.

Fig. 10 is a circuit diagram illustrating a configuration of the data tuner in fig. 7.

FIG. 11 is a flow chart illustrating operation of a storage controller according to an embodiment of the present disclosure.

Fig. 12 is a flowchart illustrating an operation of a memory device according to an embodiment of the present disclosure.

Fig. 13 is a flowchart illustrating an operation of a storage device according to an embodiment of the present disclosure.

Fig. 14 is a diagram illustrating an exemplary structure of the memory device of fig. 1.

Fig. 15 is a diagram illustrating an embodiment of the memory cell array in fig. 14.

Fig. 16 is a circuit diagram illustrating any one of the memory blocks of fig. 15.

Fig. 17 is a circuit diagram illustrating another embodiment of any one of the memory blocks of fig. 15.

Fig. 18 is a diagram illustrating another embodiment of the memory controller in fig. 1.

Fig. 19 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 20 is a block diagram exemplarily illustrating a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 21 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

Embodiments provide a storage device having an improved data reception rate and an operating method thereof.

According to an aspect of the present disclosure, there is provided a storage device including: a plurality of memory devices each including a plurality of selection signal pads; and a memory controller configured to provide a plurality of selection signals representing selected ones of the plurality of memory devices through the plurality of selection signal pads, wherein some of the plurality of selection signals include stacking information indicating a number of the plurality of memory devices controlled by the memory controller.

According to another aspect of the present disclosure, there is provided a memory device including: a plurality of selection signal pads configured to receive a plurality of selection signals, respectively; a plurality of data signal pads configured to receive a data signal; a delay tuning circuit in communication with the plurality of select signal pads and the plurality of data signal pads, the delay tuning circuit configured to determine an amount of delay to be applied to the data signal as a function of some of the plurality of select signals; and a data storage configured to generate a tuned data signal by applying the determined delay amount to the data signal and store the tuned data signal according to a reference clock.

According to yet another aspect of the present disclosure, there is provided a method for operating a memory device having a plurality of selection signal pads and a plurality of data signal pads, the method including the steps of: receiving a delay tuning command from a memory controller; acquiring stack information from some of a plurality of selection signals input through the plurality of selection signal pads in response to the delay tuning command; and generating a delay tuning signal for determining a delay amount to be applied to the data signal input through the plurality of data signal pads according to the stack information.

According to still another aspect of the present disclosure, there is provided a memory device including: a memory cell array and peripheral circuitry configured to receive data signals from a controller coupled to the memory device; a delay tuning circuit configured to provide information indicative of a number of memory devices coupled to the controller; and a data tuner configured to delay the data signal by a determined amount according to the information such that the determined amount is inversely proportional to the number, wherein the peripheral circuit is further configured to store the delayed data signal in the memory cell array.