Test method for write half-select fault of low-voltage SRAM (static random Access memory)
阅读说明：本技术 一种低电压sram写半选择故障的测试方法 (Test method for write half-select fault of low-voltage SRAM (static random Access memory) ) 是由 吕凯 蔡志匡 刘世欢 王荧 周正 胡善文 王子轩 郭宇锋 于 2019-10-09 设计创作，主要内容包括：一种低电压SRAM写半选择故障的测试方法,设计出写半选择故障测试元素：{?W0?W1column0?R1column0?R0column0’?W0?W1column1?R1column1?R0column0’},其中{W1column0}和{W1column1}利用自定义行读写方式,即一种对指定范围的行地址进行有序的读写操作方式,将数据背景写入列地址相同、行地址顺序增加的存储单元,激活敏化出故障,随后进行读操作,将读出数据与期望数据比较,不一致则判断检测出故障。该方法能够弥补传统算法无法覆盖写半选择故障的问题,实现指定故障模型的覆盖,且有效地降低了测试成本。(A test method for write half-select faults of a low-voltage SRAM (static random access memory) designs write half-select fault test elements: { ⇕ W0 ⇕ W1column0 ⇕ R1column0 ⇕ R0column0'⇕ W0 ⇕ W1column1 ⇕ R1column1 ⇕ R0column0' }, wherein { W1column0} and { W1column1} utilize a custom row read-write mode, namely, a mode of performing ordered read-write operation on row addresses in a specified range, write data backgrounds into memory cells with the same column addresses and increasing row address sequences, activate and sensitize faults, then perform read operation, compare the read data with expected data, and judge and detect faults if the read data is inconsistent. The method can solve the problem that the traditional algorithm cannot cover the half-selection fault, realizes the coverage of the specified fault model, and effectively reduces the test cost.)
1. A test method for write half-select failure of a low-voltage SRAM is characterized by comprising the following steps: the method comprises the following steps:
step 1, establishing a write half-select fault model;
step 2, writing a design of a half-selection fault test element;
step 2-1, activating and sensitizing;
step 2-2, identifying whether the fault exists or not;
2-3, selecting whether the unit has a write half selection problem;
step 2-4, according to the analysis of the steps, designing the following write half-select fault test elements:
wherein, S1-8 is the write half selection fault step using the test element;
s1: the initialization is all 0, and aiming at the current mainstream low-voltage SRAM structure, although the write half-selection fault can be activated and sensitized in the initialization process, the write half-selection fault is continuously iterated and replaced, so that all the half-selection units are set to be 0 finally, and the step only plays the role of initialization;
s2: performing write 1 operation on all addresses in a first column of the storage array, and activating and sensitizing write half-selection faults existing in other half-selection units except for the unit of the currently selected column in the low-voltage SRAM;
s3: performing 1 reading operation on all addresses in a first column of a storage array, and detecting whether 1 writing is correct or not;
s4: performing 0 reading operation on all addresses outside a first column of the storage array, and detecting whether the values of storage units of corresponding addresses are overturned, namely whether units with write half-select faults exist;
s5: initializing all 0 s again;
s6: performing write 1 operation on all addresses of the second row, activating and sensitizing write half selection faults existing in other half selection units except the unit of the currently selected row in the low-voltage SRAM, and mainly testing whether the first row of the storage array has the write half selection faults or not at this time;
s7: performing a read 1 operation on all addresses in the second column of the storage array, and detecting whether the write 1 operation of S6 is correct;
s8: and (3) performing 0 reading operation on all the addresses except the second column, and detecting whether the values of the storage units of the corresponding addresses are inverted or not, namely whether units with write half selection faults exist or not.
2. The method for testing the write half select failure of the low-voltage SRAM as claimed in claim 1, wherein: in the step 1, a write half selection fault model is established, namely, firstly, a write half selection problem caused by increasingly serious parameter fluctuation of an advanced process is mapped to a problem caused by an electrical parameter, and then, the electrical problem is abstracted and logically established into a logic model so as to facilitate subsequent algorithm development.
3. The method for testing the write half select failure of the low-voltage SRAM as claimed in claim 1, wherein: in the step 2-1, for the whole piece of SRAM test, write operation is performed on a whole column of cells at the same time, so that the step of activating the sensitized write half-select fault is covered to other columns of memory cells except for the selected column.
4. The method for testing the write half select failure of the low-voltage SRAM as claimed in claim 1, wherein: in the step 2-2, after the sensitization process is activated, the response value of the whole piece of SRAM is read, and then the expected response is compared to analyze whether the write half select fault exists or not, so that the test sequence of the expected response needs to be read.
5. The method for testing the write half select failure of the low-voltage SRAM as claimed in claim 1, wherein: in the step 2-3, considering that the selection unit also has the problem of half-write selection, the test sequence for activating sensitization needs to be reused, but the second use needs to replace the selection unit, and the object of the selection unit is replaced by all the units in the other column.
6. The method for testing the write half select failure of the low-voltage SRAM as claimed in claim 1, wherein: in the step 2-4, the test time is 4N +2R, N is the number of all the cells of the memory array, and R is the number of rows of the memory array.
Technical Field
The invention belongs to the field of integrated circuit testing, and particularly relates to a method for testing a write half-select fault of a low-voltage SRAM.
Background
The rapid development of artificial intelligence and the internet of things drives a new generation of automotive electronics, smart homes, industrial manufacturing and the like, the demand for high-performance and low-power consumption chips is continuously increased, the demand for memories is also higher, the area of the memories on the chips reaches more than 70%, and the proportion is increased. Because the requirements for high performance and low power consumption are drawn, information needs to be stored nearby a CPU (central processing unit), namely a memory needs to be embedded in the same chip position with the CPU, the memory which can maximally match the high performance and the low power consumption of the CPU can only be an SRAM (static random access memory), the read-write speed of the SRAM is high, the SRAM is often used as a cache and the like, the unique application of the SRAM is widely applied to various occasions, and the influence of the performance and the power consumption on the whole chip is very important.
In order to meet different application scenarios, the low power consumption requirement of the SRAM becomes a research hotspot in the industry, wherein the most direct and effective low power consumption design method is to reduce the working voltage. With the continuous development of the manufacturing process, the process parameter fluctuation is more serious under the low-voltage working environment, the stability of the manufactured SRAM is poorer and poorer, in order to solve the problem, the write stability and the read-write speed can be improved through a word line enhancement technology in design, and the problem brought about is that the half-selection unit is caused to have a fault. The write half select problem refers to a half-strobe phenomenon that the activation of a word line causes other memory cells in the same row to be turned on during a write operation performed on a certain memory cell. However, with the development of the process, the working voltage of the SRAM is continuously reduced, and the capacity of the half-selected cell to maintain the stored value is weaker, so that the half-selected cell is more and more serious, which causes the reduction of the cell stability and certain power consumption waste. At present, under a low-voltage working environment, the problem of write half selection of a 6T/8T SRAM is more serious due to continuous and serious process fluctuation under an advanced process band, but a traditional test algorithm cannot meet the detection of the write half selection problem, and it is very important to explore a test method capable of covering the write half selection problem.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method capable of detecting the write half selection problem. The method can solve the problem that the traditional algorithm cannot cover the half-selection fault, realizes the coverage of the specified fault model, and effectively reduces the test cost.
A test method for write half-select failure of a low-voltage SRAM comprises the following steps:
step 2, writing a design of a half-selection fault test element;
step 2-1, activating and sensitizing;
step 2-2, identifying whether the fault exists or not;
2-3, selecting whether the unit has a write half selection problem;
step 2-4, according to the analysis of the steps, designing the following write half-select fault test elements:
wherein, S1-8 is the write half selection fault step using the test element;
s1: the initialization is all 0, and aiming at the current mainstream low-voltage SRAM structure, although the write half-selection fault can be activated and sensitized in the initialization process, the write half-selection fault is continuously iterated and replaced, so that all the half-selection units are set to be 0 finally, and the step only plays the role of initialization;
s2: performing write 1 operation on all addresses in a first column of the storage array, and activating and sensitizing write half-selection faults existing in other half-selection units except for the unit of the currently selected column in the low-voltage SRAM;
s3: performing 1 reading operation on all addresses in a first column of a storage array, and detecting whether 1 writing is correct or not;
s4: performing 0 reading operation on all addresses outside a first column of the storage array, and detecting whether the values of storage units of corresponding addresses are overturned, namely whether units with write half-select faults exist;
s5: initializing all 0 s again;
s6: performing write 1 operation on all addresses of the second row, activating and sensitizing write half selection faults existing in other half selection units except the unit of the currently selected row in the low-voltage SRAM, and mainly testing whether the first row of the storage array has the write half selection faults or not at this time;
s7: performing a
s8: and (3) performing 0 reading operation on all the addresses except the second column, and detecting whether the values of the storage units of the corresponding addresses are inverted or not, namely whether units with write half selection faults exist or not.
Further, in the
Further, in the step 2-1, for the whole piece of SRAM test, writing operation is performed on a whole column of cells at the same time, so that the step of activating the sensitized write half-select fault is covered to other columns of memory cells except for the selected column.
Further, in step 2-2, after the sensitization process is activated, the response value of the whole SRAM is read, and then compared with the expected response, whether the write half select fault exists or not is analyzed, so that a test sequence of the expected response needs to be read.
Furthermore, in the step 2-3, considering that the selection unit also has the problem of half-write selection, the test sequence for activating sensitization needs to be reused, but the second use needs to replace the selection unit, and the object of the selection unit is replaced by all the units in the other column.
Further, in step 2-4, the test time is 4N +2R, N is the number of all cells in the memory array, and R is the number of rows in the memory array.
The invention achieves the following beneficial effects: the method can solve the problem that the traditional algorithm cannot cover the half-selection fault, realizes the coverage of the specified fault model, and effectively reduces the test cost.
Drawings
Fig. 1 is a schematic flow chart illustrating an implementation process of a method for testing a write half select failure of a low-voltage SRAM in an embodiment of the present invention.
FIG. 2 is a schematic diagram of the mechanism of the write half select problem in an embodiment of the present invention.
FIG. 3 is a schematic diagram of a write half select fault occurring in an embodiment of the present invention.
FIG. 4 is a schematic diagram of the top-level circuit of the MBIST in the embodiment of the present invention.
FIG. 5 is a schematic diagram of the work flow of an address generator in an embodiment of the invention.
Fig. 6 is a schematic diagram of the work flow of the data generator in the embodiment of the invention.
FIG. 7 is a functional waveform diagram of a test element writing a half-select fault in an embodiment of the invention.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the drawings in the specification.
The invention provides a targeted test method for write half-select faults of a low-voltage SRAM (static random access memory), aiming at the problem that the half-select problem of the 6T/8T low-voltage SRAM is more serious due to continuous and serious process fluctuation under an advanced process, but the current traditional test algorithm cannot meet the detection of the write half-select problem, and the steps shown in FIG. 1 comprise:
The write half select problem refers to a half-strobe phenomenon that the word line is active during a write operation to a certain memory cell, causing other memory cells in the same row to appear. As shown in fig. 2, when WL is turned on, the pull-down tube and the gate tube on the side of the internal "0" node Q of the half-selected cell are communicated with the leakage path between the floating BL, and the charge on the bit line is injected in large quantity to cause the potential at the point Q to rise; if the potential of the point Q is raised to the turning point of the storage unit, the stored value of the internal node of the half-selection unit is turned over, and damage is caused, namely the half-selection unit goes wrong.
The write half selection occurs due to the increasingly severe parameter fluctuations of advanced processes and low voltage operating environments. The method mainly comprises two steps, wherein the first step is to map the write half selection problem caused by the increasingly serious parameter fluctuation of the advanced process to the problem caused by the electrical parameter, and the second step is to abstract and logically establish the electrical problem into a logic model so as to facilitate the subsequent algorithm development. From the research on the mechanism of the occurrence of the write half selection problem, it is found that the cause of the occurrence of the write half selection problem is that the storage value of the half selection unit may be inverted due to the large current of the bit line of the half selection unit and the raising of the potential of the storage node. According to the stored value inversion, the mapping of the half-selection problem to the logic level can abstract the write half-selection fault, that is, when the selection unit performs write operation, the stored value of the same row of half-selection units undergoes the 0-to-1 (1-to-0) inversion dynamic process. Fig. 3 is a process of simulating the occurrence of a write half select fault in the logic layer, and it is assumed that the red cell is a full select cell and the yellow cell is a cell having an error problem in the half select cell.
And 2, writing a design of the half-selection fault test element.
And 2-1, activating and sensitizing.
Based on the mechanism analysis and the abstract logic modeling process of the write half selection problem, the write half selection problem which possibly occurs in the set of the upper half selection unit at the position of the row corresponding to the selection unit can be activated and sensitized by writing the selection unit. The write half-select fail test sequence therefore needs to include a write operation to the selected cell. For an entire SRAM test, it is necessary to write to an entire column of cells at the same time, so that the step of activating the sensitized write half select fault is overlaid to the other columns of memory cells except the selected column.
And 2-2, identifying whether the fault exists or not.
After the sensitization process is activated, the response value of the whole piece of SRAM needs to be read, and then the expected response is compared to analyze whether the write half select fault exists or not, so that the test sequence of the expected response needs to be read.
And 2-3, selecting whether the unit has a write half selection problem.
Considering that the selection unit also has the problem of write half selection, the test sequence for activating sensitization needs to be reused, but the second use needs to replace the selection unit, and the object of the selection unit is replaced by all the units in the other column.
And 2-4, designing the following write half-select fault test elements by the analysis:
wherein S1-8 is a write half select fail step using the test elements described above in sequence.
S1: the initialization is all 0, and for the current mainstream low-voltage SRAM structure, although the write half-select fault can be activated and sensitized in the initialization process, the write operation is continuously iterated, so that all the half-select units are set to be 0 finally, and the step only plays the role of initialization.
S2: and performing
S3: and performing 1 reading operation on all addresses in the first column of the memory array, and detecting whether 1 writing is correct.
S4: and performing 0 reading operation on all addresses outside the first column of the storage array, and detecting whether the values of the storage units of the corresponding addresses are inverted or not, namely whether units with write half selection faults exist or not.
S5: all 0 s are initialized again.
S6: and performing
S7: a
S8: and (3) performing 0 reading operation on all the addresses except the second column, and detecting whether the values of the storage units of the corresponding addresses are inverted or not, namely whether units with write half selection faults exist or not.
The test time is 4N +2R, N is the number of all the cells of the storage array, R is the number of rows of the storage array, the method activates the sensitization write half-select fault, the selection is to carry out 0W1 operation on the specified two columns of cells, and the rest 0W0, 1W1 and 1W0 are all feasible.
The feasibility and effectiveness verification of the low-voltage SRAM write half-select fault test method includes firstly designing a BIST circuit based on write half-select fault test elements, and then carrying out functional verification of the method.
The method comprises the steps of based on BIST circuit design of write half-selection fault test elements, writing data backgrounds into storage units with the same column addresses and the increased row addresses in sequence in a self-defined row read-write mode, activating and sensitizing faults, then conducting read operation, comparing read data with expected data, and judging whether the read data is inconsistent with the expected data to detect the faults. The self-defined row read-write mode is a mode of orderly read-write operation of row addresses in a specified range, and address switching can be realized by state switching in a controller. Fig. 4 is a designed top-level MBIST circuit diagram, which mainly includes two modules: BIST Controller and BIST Collar. The BISTController is a systematic test controller based on a finite-state machine, and comprises an address generator (a specific work flow schematic diagram is shown in FIG. 5), a data generator (a specific work flow schematic diagram is shown in FIG. 6) and the like, wherein the state machine is solidified based on an algorithm, and each state is distributed according to each step in a write half-select fault test element, so that the whole MBIST test process can be controlled to be reasonably carried out. The BIST Collar mainly comprises an SRAM circuit and a bypass circuit. The bypass circuit is a bypass circuit mainly based on a multiplexer and is used for switching input data sources, such as the input from a BISTController or a system; and the other is to facilitate other types of tests, such as scan tests.
The method function verifies that the selected verification object is a low-voltage 6T SRAM (capacity: 16x32), and the row address and the column address of the selected verification object are all 4. FIG. 7 is a waveform diagram illustrating a verify write half-select fail test element. test _ ADA represents the address data that the address generator in the MBIST controller supplies to the SRAM address terminal, and test _ DBIN represents the background data that the data generator in the MBIST controller supplies to the SRAM data terminal. test _ CENA, read enable signal, active low; test _ CENB is a write enable signal, active low, that varies with the course of the test algorithm. The fail _ h signal is a test result signal, and transitions to 1 if no test error persists to 0 and if an error occurs. tst _ done is a test end signal, and the test end jump becomes "1".
Test procedure referring to fig. 7, wherein fig. 7(a) shows the first four steps of the test element: { W0W1column0R1column0R0column0’}. Red is the initialization phase and the test procedure is not affected. From the test _ ADA signal, the address change is seen, first the full address is incremented, then only the first column address is selected to increment, repeating twice, then the addresses other than the first column address are selected to increment in order. the test _ DBIN signal data signal transitions from 0 to ffff _ ffff and then from ffff _ ffff to 0. It can be seen that the address, write data and expected data can all match, representing W0W1 in the algorithmcolumn0R1column0R0column0’And realizing successfully. FIG. 7(b) shows the last four steps of the test element: { W0W1column1R1column1R0column1’Can be seen as W0W1 in the algorithmcolumn1R1column1R0column1’And realizing successfully.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.
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