阅读说明：本技术 软误差恢复锁存器 (Soft error recovery latch ) 是由 A·M·韦杰蒂 A·亚恩 于 2019-06-26 设计创作，主要内容包括：本公开的实施例涉及软误差恢复锁存器。提供了一种锁存器。锁存器包括多个存储节点,包括被配置为存储具有两个状态中的一个存储状态的数据位的多个数据存储节点、以及被配置为存储数据位的补码的多个互补数据存储节点。锁存器包括分别对应于多个存储节点的多个电源电压多依赖级。每个电源电压多依赖级具有耦合到存储节点的输出和分别耦合到多个存储节点中的至少两个其他存储节点的至少两个控制输入。电源电压多依赖级被配置为响应于分别存储在至少两个其他存储节点中的两个数据位的两个状态的变化,引起存储在存储节点中的数据位的状态从第一状态变为第二状态。(Embodiments of the present disclosure relate to soft error recovery latches. A latch is provided. The latch includes a plurality of storage nodes, including a plurality of data storage nodes configured to store a data bit having one of two states, and a plurality of complementary data storage nodes configured to store complements of the data bit. The latch includes a plurality of power supply voltage multi-dependent stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of a data bit stored in the storage node to change from a first state to a second state in response to changes in two states of two data bits respectively stored in at least two other storage nodes.)

1. A circuit, comprising:

a first latch, comprising:

a plurality of storage nodes comprising:

a plurality of data storage nodes, each configured to store a data bit having one of two states, the two states including a first state and a second state; and

a plurality of complementary data storage nodes, each complementary data storage node configured to store a complement of the data bit; and

a plurality of first voltage multi-dependency stages corresponding to the plurality of storage nodes, respectively, each first voltage multi-dependency stage having an output coupled to a respective storage node of the plurality of storage nodes and at least two control inputs coupled to at least two other storage nodes of the plurality of storage nodes, respectively, the first voltage multi-dependency stages configured to cause a change in two states of two data bits stored in the storage nodes, respectively, from the second state to the first state in response to a change in the two states of the two data bits stored in the at least two other storage nodes, respectively.

2. The circuit of claim 1, wherein the first latch comprises:

a plurality of second voltage multi-dependency stages corresponding to the plurality of storage nodes, respectively, each second voltage multi-dependency stage having an output coupled to the respective one of the plurality of storage nodes and at least two control inputs coupled to at least two other ones of the plurality of storage nodes, respectively, the second voltage multi-dependency stages configured to cause a change in two states of two data bits stored in the storage nodes, respectively, from the first state to the second state in response to a change in the two states of the two data bits stored in the at least two other storage nodes, respectively.

3. The circuit of claim 1, wherein the first voltage multi-dependency stage is configured to avoid causing the state of the data bit stored in the storage node to change from the second state to the first state when only one of the two data bits stored in the at least two other storage nodes, respectively, changes state or when none of the two data bits stored in the at least two other storage nodes, respectively, changes state.

4. The circuit of claim 1, wherein the second voltage multi-dependent stage comprises:

a first transistor having a first conductive terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conductive terminal; and

a second transistor having a first conductive terminal coupled to the second conductive terminal of the first transistor, a second conductive terminal coupled to a first voltage node that provides a first voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

5. The circuit of claim 2, wherein the second voltage multi-dependent stage comprises:

a first transistor having a first conductive terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes, and a second conductive terminal; and

a second transistor having a first conductive terminal coupled to the second conductive terminal of the first transistor, a second conductive terminal coupled to a second voltage node that provides a second voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

6. The circuit of claim 1, wherein the first latch comprises:

a first input stage coupled to the plurality of storage nodes and configured to:

receiving a clock signal having one of two clock states, the two clock states including a first clock state and a second clock state;

receiving a data signal having a data signal;

setting the data bit and the complement of the data bit based on the data signal state in response to the clock signal having the first clock state; and

refraining from setting the data bit and the complement of the data bit in response to the clock signal having the second clock state.

7. The circuit of claim 6, comprising:

a second latch coupled to the first latch and comprising a plurality of second latch storage nodes, the second latch configured to:

receiving the clock signal;

causing data stored in the plurality of storage nodes to be transferred to the plurality of second latch storage nodes, respectively, in response to the clock signal having the second clock state.

8. A method, comprising:

storing a plurality of data bits in a respective plurality of storage nodes of a latch, each data bit of the plurality of data bits being stored in a respective storage node of the plurality of storage nodes;

determining, by a first multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs coupled to two other storage nodes of the plurality of storage nodes, respectively, whether two respective states of two data bits stored in the two other storage nodes, respectively, have changed;

in response to determining the two respective state changes, causing a state change of a data bit stored in the storage node; and

refraining from causing the state change of the data bit stored in the storage node in response to determining that one or neither of the two respective states changes.

9. The method of claim 8, wherein each of the plurality of data bits has one of two states, the two states comprising: a first state corresponding to the reference voltage, and a second state corresponding to the power supply voltage.

10. The method of claim 9, wherein causing a state change of the data bits stored in the storage nodes comprises: causing the state of the data bit to change from the first state to the second state.

11. The method of claim 10, comprising:

determining, by a second multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs coupled to two other storage nodes of the plurality of storage nodes, respectively, whether the two respective states of the two data bits stored in the two other storage nodes, respectively, change from the first state to the second state; and

causing the state of the data bit stored in the storage node to change from the second state to the first state in response to determining that the two respective states change from the first state to the second state.

12. The method of claim 10, wherein the first multi-dependency stage comprises:

a first transistor having a first conductive terminal coupled to the storage node, a control terminal coupled to a first of the two other storage nodes, and a second conductive terminal; and

a second transistor having a first conductive terminal coupled to the second conductive terminal of the first transistor, a second conductive terminal coupled to a supply voltage node that provides the supply voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

13. The method of claim 12, wherein the second multi-dependency stage comprises:

a first transistor having a first conductive terminal coupled to the storage node, a control terminal coupled to the first of the at least two other storage nodes, and a second conductive terminal; and

a second transistor having a first conductive terminal coupled to the second conductive terminal of the first transistor, a second conductive terminal coupled to a supply voltage node that provides the supply voltage, and a control terminal coupled to a second storage node of the at least two other storage nodes.

14. A latch, comprising:

a supply voltage node;

a reference voltage node;

a plurality of storage nodes including a first storage node, a second storage node, and a third storage node; and

a plurality of supply voltage multi-dependency stages including a first supply voltage multi-dependency stage including a first supply transistor having a first conduction terminal coupled to the first storage node, a control terminal coupled to the second storage node, and a second conduction terminal, and a second supply transistor having a first conduction terminal coupled to the second conduction terminal of the first supply transistor, a control terminal coupled to the third storage node, and a second conduction terminal coupled to the supply voltage node; and

a plurality of reference voltage multi-dependency stages including a first reference voltage multi-dependency stage including a first reference transistor having a first conduction terminal coupled to the first storage node, a control terminal coupled to the second storage node, and a second conduction terminal, and a second reference transistor having a first conduction terminal coupled to the second conduction terminal of the first reference transistor, a control terminal coupled to the third storage node, and a second conduction terminal coupled to the reference voltage node.

15. The latch of claim 14, wherein the plurality of storage nodes includes a fourth storage node.

16. The latch of claim 15, wherein the first storage node and the fourth storage node are configured to store a data bit, and the second storage node and the third storage node are configured to store a complement of the data bit.

17. The latch of claim 15, comprising:

a first input stage configured to selectively couple the first and fourth storage nodes, or the second and third storage nodes, to the supply voltage node.

18. The latch of claim 15, comprising:

a second input stage configured to selectively couple the first and fourth storage nodes, or the second and third storage nodes, to the reference voltage node.

19. The latch of claim 17, wherein the first input stage is configured to:

receiving a clock signal and an input data signal;

coupling the first storage node and the fourth storage node to the supply voltage node when the clock signal has a low state and the input data signal has a high state; and

coupling the first storage node and the fourth storage node to the reference voltage node when the clock signal has a low state and the input data signal has a low state.

20. The latch of claim 19, wherein the first input stage is configured to:

decoupling the first storage node and the fourth storage node from the supply voltage node when the clock signal transitions to the high state.

Technical Field

The present disclosure relates to data storage latches, and in particular to data storage latches that are resilient to soft errors occurring in stored data.

Background

In some cases, a storage device, such as a latch, may encounter errors that cause one or more bits of stored data to change state. For example, as a result of an error, a stored data bit may change state from a logic 0 to a logic 1, and vice versa. Storage errors may occur due to radiation or particle strikes, etc. After an error occurs, it propagates through the circuit or system and causes the circuit or system to malfunction or operate in a different manner than its intended purpose.

In many applications, particularly critical applications such as space, automotive or medical applications, the error tolerance is low. This is because the propagation of errors can have serious adverse consequences.

Disclosure of Invention

A latch is provided. The latch is soft error recovery and therefore can tolerate an error in one storage bit without adversely affecting the operation of the latch. Latches can recover from a single bit error by exploiting redundancy and dependencies.

As described herein, for each data bit, a latch stores a plurality of data bits in a corresponding plurality of storage nodes. Some storage nodes store copies of data bits, while other storage nodes store complements of the data bits. The stored data bit may be a logic 0 or a logic 1. For example, if the stored data bit is a logic 0, some storage nodes of the latch store a logic 0 and other storage nodes of the latch store a logic 1 (complement of logic 0).

For each storage node, the latch includes one or more multiple dependency stages. The multi-dependency stage links a storage node to two or more other storage nodes of a latch. The multiple dependency stages make the state of a data bit stored in a storage node dependent on two or more other storage nodes it depends on. Data in a storage node does change unless the data in two or more other storage nodes also changes. If the data of only one of the other storage nodes changes, the change is not enough to trigger the change of the data of the storage node.

A change in data of a storage node occurs when data in all two or more other storage nodes (on which the storage node depends) changes. If less than all of the other storage nodes change state, the change is insufficient to trigger a data change. Thus, the latch is resilient to soft errors.

Drawings

FIG. 1 shows a schematic diagram of a latch;

FIG. 2 shows a schematic diagram of a latch; and

fig. 3A and 3B show schematic diagrams of flip-flops.

Detailed Description

Fig. 1 shows a schematic diagram of a latch 100 a. Latch 100a includes a memory stage 101a coupled to a first input stage 102a and a second input stage 104 a. Latch 100a is a memory device that stores one or more bits of data. Latch 100a includes four data storage nodes: a first data storage node 106a, a second data storage node 106b, a first complementary data storage node 106c, and a second complementary data storage node 106 d. The data storage nodes 106a-d are coupled to the first input stage 102 a. In latch 100a, each data storage node 106a-d is coupled to an associated supply voltage multi-dependency stage 108a-d and an associated reference voltage multi-dependency stage 110 a-d.

In particular, latch 100a includes first and second supply voltage multi-dependent stages 108a and 108b for first and second data storage nodes 106a and 106b, respectively. The latch 100a includes a third and fourth supply voltage multi-dependent stage 108c, 108d for the first and second complementary data storage nodes 106c, 106d, respectively. Latch 100a also includes first and second reference voltage multi-dependent stages 110a and 110b for first and second data storage nodes 106a and 106b, respectively, and third and fourth reference voltage multi-dependent stages 110c and 110d for third and fourth complementary data storage nodes 106c and 106d, respectively.

The supply voltage multi-dependency stages 108a, 108b, 108c, 108d selectively couple the data storage nodes 106a, 106b, 106c, 106d to the voltage supply node 120, respectively. The voltage source node 120 may provide a supply voltage (or rail voltage) (V) to the latch 100a_dd) And the like. The supply voltage may be a voltage level representing a logic 1. The reference voltage multi-dependency stages 110a, 110b, 110c, 110d selectively couple the data storage nodes 106a, 106b, 106c, 106d to the second input stage 104a, respectively. The second input stage 104a selectively couples the reference voltage multi-dependency stages 110a-d to a reference voltage node (not shown) to provide a reference voltage (or ground voltage) for selectively grounding the data storage nodes 106 a-d. The reference voltage may be a zero voltage having a voltage level representing a logic 0.

Each supply voltage multi-dependent stage 108a-d comprises two cascaded transistors. The first, second, third and fourth supply voltage multi-dependent stages 108a, 108b, 108c, 108d comprise first and second transistors 112a, 112b, 112c, 112d, 114a, 114b, 114c, 114d, respectively. The first, second, third and fourth reference voltage multi-dependent stages 110a, 110b, 110c, 110d comprise first and second transistors 116a, 116b, 116c, 116d, 118a, 118b, 118c, 118d, respectively.

In each supply voltage multi-dependent stage 108a-d, a first transistor 112a-d has a drain coupled to the data storage node 106a-d of the stage 108a-d and a source coupled to the drain of a second transistor 114 a-d. The first transistors 112a-d have gates coupled to another data storage node 106 a-d. The second transistors 114a-d have a source coupled to the voltage source node 120 and a gate coupled to another data storage node 106a-d that is different from the data storage node 106a-d to which the gates of the first transistors 112a-d are coupled.

Although the first transistors 112a-d and the second transistors 114a-d of the supply voltage multi-dependency stages 108a-d are shown as p-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), any other type of transistor may be used. Each supply voltage multi-dependent stage 108a-d may have a data input at the source of the second transistor 114a-d, first and second control inputs at the gates of the first and second transistors 112a-d and 114a-d, respectively, and an output at the drain of the first transistor 112 a-d. Thus, the supply voltage multi-dependency stages 108a-d provide an output voltage (output of the stages 108 a-d) at the data storage nodes 106a-d that is dependent on the voltages of the gates of the first and second transistors 112a-d and 114a-d (control inputs of the stages 108 a-d) and the source voltage at the voltage supply node 120 (input of the stages 108 a-d).

In the first supply voltage multi-dependency stage 108a, the drain of the first transistor 112a is coupled to the first data storage node 106a, the gate of the first transistor 112a is coupled to the second complementary data storage node 106d, and the gate of the second transistor 114a is coupled to the first complementary data storage node 106 c. In the second supply voltage multi-dependency stage 108b, the drain of the first transistor 112b is coupled to the second data storage node 106b, the gate of the first transistor 112b is coupled to the first complementary data storage node 106c, and the gate of the second transistor 114b is coupled to the second complementary data storage node 106 d. In the third supply voltage multi-dependency stage 108c, the drain of the first transistor 112c is coupled to the first complementary data storage node 106c, the gate of the first transistor 112c is coupled to the second data storage node 106b, and the gate of the second transistor 114c is coupled to the first data storage node 106 a. In the fourth supply voltage multi-dependency stage 108d, the drain of the first transistor 112d is coupled to the second complementary data storage node 106d, the gate of the first transistor 112d is coupled to the first data storage node 106a, and the gate of the second transistor 114d is coupled to the second data storage node 106 b.

The reference voltage multi-dependent stages 110a-d of the plurality of data storage nodes 106a-d are similarly configured as respective supply voltage multi-dependent stages 108a-d, except that the inputs of the reference voltage multi-dependent stages 110a-d are coupled to the second input stage 104a instead of the voltage supply node 120.

Each reference voltage multi-dependent stage 110a-d includes a first transistor 116a-d and a second transistor 118 a-d. The first transistors 116a-d have drains coupled to the data storage nodes 106a-d and sources coupled to the drains of the second transistors 118 a-d. The source of the second transistor is coupled to the second input stage 104 a. The gates of the first and second transistors 116a-d and 118a-d are coupled to two data storage nodes 106a-d, respectively, the two data storage nodes 106a-d being different from each other and from the data storage node 106a-d to which the drain of the first transistor 116a-d is coupled.

The gates of the first transistor 116a and the second transistor 118a of the first reference voltage multi-dependent stage 110a are coupled to the second complementary data storage node 106d and the first complementary data storage node 106c, respectively. The gates of the first transistor 116b and the second transistor 118b of the second reference voltage multi-dependent stage 110b are coupled to the first complementary data storage node 106c and the second complementary data storage node 106d, respectively. The gates of the first transistor 116c and the second transistor 118c of the third reference voltage multi-dependent stage 110c are coupled to the second data storage node 106b and the first data storage node 106a, respectively. The gates of the first transistor 116d and the second transistor 118d of the fourth reference voltage multi-dependent stage 110d are coupled to the first data storage node 106a and the second data storage node 106b, respectively.

The first data storage node 106a and the second data storage node 106b store duplicate (or identical) data bits (denoted "MA" and "MB", respectively). The first and second complementary data storage nodes 106c and 106d store complements (denoted "MAn" and "MBn," respectively) of the data bits stored in the first and second data storage nodes 106a and 106 b. For example, if MA and MB are logic 1, then MAn and MBn are logic 0, and vice versa.

The arrangement of the supply voltage multi-dependent stages 108a-d and the reference voltage multi-dependent stages 110a-d enables the data storage nodes 106a-d to be dependent on the latch 100 a. This dependency ensures that the state of the nodes 106a-d changes only when the corresponding state of the node on which the nodes 106a-d depend also changes.

For example, the state of the first data storage node 106a ("MA") depends on the states of the first and second complementary data storage nodes 106c and 106d ("MAn" and "MBn"). When first data storage node 106a stores a logic 1, both first complementary data storage node 106c and second complementary data storage node 106d store a logic 0. To change the state of the first data storage node 106a from logic 1 to logic 0, the states of the first and second complementary data storage nodes 106c and 106d should change from logic 0 to logic 1. The change in state of one of the complementary data storage nodes 106c, 106d is insufficient to cause a change in state of the first data storage node 106 a. The increased redundancy reduces the likelihood of changing the data stored in the latch due to radiation or particle strikes, among other factors, and increases the robustness of the latch 100a in handling such events.

During operation, the first input stage 102a outputs data bits having a logic 1 state to two data storage nodes 106a-d for storage, such as a first data storage node 106a and a second data storage node 106b or a first complementary data storage node 106c and a second complementary data storage node 106 d. The second input stage 104a outputs data bits having complementary states (logic 0) to two data storage nodes 106a-d for storage, such as a first data storage node 106a and a second data storage node 106b or a first complementary data storage node 106c and a second complementary data storage node 106 d. Thus, for one bit of data, the latch stores four bits; two bits have the same state as and are copies of the data bit, while two bits have complementary or opposite states.

After data is stored or fed into the latch 100a through the first and second input stages 102a and 104a, the states of the data storage nodes 106a-d do not change unless the states of the two other data storage nodes change. For example, initially, the first data storage node 106a (ma) stores a logic 0, wherein the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn) store a complementary logic 1. As a result, the first transistor 112a and the second transistor 114a of the first supply voltage multi-dependent stage 108a are turned off and the first data storage node 106a is decoupled from the voltage supply node 120. Conversely, the first transistor 116a and the second transistor 118a of the first reference voltage multi-dependent stage 110a are turned on and the first data storage node 106a is coupled to the second input stage 104a that provides the reference voltage. Coupling the first data storage node 106a to the second input stage 104a causes the data stored in the first data storage node 106a (ma) to remain at logic 0.

If one of the first and second complementary data storage nodes 106c and 106d (MAn and MBn) changes state from a logic 1 to a logic 0 (e.g., as a result of a soft error), the change is insufficient to change the state of the first data storage node 106a (MA). If the first complementary data storage node 106c (MAn) changes state from logic 1 to logic 0, the second transistor 114a of the first supply voltage multi-dependent stage 108a is turned on. However, because the first transistor 112a remains off, the first supply voltage multi-dependency stage 108a is entirely off, and the first data storage node 106a (ma) remains decoupled from the voltage supply node 120. The change of state of the first complementary data storage node 106c (man) causes the second transistor 118a of the first reference voltage multi-dependent stage 110a to turn off, thereby decoupling the first data storage node 106a (ma) from the second input stage 104 a. With the first data storage node 106a (ma) decoupled from the voltage source node 120 and the second input stage 104a, the first data storage node 106a (ma) maintains its logic state at 1. Soft errors in the state of the first complementary data storage node 106c (man) do not affect the stored data of the first data storage node 106a (ma).

Table 1 shows the dependencies of first and second data storage nodes 106a, 106b (MA, MB) and first and second complementary data storage nodes 106c, 106d (Man, MBn).

Node point	Dependence on
		MA	MAn、MBn
MB	MAn、MBn
		MAn	MA、MB
MBn	MA、MB

TABLE 1

The stages 108a-d, 110a-d operate to couple the data storage nodes 106a-d to the voltage source node 120 or the second input stage 104a without soft errors. When data storage nodes 106a-d store a logic 1, it is coupled to voltage source node 120, and when data storage nodes 106a-d store a logic 0, it is coupled to second input stage 104 a. When a soft error occurs, the stages 108a-d, 110a-d operate to decouple the data storage nodes 106a-d from both the voltage source node 120 and the second input stage 104 a. Once decoupled from the voltage source node 120 and the second input stage 104a, the data storage nodes 106a-d retain their states until a soft error occurs. The stages 108a-d, 110a-d operate to change the state of the data storage nodes 106a-d if the state of the two nodes on which the data storage nodes 106a-d depend changes.

Fig. 2 shows a schematic diagram of a latch 100 b. The latch 100b includes a memory stage 101a and first and second input stages 102b and 104b coupled to the memory stage 101 a. The latch 100b has a similar structure to the latch 100a described with reference to fig. 1. However, in the latch 100b of FIG. 2, the data storage nodes 106a-d are coupled to the second input stage 104b instead of the first input stage 102 b. The second input stage 104b operates to selectively couple either the first and second data storage nodes 106a, 106b (SA, SB) or the first and second complementary data storage nodes 106c, 106d (San, SBn) to the reference voltage node. Thus, either first data storage node 106a and second data storage node 106b or first complementary data storage node 106c and second complementary data storage node 106d are set to store a logic 0 (or are in a de-asserted or de-activated state).

When a data storage node 106a-d stores a logic 0, its complementary node 106a-d stores a logic 1, which causes the associated reference voltage multi-dependent stage 110a-d and its transistors 116a-d, 118a-d to turn on. Thus, the inputs of the reference voltage multi-dependency stages 110a-d (the sources of the second transistors 118 a-d) are coupled to the reference voltage node 122. Reference voltage node 122 provides a reference voltage or ground voltage to latch 100 b.

The latch 100b is coupled to the first input stage 102b at the inputs of the supply voltage multi-dependent stages 108 a-d. In particular, the sources of the second transistors 114a-d of the supply voltage multi-dependent stages 108a-d are coupled to the first input stage 102 b. The first input stage 102b selectively provides a supply voltage to the supply voltage multi-dependent stages 108 a-d.

Fig. 3A and 3B show schematic diagrams of the flip-flop 124. The flip-flop 124 includes a master stage 126a and a slave stage 126 b. The primary stage 126a includes a data stage 128, a first input stage 102a, a first latch 100a, and a second input stage 104 a. The slave stage 126b includes a first input stage 102b, a second latch 100b, a second input stage 104b, and an output stage 130.

The data stage 128 includes two inverting diodes 132a, 132b arranged back-to-back, whereby the cathode of the first inverting diode 132a is coupled to the anode of the second inverting diode 132 b. The first inverting diode 132a receives a data bit (denoted as "D") at its anode and outputs the complement of the data bit (denoted as "DN") at its cathode. The second inverting diode 132b receives the complement of the data bit at its anode and outputs the data bit (denoted as "DB") at its cathode.

The first input stage 102a of the main stage 126a includes first and second data transistors 134a, 134b, first and second complementary data transistors 134c, 134d, and first, second, third and fourth clock transistors 136a, 136b, 136c, 136 d. The data transistors 134a, 134b, 134c, 134d have a cascade arrangement with the clock transistors 136a, 136b, 136c, 136d, respectively. According to the cascade arrangement, the data transistors 134a-d have sources coupled to the voltage source node 120 and drains coupled to the sources of the clock transistors 136 a-d. The gates of clock transistors 136a-d are used to receive a clock signal (denoted "CP"). The gates of the first and second data transistors 134a and 134b are coupled to the cathode of the first inverting diode 132 a. The gates of the second complementary data transistor 134c and the second complementary data transistor 134d are coupled to the cathode of the second inverting diode 132 b.

The drains of the clock transistors 136a, 136b, 136c, 136d are coupled to the first and second data storage nodes 106a, 106b and the first and second complementary data storage nodes 106c, 106d, respectively.

The second input stage 104a includes first and second complementary data transistors 138a, 138b, first and second data transistors 138c, 138d, and first and second clock transistors 140a, 140 b. The drains of the transistors 138a, 138b, 138c, 138d are coupled to the sources of the second transistors 118a-d of the reference voltage multi-dependent stages 110a-d, respectively. The sources of the transistors 138a, 138b, 138c, 138d are coupled to the reference voltage node 122. The gates of the first and second complementary data transistors 138a, 138b are coupled to the cathode of the first inverting diode 132 a. The gates of first data transistor 138c and second data transistor 138d are coupled to the cathode of second inverting diode 132 b.

The first clock transistor 140a has a drain coupled to the drain of the first complementary data transistor 138a, a source coupled to the drain of the second data transistor 138d, and a gate for receiving a clock signal ("CP"). The second clock transistor 140a has a drain coupled to the drain of the second complementary data transistor 138b, a source coupled to the drain of the first data transistor 138c, and a gate for receiving a clock signal ("CP").

In the slave stage 126b of the flip-flop 124, the first input stage 102b includes first, second, third and fourth master data transistors 142a, 142b, 142c and 142d and first and second clock transistors 144a and 144 b. The sources of the primary data transistors 142a-d are coupled to the voltage supply node 120. The drains of the main data transistors 142a, 142b, 142c, 142d are coupled to the sources of the second transistors 114a, 114b, 114c, 114d of the supply voltage multi-dependent stages 108a, 108b, 108c, 108d, respectively. The gates of the primary data transistors 142a, 142b, 142c, 142d are coupled to the data storage nodes 106a, 106b, 106c, 106d, respectively, of the first latch 100a of the primary stage 126 a.

The first clock transistor 144a has a source coupled to the source of the second transistor 114a of the first supply voltage multi-dependent stage 108a, a drain coupled to the source of the second transistor 114d of the fourth supply voltage multi-dependent stage 108d, and a gate for receiving a clock signal (CP). The second clock transistor 144b has a source coupled to the source of the second transistor 114b of the second supply voltage multi-dependent stage 108b, a drain coupled to the source of the second transistor 114c of the third supply voltage multi-dependent stage 108c, and a gate for receiving a clock signal (CP).

The second input stage 104b of the slave stage 126b includes first and second data transistors 146a, 146b, first and second complementary data transistors 146c, 146d, and first, second, third and fourth clock transistors 148a, 148b, 148c, 148 d. The data transistors 146a, 146b, 146c, 146d have a cascade arrangement with clock transistors 148a, 148b, 148c, 148d, respectively. According to the cascade arrangement, the data transistors 136a-d have sources coupled to the reference voltage node 122 and drains coupled to the sources of the clock transistors 148 a-d. The gates of clock transistors 148a-d are used to receive a clock signal (denoted "CP"). The drains of clock transistors 148a, 148b, 148c, 148d are coupled to first and second data storage nodes 106a, 106b and first and second complementary data storage nodes 106c, 106d of second latch 100b, respectively.

The gate of first data transistor 146a is coupled to first complementary data storage node 106c of first latch 100a of main stage 126a, the gate of second data transistor 146b is coupled to second complementary data storage node 106d of first latch 100a of main stage 126a, the gate of first complementary data transistor 146c is coupled to second data storage node 106b, and the gate of second complementary data transistor 146d is coupled to first data storage node 106 a.

The output stage 130 includes a first transistor 150a, a second transistor 150b, a third transistor 150c, and a fourth transistor 150d having a cascade arrangement. The first transistor 150a has a source coupled to the voltage source node 120, a drain coupled to the source of the second transistor 150b, and a gate coupled to the second complementary data storage node 106d of the second latch 100 b. The second transistor 150b has a drain coupled to the output node 152 and a gate coupled to the first complementary data storage node 106c of the second latch 100 b. The third transistor 150c has a drain coupled to the output node 152, a source coupled to the drain of the fourth transistor 150d, and a gate coupled to the first complementary data storage node 106c of the second latch 100 b. The fourth transistor 150d has a gate coupled to the second complementary data storage node 106d of the second latch 100b and a source coupled to the reference voltage node 122.

The master latch 126a is a single phase active low latch. When the clock signal (CP) is low, the first and second input stages 102a and 104a feed data into the first latch 100 a. When the clock signal (CP) is low, the clock transistors 136a-d of the first input stage 102a are turned on. Thus, depending on whether the data bit (D) is a logic 0 or a logic 1, either the first and second data storage nodes 106a and 106b or the first and second complementary data storage nodes 106c and 106D are coupled to the voltage source node 120 to store a logic 1.

When the data bit (D) is a logic 1, the first and second data transistors 134a and 134b are turned on, and the logic 1 is transferred to the first and second data storage nodes 106a and 106b (MA and MB). As described herein, the first and second complementary data storage nodes 106c and 106d (MAn and MBn) are dependent on the first and second data storage nodes 106a and 106b (MA and MB).

At the same time, the first and second data transistors 138c, 138d of the second input stage 104a are conductive, and the first and second complementary data transistors 138a, 138b are non-conductive. Thus, the reference voltage of the reference voltage node 122 is passed to the sources of the second transistors 118c, 118d and, via the third reference voltage multi-dependent stage 110c and the fourth reference voltage multi-dependent stage 110d, to the first complementary data storage node 106c and the second complementary data storage node 106d (MAn and MBn), which thus convert to storing a logic 0. When the data bit (D) is a logic 0, the first and second input stages 102a and 104a operate in a similar manner to cause a logic 0 to be stored in the first and second data storage nodes 106a and 106b (MA and MB) and a logic 1 to be stored in the first and second complementary data storage nodes 106c and 106D (MAn and MBn).

When the clock signal (CP) transitions to a logic 0, the first input stage 102a is turned off. The second input stage 104a provides a reference voltage at the sources of the second transistors 118a-d of the reference voltage multi-dependent stages 110 a-d. First latch 100a retains the stored data in data storage nodes 106 a-d.

In the slave latch 126b, the second input stage 104b is off while the clock signal (CP) is low. The first input stage 102b provides a supply voltage to the sources of the second transistors 114a-d of the supply voltage multi-dependent stages 108 a-d. The second latch 102b retains previously stored data in the data storage nodes 106 a-d.

When the clock signal (CP) transitions high, the clock transistors 148a-d become conductive. Depending on the logic states of the data stored in first and second data storage nodes 106a and 106b (MA and MB) and first and second complementary data storage nodes 106c and 106d (MAn and MBn) of first latch 100a of master latch 126a, first and second data transistors 146a and 146b or first and second complementary data transistors 146c and 146d are turned on.

When master latch 126a stores a logic 1 in first and second data storage nodes 106a and 106b (MA and MB), second input stage 104b passes a logic 0 to first and second complementary data storage nodes 106c and 106d (SAn and SBn) of slave latch 126 b. As described herein, first data storage node 106a and second data storage node 106b (SA and SB) are dependent upon first complementary data storage node 106c and second complementary data storage node 106d (SAn and SBn). Thus, a logic 1 is fed from the first input stage 102b to the first data storage node 106a and the second data storage node 106b (SA and SB).

Thus, when the clock signal (CP) goes high, the data stored in the data storage nodes 106a-d of the master latch 126a is transferred to the data storage node 106a of the slave latch 126 b. The slave latch 126b, which is an active high latch, stores the data stored in the master latch 126a at the time when the clock signal (CP) transitions from low to high. When the clock signal (CP) transitions back low, the slave latch 126b holds the data it stored when the clock signal (CP) is high.

The output stage 130 outputs a logic 1 or a logic 0 based on the states of the data stored in the first and second complementary data storage nodes 106c and 106d (SAn and SBn). When the complementary data storage nodes 106c, 106d (SAn and SBn) are both logic 0, the output stage 130 outputs a logic 1 at the output node 152. Conversely, when the complementary data storage nodes 106c, 106d (SAn and SBn) are both logic 1, the output stage 130 outputs a logic 0 at the output node 152. If the first and second complementary data storage nodes 106c and 106d (SAn and SBn) have different states, the output stage 130 maintains the previous output (i.e., the output provided prior to the inconsistency between the data states in the first and second complementary data storage nodes 106c and 106d (SAn and SBn)).

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.