阅读说明：本技术 数据驱动器和包括数据驱动器的显示装置 (Data driver and display device including the same ) 是由 黄英秀 高俊哲 权五照 金起德 金贞敏 柳凤铉 李炯玟 崔升勋 于 2021-04-27 设计创作，主要内容包括：本发明涉及一种数据驱动器和包括数据驱动器的显示装置。该数据驱动器包括：被配置成基于像素数据的数据位的数量生成伽马电压的伽马电压生成器；被配置成生成分别与多个伽马电压组相对应的多个时分伽马电压信号的第一数模块；用于传送多个时分伽马电压信号的多个时分伽马电压线组；被配置成根据各通道中的像素数据的高位在时分伽马电压信号当中选择时分伽马电压信号的第二数模块；被配置成根据每个通道中的像素数据的低位选择伽马电压的时分伽马电压选择块；以及被配置成在每个通道中输出选择出的伽马电压的输出缓冲器块。(The present invention relates to a data driver and a display device including the same. The data driver includes: a gamma voltage generator configured to generate a gamma voltage based on a number of data bits of the pixel data; a first number module configured to generate a plurality of time-division gamma voltage signals respectively corresponding to a plurality of gamma voltage groups; a plurality of time division gamma voltage line groups for transmitting a plurality of time division gamma voltage signals; a second number module configured to select a time-division gamma voltage signal among the time-division gamma voltage signals according to upper bits of pixel data in the channels; a time division gamma voltage selection block configured to select a gamma voltage according to lower bits of the pixel data in each channel; and an output buffer block configured to output the selected gamma voltage in each channel.)

1. A data driver outputting a plurality of data voltages to a plurality of pixels through a plurality of channels, the data driver comprising:

a gamma voltage generator configured to generate 2^NA plurality of gamma voltages, wherein N is an integer greater than 1, N corresponding to a number of data bits of each pixel data among a plurality of pixel data received by the data driver;

a first number module configured to assign the 2^NGamma voltage component 2^N-MA gamma voltage group such that 2^N-MEach of the gamma voltage groups includes the 2^N2 among gamma voltages^MA gamma voltage, where M is an integer greater than 0 and less than N, and the first number module is configured to generate the first number of gamma voltages respectively corresponding to the 2^N-M2 corresponding to each gamma voltage group^N-MA time division gamma voltage signal of 2^N-MEach of the time division gamma voltage signals represents the 2 by dividing one horizontal time^MA gamma voltage;

2^N-Ma time division gamma voltage line group for transferring the 2^N-MA time division gamma voltage signal of 2^N-MEach of the time division gamma voltage line groups comprises K time division gamma voltage lines, wherein K is greater than 1 and less than or equal to the number of the plurality of channels;

a second numerical module configured to pass the 2^N-MA time division gamma voltage line group receiving the 2^N-MA plurality of time-division gamma voltage signals, and at the 2 nd according to upper N-M bits of the N bits of a corresponding one of the plurality of pixel data in each of the plurality of channels^N-MTime division gamma voltage signalSelecting a time division gamma voltage signal;

a time division gamma voltage selection block configured to select the lower M bits of the N bits of the corresponding one of the plurality of pixel data in each of the plurality of channels at the 2^MSelecting a gamma voltage represented by the time-division gamma voltage signal selected by the second digital module among the plurality of gamma voltages; and

an output buffer block configured to output the gamma voltage in each of the plurality of channels as a data voltage among the plurality of data voltages.

2. The data driver of claim 1, wherein the plurality of lanes are grouped into K lane groups, and

wherein the K time-division gamma voltage lines are respectively coupled to the K channel groups.

3. The data driver of claim 1, wherein the plurality of lanes comprise K x L lanes, wherein L is an integer greater than zero,

wherein the K x L channels are grouped into K channel groups such that a K x I + J channel of the K channel groups is grouped into a J channel group of the K channel groups, wherein I is an integer greater than or equal to zero and less than L and J is an integer greater than zero and less than or equal to K, and

wherein the K time division gamma voltage lines are respectively coupled to the K channel groups such that each of the K time division gamma voltage lines is coupled to L of the K channels.

4. The data driver of claim 1, wherein the K time-division gamma voltage lines are four time-division gamma voltage lines,

wherein the plurality of channels comprises 4 x L channels, wherein L is an integer greater than zero,

wherein the 4 x L channels are grouped into 4 channel groups such that a 4 x I + J channel of the 4 x L channels is grouped into a J channel group of the 4 channel groups, wherein I is an integer greater than or equal to zero and less than L and J is an integer greater than zero and less than or equal to 4, and

wherein the four time-division gamma voltage lines are respectively coupled to the 4 channel groups such that each of the four time-division gamma voltage lines is coupled to L channels of the 4 × L channels.

5. The data driver of claim 1, wherein the plurality of lanes comprise K x L lanes, wherein L is an integer greater than zero,

wherein the K x L channels are grouped into K channel groups such that consecutive L channels of the K x L channels are grouped into a channel group among the K channel groups, and

wherein the K time-division gamma voltage lines are respectively coupled to the K channel groups such that each of the K time-division gamma voltage lines is coupled to the consecutive L channels of the K x L channels.

6. The data driver of claim 1, wherein the K time-division gamma voltage lines are four time-division gamma voltage lines,

wherein the plurality of channels comprises 4 x L channels, wherein L is an integer greater than zero,

wherein first to Lth channels of the 4 x L channels are grouped into a first channel group, L +1 to 2L channels of the 4 x L channels are grouped into a second channel group, 2L +1 to 3L channels of the 4 x L channels are grouped into a third channel group, and 3L +1 to 4L channels of the 4 x L channels are grouped into a fourth channel group, and

wherein the four time-division gamma voltage lines are respectively coupled to the first channel group, the second channel group, the third channel group, and the fourth channel group such that each of the four time-division gamma voltage lines is coupled to L of the 4 × L channels.

7. The data driver of claim 1, wherein the one horizontal time is equally divided into 2 having the same time period^MDivide the time, and

wherein each time division gamma voltage signal is respectively represented at the 2^MThe 2 with non-linear voltage interval in one division time^MAnd a gamma voltage.

8. The data driver of claim 1, wherein the one horizontal time is equally divided into 2 having the same time period^MDivide the time, and

wherein each time division gamma voltage signal is respectively represented at the 2^MThe 2 of the same voltage interval in one division time^MAnd a gamma voltage.

9. The data driver of claim 1, wherein the one horizontal time is divided into 2 having different time periods^MDivide the time, and

wherein each time division gamma voltage signal is respectively represented at the 2^MThe 2 of the same voltage interval in one division time^MAnd a gamma voltage.

10. The data driver of claim 1, wherein the gamma voltage generator comprises:

2^N+1 resistors coupled in series between a first line of high voltage and a second line of low voltage and configured to generate the 2 by dividing between the high voltage and the low voltage^NAnd a gamma voltage.

11. The data driver of claim 1, wherein the 2 generated by the gamma voltage generator^NThe gamma voltages are gradually decreased from the first gamma voltage to the second gamma voltage2^NA gamma voltage.

12. The data driver of claim 1, wherein the 2 generated by the gamma voltage generator^NThe gamma voltages are gradually increased from the first gamma voltage to the 2 nd gamma voltage^NA gamma voltage.

13. The data driver of claim 1, wherein the 2^NA first voltage interval between the gamma voltages in the low gray region is less than 2^NA second voltage interval in the high gray region between the gamma voltages.

14. The data driver of claim 1, wherein the first digital module comprises:

a clock generator configured to generate a clock having 2 during the one horizontal time^MA clock signal of each clock;

a bit counter configured to generate representations 1 to 2 in response to the clock signal^MThe count signal of (2); and

2^N-Mm digital-to-analog converters configured to output the 2^N-MA time division gamma voltage signal of 2^N-MEach of the M-bit digital-to-analog converters is configured to sequentially output the 2-bit analog-to-digital converter in response to the count signal^MA gamma voltage as said 2^N-MTime-division gamma voltage signals among the time-division gamma voltage signals.

15. The data driver of claim 1, wherein the second digital module comprises:

a plurality of N-M bit digital-to-analog converters respectively corresponding to the plurality of channels, each of the plurality of N-M bit digital-to-analog converters being configured to convert the plurality of pixel data into the plurality of pixel data at the 2 nd level according to the upper N-M bit of the corresponding one of the plurality of pixel data^N-MThe time-division gamma voltage signal is selected among the time-division gamma voltage signals.

16. The data driver of claim 15, wherein each of the plurality of N-M bit number analog-to-digital converters comprises:

a decoder configured to generate 2 based on the high N-M bits of the corresponding one of the plurality of pixel data^N-MA switching signal; and

2^N-Ma switch configured to respond to the 2^N-MA switching signal selectively outputting the 2^N-MTime-division gamma voltage signals.

17. The data driver of claim 1, wherein the time division gamma voltage selection block comprises:

a plurality of switching signal generators respectively corresponding to the plurality of channels, each of the plurality of switching signal generators being configured to be 2 at the one horizontal time^MGenerating a time-division switching signal having an active level during a division time corresponding to the lower M-bit of the corresponding one of the plurality of pixel data among the division times; and

a plurality of time division gamma voltage selection switches respectively corresponding to the plurality of channels, each of the plurality of time division gamma voltage selection switches configured to respond to the time division switching signal having the active level at the 2 nd^MThe gamma voltage is selected among the gamma voltages.

18. The data driver of claim 1, further comprising:

a shift register block configured to sequentially generate sampling signals in response to a start signal and a clock signal;

a sampling latch block configured to sequentially sample the plurality of pixel data in response to the sampling signal; and

a holding latch block configured to store the plurality of pixel data sampled by the sampling latch block in response to a load signal.

19. The data driver of claim 18, wherein the upper N-M bits of the N bits of each of the plurality of pixel data output from the retention latch block are provided to the second digital module, and

wherein the lower M bits of the N bits of each of the plurality of pixel data output from the holding latch block are provided to the time division gamma voltage selection block.

20. A display device, comprising:

a display panel including a plurality of pixels;

a data driver configured to receive a plurality of pixel data each having N bits, where N is an integer greater than 1, and to output a plurality of data voltages corresponding to the plurality of pixel data to the plurality of pixels through a plurality of channels; and

a controller configured to supply the plurality of pixel data to the data driver,

wherein the data driver includes:

a gamma voltage generator configured to generate 2^NA gamma voltage;

a first number module configured to assign the 2^NGamma voltage component 2^N-MA gamma voltage group such that 2^N-MEach of the gamma voltage groups includes the 2^N2 among gamma voltages^MA gamma voltage, where M is an integer greater than 0 and less than N, and the first number module is configured to generate the first number of gamma voltages respectively corresponding to the 2^N-M2 corresponding to each gamma voltage group^N-MA time division gamma voltage signal of 2^N-MEach of the time division gamma voltage signals represents the 2 by dividing one horizontal time^MA gamma voltage;

2^N-Ma time division gamma voltage line group for transferring2 is described^N-MA time division gamma voltage signal of 2^N-MEach of the time division gamma voltage line groups comprises K time division gamma voltage lines, wherein K is greater than 1 and less than or equal to the number of the plurality of channels;

a second numerical module configured to pass the 2^N-MA time division gamma voltage line group receiving the 2^N-MA plurality of time-division gamma voltage signals, and at the 2 nd according to upper N-M bits of the N bits of a corresponding one of the plurality of pixel data in each of the plurality of channels^N-MSelecting a time division gamma voltage signal among the time division gamma voltage signals;

a time division gamma voltage selection block configured to select the lower M bits of the N bits of the corresponding one of the plurality of pixel data in each of the plurality of channels at the 2^MSelecting a gamma voltage represented by the time-division gamma voltage signal selected by the second digital module among the plurality of gamma voltages; and

an output buffer block configured to output the gamma voltage in each of the plurality of channels as a data voltage among the plurality of data voltages.

Technical Field

Embodiments of the inventive concept relate to a display apparatus, and more particularly, to a data driver and a display apparatus including the same.

Background

A data driver of the display device may receive a plurality of pixel data and may output a plurality of data voltages corresponding to the plurality of pixel data to the plurality of pixels through a plurality of channels. In doing so, the data driver may generate and supply a plurality of gamma voltages to each channel through a plurality of gamma voltage lines, select one of the plurality of gamma voltages according to pixel data for each channel, and output the selected gamma voltage as a data voltage for each channel. The number of the plurality of gamma voltage lines corresponding to the number of the plurality of gamma voltages may increase the size of the data driver. For example, as the number of bits of each pixel data increases by 1, the number of gamma voltage lines may be doubled, and the size of the data driver may increase accordingly.

Disclosure of Invention

Some embodiments of the present disclosure provide a data driver having a reduced size.

Some embodiments of the present disclosure provide a display device including a data driver having a reduced size.

According to one embodiment, a data driver outputs a plurality of data voltages to a plurality of pixels through a plurality of channels. The data driver includes: a gamma voltage generator configured to generate 2^NA plurality of gamma voltages, wherein N is an integer greater than 1, N corresponding to a number of data bits of each pixel data among a plurality of pixel data received by the data driver; a first number module configured to assign 2^NGamma voltage component 2^N-MA gamma voltage group of 2^N-MEach of the gamma voltage groups includes 2^N2 among gamma voltages^MA gamma voltage, where M is an integer greater than 0 and less than N, and a first number module configured to generate respective ones of the first and second gamma voltages of 2^N-M2 corresponding to each gamma voltage group^N-MTime division gamma voltage signals, 2^N-MEach of the time division gamma voltage signals represents 2 by dividing one horizontal time^MA gamma voltage; 2^N-MA time division gamma voltage line group for transfer 2^N-MTime division gamma voltage signals, 2^N-MEach of the time division gamma voltage line groups includes K time division gamma voltage lines, where K is greater than 1 and less than or equal to the number of the plurality of channels; a second digital module configured to pass 2^N-MTime division gamma voltage line group receiving 2^N-MA plurality of time-division gamma voltage signals, and 2, based on the upper N-M bits of the N bits of the corresponding one of the plurality of pixel data in each of the plurality of channels^{N -M}Selecting a time division gamma voltage signal among the time division gamma voltage signals; a time division gamma voltage selection block configured to select a gamma voltage according to lower M bits of N bits of a corresponding one of the plurality of pixel data in each of the plurality of channels at 2^MSelecting one gamma voltage among the plurality of gamma voltages represented by the time-division gamma voltage signal selected by the second digital block; and an output buffer block configured to output the gamma voltage in each of the plurality of channels as a data voltage among the plurality of data voltages.

In an embodiment, the plurality of channels may be grouped into K channel groups, and the K time-division gamma voltage lines may be respectively coupled to the K channel groups.

In an embodiment, the plurality of channels may include K × L channels, wherein L is an integer greater than zero, K × L channels may be grouped into K channel groups such that a K × I + J channel of the K × L channels is grouped into a J channel group of the K channel groups, wherein I is an integer greater than or equal to zero and less than L, and J is an integer greater than zero and less than or equal to K, and the K time-division gamma voltage lines may be respectively coupled to the K channel groups such that each of the K time-division gamma voltage lines is coupled to L channels of the K × L channels.

In an embodiment, the K time-division gamma voltage lines may be four time-division gamma voltage lines, the plurality of channels may include 4 × L channels, where L is an integer greater than zero, the 4 × L channels may be grouped into 4 channel groups such that a 4 × I + J channel of the 4 × L channels is grouped into a J channel group of the 4 channel groups, where I is an integer greater than or equal to zero and less than L, and J is an integer greater than zero and less than or equal to 4, and the four time-division gamma voltage lines may be respectively coupled to the 4 channel groups such that each of the four time-division gamma voltage lines is coupled to a corresponding L channel of the 4 × L channels.

In an embodiment, the plurality of channels may include K × L channels, where L is an integer greater than zero, the K × L channels may be grouped into K channel groups such that consecutive L channels of the K × L channels are grouped into a channel group among the K channel groups, and the K time-division gamma voltage lines may be respectively coupled to the K channel groups such that each of the K time-division gamma voltage lines is coupled to consecutive L channels of the K × L channels.

In an embodiment, the K time-division gamma voltage lines may be four time-division gamma voltage lines, the plurality of channels may include 4 × L channels, wherein L is an integer greater than zero, first to lth channels of the 4 × L channels may be grouped into a first channel group, L +1 to 2 lth channels of the 4 × L channels may be grouped into a second channel group, 2L +1 to 3 lth channels of the 4 × L channels may be grouped into a third channel group, 3L +1 to 4 lth channels of the 4 × L channels may be grouped into a fourth channel group, and the four time-division gamma voltage lines may be respectively coupled to the first channel group, the second channel group, the third channel group and the fourth channel group, such that each of the four time-division gamma voltage lines is coupled to L of the 4 × L channels.

In an embodiment, one horizontal time may be equally divided into 2 having the same time period^MEach time division gamma voltage signal can be expressed at 2^M2 with non-linear voltage interval in each division time^MAnd a gamma voltage.

In an embodiment, one horizontal time may be equally divided into 2 having the same time period^MEach time division gamma voltage signal can be expressed at 2^M2 with equal voltage intervals in each division time^MAnd a gamma voltage.

In an embodiment, one horizontal time may be divided into 2 having different time periods^MEach time division gamma voltage signal can be expressed at 2^M2 with equal voltage intervals in each division time^MAnd a gamma voltage.

In an embodiment, the gamma voltage generator may include 2^N+1 resistors, 2^N+1 resistors are coupled in series between a first line of high voltage and a second line of low voltage, and configured to generate 2 by dividing between high voltage and low voltage^NAnd a gamma voltage.

In an embodiment, 2 generated by the gamma voltage generator^NThe gamma voltages may be gradually decreased from the first gamma voltage to the 2 nd gamma voltage^NA gamma voltage.

In an embodiment, 2 generated by the gamma voltage generator^NThe gamma voltages may be gradually increased from the first gamma voltage to the 2 nd gamma voltage^NA gamma voltage.

In the examples，2^NA first voltage interval between the gamma voltages in the low gray region may be less than 2^NA second voltage interval in the high gray region between the gamma voltages.

In an embodiment, the first digital module may include: a clock generator configured to generate a clock having 2 during one horizontal time^MA clock signal of each clock; a bit counter configured to generate representations 1 to 2 in response to a clock signal^MThe count signal of (2); and 2^N-MM digital-to-analog converters configured to output 2 respectively^N-MTime division gamma voltage signals, 2^N-MEach of the M-bit digital-to-analog converters is configured to sequentially output 2 in response to the count signal^MGamma voltage as 2^{N -M}Time-division gamma voltage signals among the time-division gamma voltage signals.

In an embodiment, the second digital module may include a plurality of N-M bit digital-to-analog converters respectively corresponding to the plurality of channels, each of the plurality of N-M bit digital-to-analog converters being configured to be at 2 according to a high N-M bit of a corresponding one of the plurality of pixel data^N-MThe time division gamma voltage signal is selected among the time division gamma voltage signals.

In an embodiment, each of the plurality of N-M bit digital to analog converters may include: a decoder configured to generate 2 based on high N-M bits of corresponding one of the plurality of pixel data^N-MA switching signal; and 2^N-MA switch configured to respond to 2^N-MA switching signal is selectively output 2^N-MTime-division gamma voltage signals.

In an embodiment, the time division gamma voltage selection block may include: a plurality of switching signal generators respectively corresponding to the plurality of channels, each of the plurality of switching signal generators being configured to be 2 at one horizontal time^MGenerating a time-division switching signal having an active level during a division time corresponding to a lower M-phase of a corresponding one of the plurality of pixel data among the division times;and a plurality of time division gamma voltage selection switches respectively corresponding to the plurality of channels, each of the plurality of time division gamma voltage selection switches being configured to respond to a time division switching signal having an active level, at 2^MThe gamma voltage is selected among the gamma voltages.

In an embodiment, the data driver may further include: a shift register block configured to sequentially generate sampling signals in response to a start signal and a clock signal; a sampling latch block configured to sequentially sample a plurality of pixel data in response to a sampling signal; and a holding latch block configured to store the plurality of pixel data sampled by the sampling latch block in response to the load signal.

In an embodiment, upper N-M bits of N bits of each of the plurality of pixel data output from the holding latch block may be provided to the second digital block, and lower M bits of N bits of each of the plurality of pixel data output from the holding latch block may be provided to the time division gamma voltage selection block.

According to one embodiment, a display device includes: a display panel including a plurality of pixels; a data driver configured to receive a plurality of pixel data each having N bits, where N is an integer greater than 1, and output a plurality of data voltages corresponding to the plurality of pixel data to the plurality of pixels through a plurality of channels; and a controller configured to provide the plurality of pixel data to the data driver. The data driver includes: a gamma voltage generator configured to generate 2^NA gamma voltage; a first number module configured to assign 2^NGamma voltage component 2^N-MA gamma voltage group of 2^N-MEach of the gamma voltage groups includes 2^N2 among gamma voltages^MA gamma voltage, where M is an integer greater than 0 and less than N, and a first number module configured to generate respective ones of the first and second gamma voltages of 2^N-M2 corresponding to each gamma voltage group^N-MTime division gamma voltage signals, 2^N-MEach of the time division gamma voltage signals is tabulated by dividing one horizontal timeShow 2^MA gamma voltage; 2^N-MA time division gamma voltage line group for transfer 2^N-MTime division gamma voltage signals, 2^N-MEach of the time division gamma voltage line groups includes K time division gamma voltage lines, where K is greater than 1 and less than or equal to the number of the plurality of channels; a second digital module configured to pass 2^N-MTime division gamma voltage line group receiving 2^N-MA plurality of time-division gamma voltage signals, and 2, based on the upper N-M bits of the N bits of the corresponding one of the plurality of pixel data in each of the plurality of channels^N-MSelecting a time division gamma voltage signal among the time division gamma voltage signals; a time division gamma voltage selection block configured to select a gamma voltage according to lower M bits of N bits of a corresponding one of the plurality of pixel data in each of the plurality of channels at 2^MSelecting a gamma voltage represented by the time-division gamma voltage signal selected by the second digital module among the plurality of gamma voltages; and an output buffer block configured to output the gamma voltage in each of the plurality of channels as a data voltage among the plurality of data voltages.

As described above, in the data driver and the display device according to the embodiment, the first digital module may generate 2^N-MA second digital module for selecting 2 according to high N-M bits of each pixel data in each channel^N-MOne of the time-division gamma voltage signals, and the time-division gamma voltage selection block may select one of the 2M gamma voltages represented by the selected time-division gamma voltage signal according to the lower M bits of each pixel data in each channel. Accordingly, the size and power consumption of the data driver can be reduced.

Further, in the data driver and the display device according to the embodiment, each of the time-division gamma voltage signals may be transferred to a plurality of channels through K time-division gamma voltage lines, where K is greater than 1 and less than or equal to the number of the plurality of channels, and each of the time-division gamma voltage lines may be coupled to only a corresponding portion of the plurality of channels. Accordingly, a delay (e.g., RC delay) of the time-division gamma voltage signal may be reduced, and the time-division gamma voltage signal may be accurately transmitted to a plurality of channels.

Drawings

Illustrative, non-limiting embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1 is a block diagram of a data driver according to an embodiment.

Fig. 2 is a circuit diagram of a gamma voltage generator included in a data driver according to an embodiment.

Fig. 3 illustrates an example of a gamma voltage generated by the gamma voltage generator according to an embodiment.

Fig. 4 illustrates another example of gamma voltages generated by a gamma voltage generator according to an embodiment.

Fig. 5 is a block diagram of a first data module included in a data driver according to an embodiment.

Fig. 6 illustrates an example of time-division gamma voltage signals output by each of the M-bit digital-to-analog converters of the first digital block.

Fig. 7 illustrates another example of the time-division gamma voltage signals output by each of the M-bit digital-to-analog converters of the first digital block.

Fig. 8 illustrates still another example of the time-division gamma voltage signals output by each of the M-bit digital-to-analog converters of the first digital block.

Fig. 9 is a block diagram of a data driver including a plurality of time-division gamma voltage line groups coupled to a plurality of channels according to an embodiment.

Fig. 10 is a circuit diagram of time-division gamma voltage lines for describing an example of delay of time-division gamma voltage signals.

Fig. 11 is a block diagram of a data driver including a plurality of time-division gamma voltage line groups coupled to a plurality of channels according to another embodiment.

Fig. 12 is a block diagram of a second module included in a data driver according to an embodiment.

Fig. 13 is a block diagram of a time division gamma voltage selection block included in a data driver according to an embodiment.

Fig. 14 illustrates an example of an operation of the time-division gamma voltage selection block of fig. 13.

Fig. 15 is a block diagram of a display device including a data driver according to an embodiment.

Fig. 16 is a circuit diagram of a pixel included in a display device according to an embodiment.

Fig. 17 is a circuit diagram of another example of a pixel included in a display device according to an embodiment.

Fig. 18 is a block diagram of an electronic device including a display device according to an embodiment.

Detailed Description

Embodiments of the present disclosure are described more fully hereinafter with reference to the accompanying drawings. Throughout this disclosure, the same or similar reference numerals refer to the same or similar elements.

Fig. 1 is a block diagram of a data driver according to an embodiment, fig. 2 is a circuit diagram of a gamma voltage generator included in the data driver according to an embodiment, fig. 3 illustrates an example of a gamma voltage generated by the gamma voltage generator according to an embodiment, fig. 4 illustrates another example of a gamma voltage generated by the gamma voltage generator according to an embodiment, fig. 5 is a block diagram of a first number module included in the data driver according to an embodiment, fig. 6 illustrates an example of a time division gamma voltage signal output by each M-bit digital-to-analog converter of the first number module, fig. 7 illustrates another example of a time division gamma voltage signal output by each M-bit digital-to-analog converter of the first number module, fig. 8 illustrates yet another example of a time division gamma voltage signal output by each M-bit digital-to-analog converter of the first number module, fig. 9 is a block diagram of a data driver including a plurality of time division gamma voltage line groups coupled to a plurality of channels according to an embodiment, fig. 10 is a circuit diagram of time-division gamma voltage lines for describing an example of delay of a time-division gamma voltage signal, fig. 11 is a block diagram of a data driver including a plurality of time-division gamma voltage line groups coupled to a plurality of channels in the data driver according to another embodiment, fig. 12 is a block diagram of a second module included in the data driver according to the embodiment, fig. 13 is a block diagram of a time-division gamma voltage selection block included in the data driver according to the embodiment, and fig. 14 illustrates an example of an operation of the time-division gamma voltage selection block of fig. 13.

Referring to fig. 1, the data driver 100 may receive a plurality of pixel data PDAT and may output a plurality of data voltages VD corresponding to the plurality of pixel data PDAT to a plurality of pixels of the display panel through a plurality of channels CH. The data driver 100 may include a gamma voltage generator 150, a first number module 160, 2^N-MTime division gamma voltage line groups TDGLG 1-TDGLG 2^N-MA second module 170, a time division gamma voltage selection block 180, and an output buffer block 190. In some embodiments, the data driver 100 may further include a shift register block 110, a sampling latch block 120, a holding latch block 130, and a level shifter block 140.

The shift register block 110 may sequentially generate the sampling signal SS in response to the start signal STS and the clock signal CLK. In some embodiments, the shift register block 110 may include a plurality of serially connected shift registers that sequentially output the sampling signal SS by shifting the start signal STS in response to the clock signal CLK.

The sample latch block 120 may sequentially sample the output image data ODAT from a controller (e.g., the controller 440 in fig. 15) or a plurality of pixel data PDAT of a plurality of pixels in response to the sampling signal SS received from the shift register block 110. In some embodiments, the sample latch block 120 may include a plurality of sample latches that respectively sample the plurality of pixel data PDAT in response to the sampling signal SS.

The hold latch block 130 may store the plurality of pixel data PDAT sampled by the sample latch block 120 in response to the LOAD signal LOAD. In some embodiments, the hold latch block 130 may include a plurality of hold latches corresponding to the plurality of sample latches of the sample latch block 120.

The level shifter block 140 may change the voltage levels of the plurality of pixel data PDAT output from the holding latch block 130 to voltage levels suitable for the second digital block 170 and/or the time division gamma voltage selection block 180. In some embodiments, the level shifter block 140 may include a plurality of level shifters corresponding to a plurality of holding latches of the holding latch block 130.

In some embodiments, each pixel data PDAT may have N bits, where N is an integer greater than 1. In each channel CH, upper N-M bits of N bits of each pixel data PDAT output from the holding latch block 130 through the level shifter block 140 may be provided to the second number block 170, and lower M bits of N bits of each pixel data PDAT output from the holding latch block 130 through the level shifter block 140 may be provided to the time division gamma voltage selection block 180, where M is an integer greater than 0 and less than N. For example, in the case where N is 10 and M is 4, the holding latch block 130 may provide the upper 6 bits of each pixel data PDAT to the second digital block 170 and may provide the lower 4 bits of each pixel data PDAT to the time division gamma voltage selection block 180.

The gamma voltage generator 150 may generate 2 which can be represented by each pixel data PDAT having N bits^N2 corresponding to each gray level^NAnd a gamma voltage. In some embodiments, the gamma voltage generator 150 may receive the reference voltage having a value of 2 from a controller (not shown) or a gamma reference voltage generator (not shown)^NGamma reference voltages of gamma reference gray levels of a part of the gray levels, and may be generated respectively with all of 2 based on the gamma reference voltages^N2 corresponding to each gray level^NAnd a gamma voltage.

In some embodiments, as illustrated in fig. 2, the gamma voltage generator 150 may include 2 serially coupled between a line of a high voltage VDD and a line of a low voltage VSS^N+1 resistors R1-R2^N+1。2^N+1 resistors R1-R2^N+1 may generate 2 by dividing between a high voltage VDD and a low voltage VSS^NGamma voltages GV 1-GV 2^N. In some embodiments, as illustrated in FIG. 3, 2 is generated by gamma voltage generator 150^NGamma voltages GV 1-GV 2^NMay be gradually decreased from the first gamma voltage GV1 corresponding to the first gray level (e.g., 0 gray level) to the 2 nd gray level^NThe second gray level (for example, 255 gray levels in the case where N is 8)2^NGamma voltage GV2^N. In other embodiments, as illustrated in FIG. 4, 2 is generated by the gamma voltage generator 150^NGamma voltages GV 1-GV 2^NCan be gradually increased from the first gamma voltage GV1 corresponding to the first gray level (e.g., 0 gray level) to the 2 nd gray level^N2 nd gray level (for example, 255 gray level in the case where N is 8) corresponding to the gray level^NGamma voltage GV2^N. For example, as illustrated in fig. 16, in the case where each pixel PX includes a driving transistor PT1 implemented with a P-type metal oxide semiconductor (PMOS) transistor, the gamma voltage generator 150 may generate (but is not limited to) 2 as illustrated in fig. 3^NGamma voltages GV 1-GV 2^N. In another example, as illustrated in fig. 17, in the case where each pixel PX includes a driving transistor NT1 implemented with an N-type metal oxide semiconductor (NMOS) transistor, the gamma voltage generator 150 may generate, but is not limited to, 2 as illustrated in fig. 4^NGamma voltages GV 1-GV 2^N. In yet another example, 2 generated by the gamma voltage generator 150 regardless of the type of the driving transistor^NGamma voltages GV 1-GV 2^NCan be increased and/or decreased from the first gamma voltage GV1 to the 2 nd^NGamma voltage GV2^N. Further, in some embodiments, as illustrated in fig. 3 and 4, in a low gray region (e.g., from a first gray level to a 2 nd gray level)^MGray level) (e.g., first gamma voltage GV1 to 2 nd gamma voltage GV 1)^MGamma voltage GV2^M) The voltage interval therebetween may be smaller than in the high gray region (e.g., from 2 nd^N-2^M+1 gray level to 2 nd gray level^NGray scale) in the gamma voltage (e.g., 2 nd^N-2^M+1 gamma voltage GV2^N-2^M+1 to 2 nd^NGamma voltage GV2^N) The voltage interval in between. For example, as the gray level increases, or as 2^NGamma voltages GV 1-GV 2^NIncreasing the first gamma voltage GV1 to the 2 nd^NGamma voltage GV2^N，2^NGamma voltages GV 1-GV 2^NMay be gradually increased. In this case, it is preferable that the air conditioner,2^Ngamma voltages GV 1-GV 2^NIt is possible to have a relatively small voltage interval in the low gray region and thus to more accurately represent gray levels in the low gray region.

Further, in some embodiments, as illustrated in fig. 2, 2^NGamma voltages GV 1-GV 2^NMay be grouped (by first number module 160) into 2^N-MGamma voltage groups GVG 1-GVG 2^N-MSo that each gamma voltage group (e.g., the first gamma voltage group GVG1) may include 2 respectively^NGamma voltages GV 1-GV 2^NMiddle 2^MGamma voltages (e.g., first gamma voltage GV 1-2 nd gamma voltage)^MGamma voltage GV2^M). For example, in the case where N is 10 and M is 4, the first to sixteenth gamma voltages GV1 to GV16 may be grouped into a first gamma voltage group GVG1, the seventeenth to thirty-second gamma voltages GV17 to GV32 may be grouped into a second gamma voltage group GVG2, and the first to sixty-zero nine gamma voltages GV1009 to the first to twenty-four gamma voltages GV1024 may be grouped into a sixty-fourth gamma voltage group GVG 64.

The first number module 160 may receive 2 from the gamma voltage generator 150^N-MGamma voltage groups GVG 1-GVG 2^N-MEach gamma voltage group (e.g., the first gamma voltage group GVG1) includes 2^MGamma voltages (e.g., first gamma voltage GV 1-2 nd gamma voltage)^MGamma voltage GV2^M) And the first number module 160 may generate the values of 2 respectively^N-MGamma voltage groups GVG 1-GVG 2^N-MCorresponding to 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-M. Each time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) may represent 2 by dividing one horizontal time 1H^MGamma voltages (e.g., first gamma voltage GV 1-2 nd gamma voltage)^MGamma voltage GV2^M). One horizontal time 1H indicates a time for processing one line of pixels.

In some embodiments, as illustrated in fig. 5, the first number module 160 may include an M clock generator 161, an M-bit counter 162, and 2^N-MM-bit digital-to-analog converters (DACs) 163, 164, …And 166. The M clock generator 161 may generate a clock having 2 during one horizontal time 1H^MM clock signals MCLK of one clock. The M-bit counter 162 may generate a signal indicating an increase from 1 to 2 during one horizontal time 1H by counting clocks of the M clock signal MCLK^MM count signal MCS of the value of (c). 2^N-MThe M-bit DACs 163, 164, …, 166 may each output 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-M. Each M-bit DAC (e.g., the first M-bit DAC 163) may receive a corresponding gamma voltage group (e.g., the first gamma voltage group GVG1) or 2^MGamma voltages (e.g., first gamma voltage GV 1-2 nd gamma voltage)^MGamma voltage GV2^M) And may sequentially output 2 in response to the M-count signal MCS^MGamma voltages (e.g., first gamma voltage GV 1-2 nd gamma voltage)^MGamma voltage GV2^M) As 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MCorresponding time-division gamma voltage signal TDGVS (e.g., first time-division gamma voltage signal TDGVS1) among them. For example, in the case where M is 3, as illustrated in fig. 6, one horizontal time 1H may be equally divided into 2^M(or 8) division times having the same period 1H/8, and each time-division gamma voltage signal TDGVS output from each M-bit DAC (e.g., the first M-bit DAC 163) may respectively represent a corresponding 2-division gamma voltage signal having a non-linear voltage interval in the 8 division times^M(or 8) gamma voltages GV1, GV2, GV3, GV4, GV5, GV6, GV7, and GV 8. In the present example of fig. 6, the 8 gamma voltages GV1, GV2, GV3, GV4, GV5, GV6, GV7, and GV8 of the time-division gamma voltage signal TDGVS may have gradually increasing voltage intervals in one horizontal time 1H.

In other embodiments, as illustrated in fig. 7, one horizontal time 1H may be equally divided into 2^MEach (or 8 in this example, where M is 3) of the division times having the same period 1H/8, and each time-division gamma voltage signal TDGVS may respectively represent 8 gamma voltages GV1 to GV8 having substantially the same voltage interval among the 8 division times. In the present example of fig. 7, 8 gamma voltages GV of the time-division gamma voltage signal TDGVS1 to GV8 may decrease linearly with time in one horizontal time 1H.

In yet other embodiments, as illustrated in fig. 8, one horizontal time 1H may be divided into 2 having different time periods^MThe times T1 to T8 are divided by (or 8 in this example, where M is 3). In the present example of fig. 8, the 8 division times T1 to T8 may have gradually increasing periods in one horizontal time 1H. Further, each time-division gamma voltage signal TDGVS may respectively represent 8 gamma voltages GV1 to GV8 having substantially the same voltage interval in 8 division times.

For example, as illustrated in fig. 6, 7 and 8, since 2^N-MThe M-bit DACs 163, 164, …, 166 each generate 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MThus, can be adjusted separately or independently 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-M。

Referring to FIG. 1, 2 generated by the first number module 160^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MMay be provided to a plurality of channels CH, or may pass through 2^N-MTime division gamma voltage line groups TDGLG 1-TDGLG 2^N-MAre provided to a plurality of N-M bit DACs 172 (see fig. 12) of the second submodule 170 in the plurality of channels CH. Further, as illustrated in FIG. 1, 2^N-MTime division gamma voltage line groups TDGLG 1-TDGLG 2^N-MMay include K time-division gamma voltage lines TDGVL (also referred to as K lines in fig. 1), where K is greater than 1 and less than or equal to the number of the channels CH, and the K time-division gamma voltage lines TDGVL of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may transmit 2 time-division gamma voltage lines TDGVL^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MThe same time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS 1).

In the data driver 100 according to the embodiment, the plurality of channels CH may be grouped into K channel groups, and the K time-division gamma voltage lines TDGVL of each time-division gamma voltage line group TDGVLG may be respectively coupled to the K channel groups. Accordingly, each of the time-division gamma voltage lines TDGVL may be coupled to only a portion of the plurality of channels CH. Accordingly, the load of each of the time-division gamma voltage lines TDGVL and the channel CH coupled to each of the time-division gamma voltage lines TDGVL may be reduced, and the delay (e.g., RC delay) of the time-division gamma voltage signal TDGVS transferred through the time-division gamma voltage lines TDGVL may be reduced.

In some embodiments, the plurality of channels CH in the data driver 100 may include K × L channels, where L is an integer greater than 0, and the K × L channels may be grouped into K channel groups such that a K × I + J channel of the K × L channels is grouped into a J channel group of the K channel groups, where I is an integer greater than or equal to 0 and less than L, and J is an integer greater than 0 and less than or equal to K. In this case, the K time-division gamma voltage lines TDGVL may be respectively coupled to the K channel groups such that each of the K time-division gamma voltage lines TDGVL is coupled to a corresponding L channel of the K × L channels.

Referring to fig. 9, each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may include four time-division gamma voltage lines TDGVL as the K time-division gamma voltage lines TDGVL. For example, the first time-division gamma voltage line group TDGVLG1 may include four time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4 for transferring the first time-division gamma voltage signal TDGVS1, the second time-division gamma voltage line group TDGVLG2 may include four time-division gamma voltage lines TDGVL2_1, TDGVL2_2, TDGVL2_3, and TDGVL2_4 for transferring the second time-division gamma voltage signal TDGVS2, and the 2 nd time-division gamma voltage line group TDGVL 3583 may include four time-division gamma voltage lines TDGVL2_1, TDGVL2_2, TDGVL2_3, and TDGVL2_4^N-MTime division gamma voltage line group TDGLG 2^N-MMay include a 2 nd for transmission^N-MTime division gamma voltage signal TDGVS2^N-MFour time division gamma voltage lines TDGVL2^N-M_1、TDGVL2^N-M_2、TDGVL2^N-MR3 and TDGVL2^N-MAnd 4. The 4 × L channels CH1 through CH4L may be grouped into four channel groups CHG1, CHG2, CHG3, and CHG 4. For example, the first channel CH1, the fifth channels CH5, …, and the 4L-3 th channel CH4L-3 may be grouped into a first channel group CHG1, the second channel CH2, the sixth channel CH6, …, and the 4L-2 th channel CH4L-2 may be grouped into a second channel group CHG2, and the third channel group CHG2The channel CH3, the seventh channel CH7, …, and the 4L-1 th channel CH4L-1 may be grouped into a third channel group CHG3, and the fourth channel CH4, the eighth channel CH8, …, and the 4L-1 th channel CH4L may be grouped into a fourth channel group CHG 4. Four time-division gamma voltage lines TDGVL (e.g., time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4) of each time-division gamma voltage line group TDGVLG (e.g., first time-division gamma voltage line group TDGVLG1) may be coupled to the four channel groups CHG1, CHG2, CHG3, and CHG4, respectively. In the example of fig. 9, the second module 170a may include 4 × L N-M bit DACs 211a to 222a in 4 × L channels CH1 to CH4L, the first time division gamma voltage line TDGVL (e.g., the first time division gamma voltage line group TDGVLG 1_1) of each time division gamma voltage line group TDGVLG (e.g., the first time division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 211a, 215a, …, 219a in the channels CH1, CH5, …, CH4L-3 belonging to the first channel group CHG1, the second time division gamma voltage line TDGVL (e.g., the second time division gamma voltage line TDGVLG 1_2) of each time division gamma voltage line group TDGVLG (e.g., the first time division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 211a, 215a, … a, 220a, 216a, 220a, b, the third time-division gamma voltage line TDGVL (e.g., the third time-division gamma voltage line TDGVL1_3) of the first time-division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 213a, 217a, …, 221a in the channels CH3, CH7, …, CH4L-1 belonging to the third channel group CHG3, and the fourth time-division voltage line gamma TDGVL (e.g., the fourth time-division gamma voltage line TDGVL1_4) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 214a, 218a, …, 222a in the channels CH4, CH8, …, CH4L belonging to the fourth channel group CHG 4. That is, each time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) may be coupled to only L channels (e.g., channels CH1, CH5, …, CH4L-3) among the 4 × L channels CH1 to CH 4L. In this case, as illustrated in fig. 10, the time-division gamma voltage line TDGVL for transferring the time-division gamma voltage signal TDGVS is coupled to only the L channels C among the 4 × L channels CH1 to CH4LH1, CH5, …, CH4L-3, so the time-division gamma voltage signal TDGVS may not be affected by all of the 4 × L parasitic capacitors PC1 to PC4L of the 4 × L channels CH1 to CH4L, but may be affected only by the L parasitic capacitors PC1, PC5, tserda, PC4L-3 of the L channels CH1, CH5, tserda, CH 4L-3. Therefore, in the data driver 100 according to the embodiment, the load of each of the time-division gamma voltage lines TDGVL and the channels CH1, CH5, …, CH4L-3 coupled to the time-division gamma voltage line TDGVL may be reduced, and the delay (e.g., RC delay) of the time-division gamma voltage signal TDGVS transmitted through the time-division gamma voltage line TDGVL may be reduced, compared to the case where each of the time-division gamma voltage lines TDGVL is coupled to all of the channels CH1 to CH 4L.

In other embodiments, the plurality of channels CH of the data driver 100 may include K × L channels, and the K × L channels may be grouped into K channel groups such that consecutive L channels of the K × L channels are grouped into the same channel group. In addition, K time-division gamma voltage lines TDGVL may be respectively coupled to the K channel groups. In this case, each of the K time-division gamma voltage lines TDGVL may be coupled to only corresponding L channels of the K × L channels.

Referring to fig. 11, each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may include four time-division gamma voltage lines TDGVL (e.g., time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4) as K time-division gamma voltage lines TDGVL. The 4 × L channels CH1 through CH4L may be grouped into four channel groups CHG1, CHG2, CHG3, and CHG 4. For example, the first to L-th channels CH1 to CHL may be grouped into a first channel group CHG1, the L + 1-L-th channels CHL +1 to CH2L may be grouped into a second channel group CHG2, the 2L + 1-L-th channels CH2L +1 to CH3L may be grouped into a third channel group CHG3, and the 3L + 1-th channels CH3L +1 to CH4L may be grouped into a fourth channel group CHG 4. Four time-division gamma voltage lines TDGVL (e.g., time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4) of each time-division gamma voltage line group TDGVLG (e.g., first time-division gamma voltage line group TDGVLG1) may be coupled to the four channel groups CHG1, CHG2, CHG3, and CHG4, respectively. In the example of fig. 11, the second module 170b may include 4 × L N-M bit DACs 211b to 218b in 4 × L channels CH1 to CH4L, the first time division gamma voltage line TDGVL (e.g., the first time division gamma voltage line group TDGVLG1) of each time division gamma voltage line group TDGVLG (e.g., the first time division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 211b, …, 212b in the channels CH1 to CHL belonging to the first channel group CHG1, the second time division gamma voltage line TDGVL (e.g., the second time division gamma voltage line group TDGVLG 1_2) of each time division gamma voltage line group TDGVLG (e.g., the first time division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 213b, 214b, each time division gamma voltage line group TDGVLG (e.g., the third time division gamma voltage line group TDGVLG 25), the third time-division gamma voltage line TDGVL1_3) may be coupled to the N-M bit DACs 215b, …, 216b in the channels CH2L +1 to CH3L belonging to the third channel group CHG3, and the fourth time-division gamma voltage line TDGVL (e.g., the fourth time-division gamma voltage line TDGVL1_4) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may be coupled to the N-M bit DACs 217b, …, 218b in the channels CH3L +1 to CH4L belonging to the fourth channel group CHG 4. That is, each of the time-division gamma voltage lines TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) may be coupled to only L channels (e.g., the channels CH1 to CHL) among the 4 × L channels CH1 to CH 4L. Accordingly, the load of each of the time-division gamma voltage lines TDGVL and the channels CH1 to CHL coupled thereto may be reduced, and the delay (e.g., RC delay) of the time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) transferred through the time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) may be reduced.

Although fig. 9 and 11 illustrate an example in which each time-division gamma voltage line group TDGVLG includes four time-division gamma voltage lines TDGVL, the number of time-division gamma voltage lines TDGVL included in each time-division gamma voltage line group TDGVLG is not limited to the example of fig. 9 and 11. In addition, fig. 9 and 11 illustrate an example of connecting the time-division gamma voltage line TDGVL and the plurality of channels CH, and the connection relationship between the time-division gamma voltage line TDGVL and the plurality of channels CH is not limited to the example of fig. 9 and 11.

Referring again to fig. 1, the second digital block 170 may receive the high N-M bits of each pixel data PDAT from the retention latch block 130 (through the level shifter block 140), which may be 2^N-MTime division gamma voltage line groups TDGLG 1-TDGLG 2^N-MReceive 2 from first number module 160^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MAnd may be at 2 based on the upper N-M bits of the N bits of the corresponding pixel data PDAT in each channel CH^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MAmong which one time-division gamma voltage signal STDGVS is selected. For example, in the case where N is 10 and M is 4, the second modulo block 170 may time-divide the gamma voltage signals TDGVS1 through TDGVS2 at 64 times according to the upper 6 bits of the pixel data PDAT in each channel CH⁶Among which one time-division gamma voltage signal STDGVS is selected.

In some embodiments, as illustrated in FIG. 12, the second digital module 170 may include a plurality of N-M bit DACs 172 corresponding to the plurality of channels CH, respectively. That is, the number of the plurality of N-M bit DACs 172 in the second numerator module 170 may correspond to the number of the plurality of channels CH. The N-M bit DAC172 in each channel CH may be at 2 according to the high N-M bits of the pixel data PDAT^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MAmong which one time-division gamma voltage signal STDGVS is selected. To perform this operation, the N-M bit DAC172 in each channel CH may include a decoder 174 and a 2^N-MSwitches SW 1-SW 2^N-M. Decoder 174 may generate 2 based on the high N-M bits of pixel data PDAT^N-MSwitching signals SWS 1-SWS 2^N-M。2^N-MSwitches SW 1-SW 2^N-MCan respond to 2 respectively^N-MSwitching signals SWS 1-SWS 2^N-MSelectively output 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-M。2^N-MSwitching signals SWS 1-SWS 2^N-MMay have an on level according to the high N-M bits of the pixel data PDAT, 2^N-MSwitches SW 1-SW 2^N-MCan be turned on in response to a switching signal having a turn-on level, and thus, 2^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MMay be output as the selected time-division gamma voltage signal STDGVS. Although fig. 12 illustrates an example in which the second module 170 is implemented using a decoder type DAC including the decoder 174, the second module 170 may be implemented using a Read Only Memory (ROM) type DAC, a tree type DAC, or any other type of DAC, according to embodiments.

Referring again to fig. 1, the time division gamma voltage selection block 180 may receive the low M bits of each pixel data PDAT from the retention latch block 130 through the level shifter block 140, may receive the selected time division gamma voltage signal STDGVS in each channel CH from the second modulo block 170, and may receive the selected time division gamma voltage signal STDGVS at 2 represented by the selected time division gamma voltage signal STDGVS according to the low M bits of the pixel data PDAT in each channel CH^MGamma voltages (e.g., gamma voltages GV 1-GV 2)^M) Among which one gamma voltage SGV is selected. For example, in the case where N is 10 and M is 4, the time-division gamma voltage selection block 180 may select 16 gamma voltages (e.g., gamma voltages GV1 to GV 2) represented by the selected time-division gamma voltage signal STDGVS according to the lower 4 bits of the pixel data PDAT in each channel CH⁴) Among which one gamma voltage SGV is selected.

In some embodiments, as illustrated in fig. 13, the time-division gamma voltage selection block 180 may include a plurality of switching signal generators 182 respectively corresponding to the plurality of channels CH, and a plurality of time-division gamma voltage selection switches TDSW respectively corresponding to the plurality of channels CH. That is, the number of the plurality of switching signal generators 182 and the number of the plurality of time-division gamma voltage selection switches TDSW may correspond to the number of the plurality of channels CH. The switching signal generator 182 in each channel CH may be 2 at one horizontal time 1H^MDuring a division time corresponding to the lower M-phase of the pixel data PDAT among the division times, the time division switching signal TDSS having an active level (e.g., a high level) is generated. For example, the switching signal generator 182 may receive a clock signal having 2 from the M clock generator 161 or another clock generator during one horizontal time 1H^MM clock signal MCLK of each clock, can calculate the clock of M clock signal MCLK, andand when the number of counted clocks corresponds to a value of the lower M bits of the pixel data PDAT, the time division switching signal TDSS having an active level may be generated. In the example illustrated in fig. 14, where M is 3, one horizontal time 1H is divided into 8 division times, and the value of the lower 3 bits of the pixel data PDAT is 5, the switching signal generator 182 may generate the time division switching signal TDSS having an active level during a fifth division time (e.g., from a time point of 4H/8 to a time point of 5H/8) among the 8 division times in one horizontal time 1H. The time division gamma voltage selection switch TDSW may be responsive to a time division switch signal TDSS having an active level, at 2^MGamma voltages (e.g., gamma voltages GV 1-GV 2)^M) Among which one gamma voltage SGV is selected. In the example illustrated in fig. 14, in which the selected time-division gamma voltage signals STDGVS respectively represent the first to eighth gamma voltages GV1 to GV8 in 8 division times and the time-division switching signal TDSS has an active level during a fifth division time (e.g., from a time point of 4H/8 to a time point of 5H/8) among the 8 division times, the time-division gamma voltage selection switch TDSW may select the fifth gamma voltage GV5 among the first to eighth gamma voltages GV1 to 8 in the fifth division time.

Referring again to fig. 1, the output buffer block 190 may receive the selected gamma voltage SGV in each channel CH from the time division gamma voltage selection block 180 and may output the selected gamma voltage SGV in each channel CH as the data voltage VD. In some embodiments, the output buffer block 190 may include a plurality of output buffers respectively corresponding to the plurality of channels CH.

As described above, the data driver 100 may select 2 according to the high N-M bits of the pixel data PDAT in each channel CH using the second numerator module 170^N-MTime division gamma voltage signals TDGVS 1-TDGVS 2^N-MAnd 2 may be selected according to the lower M bits of the pixel data PDAT in each channel CH using the first number module 160 and the time division gamma voltage selection block 180^MGamma voltages (e.g., gamma voltages GV 1-GV 2)^M) Is selected from the time-division gamma voltage signals STDGVOne of S. Accordingly, the size and power consumption of the data driver 100 may be reduced. Further, in the data driver 100, each of the time-division gamma voltage signals TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) may be transferred to the plurality of channels CH through K time-division gamma voltage lines TDGVL, and each of the time-division gamma voltage lines TDGVL may be coupled to only corresponding portions of the plurality of channels CH. Accordingly, a delay (e.g., RC delay) of each time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) may be reduced, and the time-division gamma voltage signals TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) may be accurately transferred to the plurality of channels CH.

Fig. 15 is a block diagram of a display device including a data driver according to an embodiment, fig. 16 is a circuit diagram of a pixel included in the display device according to the embodiment, and fig. 17 is a circuit diagram of another example of the pixel included in the display device according to the embodiment.

Referring to fig. 15, the display apparatus 400 may include a display panel 410 including a plurality of pixels PX, a SCAN driver 420 supplying a SCAN signal SCAN to the plurality of pixels PX, a data driver 430 supplying a data voltage VD to the plurality of pixels PX, and a controller 440 controlling the SCAN driver 420 and the data driver 430.

The display panel 410 may include scan lines, data lines, and a plurality of pixels PX coupled to the scan lines and the data lines. In some embodiments, the display panel 410 may be an OLED display panel. In this case, each pixel PX may include at least two transistors, at least one capacitor, and an Organic Light Emitting Diode (OLED). Referring to fig. 16, each pixel PX may include a switching transistor PT2 transferring a data voltage VD in response to a SCAN signal SCAN, a storage capacitor CST storing the data voltage VD transferred by the switching transistor PT2, a driving transistor PT1 supplying a driving current from a line of a first power supply voltage ELVDD to a line of a second power supply voltage ELVSS based on the data voltage VD stored in the storage capacitor CST, and an organic light emitting diode EL emitting light based on the driving current supplied by the driving transistor PT 1. In some embodiments, as illustrated in fig. 16, the driving transistor PT1 and the switching transistor PT2 may be implemented with PMOS transistors. In other embodiments, as illustrated in fig. 17, the driving transistor NT1 and the switching transistor NT2 may be implemented with NMOS transistors. In still other embodiments, each pixel PX may include at least one PMOS transistor and at least one NMOS transistor. In other embodiments, the display panel 410 may be a Liquid Crystal Display (LCD) panel. In this case, each pixel PX may include a switching transistor and a liquid crystal capacitor coupled to the switching transistor. However, the display panel 410 may not be limited to the OLED panel and the LCD panel, and the display panel 410 may be any suitable display panel for displaying an image.

The SCAN driver 420 may generate the SCAN signal SCAN based on the SCAN control signal SCTRL received from the controller 440, and may sequentially supply the SCAN signal SCAN to the plurality of pixels PX row by row through the SCAN lines. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal (e.g., the start signal STS of fig. 1), a scan clock signal (e.g., the clock signal CLK of fig. 1), and the like. In some embodiments, the scan driver 420 may be integrated or formed in a peripheral portion of the display panel 410. In other embodiments, the scan driver 420 may be implemented in the form of an Integrated Circuit (IC).

The data driver 430 may generate the data voltage VD based on the output image data ODAT (or the pixel data PDAT) and the data control signal DCTRL received from the controller 440, and may supply the data voltage VD to the plurality of pixels PX through the data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, the start signal STS, the clock signal CLK, and the LOAD signal LOAD in fig. 1. In some embodiments, the data driver 430 and the controller 440 may be implemented in a single integrated circuit referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 430 and the controller 440 may be implemented in separate integrated circuits.

In some embodiments, the data driver 430 may be the data driver 100 of fig. 1. The data driver 430 may use the second numerator 170 according to each channelHigh N-M bits of pixel data PDAT in CH to select 2^N-MOne of the time division gamma voltage signals TDGVS, and 2 may be selected according to the lower M bits of the pixel data PDAT in each channel CH using the first number block 160 and the time division gamma voltage selection block 180^MOne of the gamma voltages represented by the selected time-division gamma voltage signal STDGVS. Accordingly, the size and power consumption of the data driver 430 may be reduced. Further, in the data driver 430, each of the time-division gamma voltage signals TDGVS may be transferred to the plurality of channels CH through the K time-division gamma voltage lines TDGVL, and each of the time-division gamma voltage lines TDGVL may be coupled to only corresponding portions of the plurality of channels CH. Accordingly, a delay (e.g., RC delay) of each time-division gamma voltage signal TDGVS may be reduced, and the time-division gamma voltage signals TDGVS may be accurately transferred to the plurality of channels CH.

The controller 440 (e.g., a Timing Controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host (e.g., a Graphics Processing Unit (GPU), a graphics card, etc.). For example, the input image data IDAT may be, but is not limited to, RGB image data including red image data, green image data, and blue image data. Further, the control signal CTRL may include, but is not limited to, a data enable signal, a master clock signal, and the like. The controller 440 may generate output image data ODAT, a data control signal DCTRL, and a scan control signal SCTRL based on the input image data IDAT and the control signal CTRL. The controller 440 may control the operation of the scan driver 420 by supplying a scan control signal SCTRL to the scan driver 420, and may control the operation of the data driver 430 by supplying output image data ODAT and a data control signal DCTRL to the data driver 430.

As described above, in the display device 400 according to the embodiment, the data driver 430 may perform the N-M bit gamma voltage selection operation in the spatial division scheme according to the upper N-M bits of the pixel data PDAT using the second number module 170, and may perform the M bit gamma voltage selection operation in the time division scheme according to the lower M bits of the pixel data PDAT using the first number module 160 and the time division gamma voltage selection block 180. Accordingly, the size and power consumption of the data driver 430 may be reduced. Further, in the data driver 430, each of the time-division gamma voltage signals TDGVS may be transferred to the plurality of channels CH through the K time-division gamma voltage lines TDGVL. Accordingly, the delay of each time-division gamma voltage signal TDGVS can be reduced, and the time-division gamma voltage signals TDGVS can be accurately transferred to the plurality of channels CH.

Fig. 18 is a block diagram of an electronic device including a display device according to an embodiment.

Referring to fig. 18, an electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input/output (I/O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with various peripheral devices including, but not limited to, video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, other electronic devices, and the like.

Processor 1110 may perform various computing functions or tasks. The processor 1110 may be an Application Processor (AP), a microprocessor, a Central Processing Unit (CPU), or the like. The processor 1110 may be coupled to the other components of the electronic device 1100 via an address bus, a control bus, a data bus, and the like. Further, in some embodiments, processor 1110 may be further coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 1120 may store data used to operate the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an Erasable Programmable Read Only Memory (EPROM) device, an Electrically Erasable Programmable Read Only Memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a Resistive Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a polymer random access memory (ponam) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, etc., and/or at least one volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

The storage device 1130 may be a Solid State Drive (SSD) device, a Hard Disk Drive (HDD) device, a CD-ROM device, or the like. I/O devices 1140 may be input devices such as a keyboard, keypad, mouse, touch screen, etc., and output devices such as a printer, speakers, etc. The power supply 1150 may supply power for operating the electronic device 1100. Display device 1160 may be coupled to other components by a bus or other communication link.

Display device 1160 may be display device 400 of fig. 15. The display device 1160 includes a data driver that performs an N-M bit gamma voltage selection operation in a spatial division scheme according to the upper N-M bits of the pixel data PDAT using the second number module 170, and may perform an M bit gamma voltage selection operation in a time division scheme according to the lower M bits of the pixel data PDAT using the first number module 160 and the time division gamma voltage selection block 180. Accordingly, the size and power consumption of the display device 1160 can be reduced. Further, in the display device 1160, each of the time-division gamma voltage signals TDGVS may be transferred to the plurality of channels CH through the K time-division gamma voltage lines TDGVL. Accordingly, the delay of each time-division gamma voltage signal TDGVS can be reduced, and the time-division gamma voltage signals TDGVS can be accurately transferred to the plurality of channels CH.

According to an embodiment, the electronic device 1100 may be any electronic device including the display device 1160, such as a digital television, a three-dimensional (3D) television, a Personal Computer (PC), a home appliance, a notebook computer, a mobile phone, a smart phone, a tablet computer, a wearable device, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a digital camera, a music player, a portable game console, a navigation system, and the like.

The foregoing is illustrative of embodiments of the present disclosure and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications and/or alterations may be made in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, such variations and/or modifications are intended to be included within the scope of the inventive concept of the present disclosure, including the following claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications and/or alterations to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the present disclosure, including the appended claims.