阅读说明：本技术 显示面板 (Display panel ) 是由 刘念 卢马才 冯铮宇 梅雪茹 柳铭岗 于 2021-07-07 设计创作，主要内容包括：本申请公开了一种显示面板,通过设置LED芯片的P电极与N电极的高度差,与阵列基板的第一像素电极与第二像素电极的高度差相同,使得第一像素电极所受到P电极的力度,与第二像素电极所受到N电极的力度是相同的,从而有利于提高所述LED芯片和阵列基板的绑定良率。(The application discloses display panel, through the difference in height of the P electrode that sets up the LED chip and N electrode, it is the same with the difference in height of array substrate's first pixel electrode and second pixel electrode for the dynamics that first pixel electrode received the P electrode is the same with the dynamics that second pixel electrode received the N electrode, thereby is favorable to improving LED chip and array substrate's the yield of binding.)

1. A display panel is characterized by comprising an LED chip and an array substrate which are mutually bonded and pressed;

the LED chip includes:

a substrate; and

a first electrode part and a second electrode part protruding from the upper surface of the substrate;

wherein the height of the second electrode portion is lower than the height of the first electrode portion;

the array substrate includes:

the substrate layer is provided with a laminating groove;

the first pixel electrode is arranged in the laminating groove;

the second pixel electrode is arranged on the upper surface of the substrate layer; and

an anisotropic conductive film disposed on the substrate layer, the first pixel electrode, and the second pixel electrode;

when the LED chip and the array substrate are bonded and pressed with each other, the first electrode part is pressed to the pressing groove and connected to the first pixel electrode; the second electrode portion is connected to the second pixel electrode.

2. The display panel according to claim 1,

a height difference between the second electrode portion and the first electrode portion is the same as a height difference between the first pixel electrode and the second pixel electrode;

the height of the first electrode part is the same as the depth of the pressing groove.

3. The display panel of claim 1, wherein the substrate layer comprises:

a glass substrate;

a light shielding layer disposed on the glass substrate;

the buffer layer covers the light shielding layer and extends to the glass substrate;

the active layer is arranged on the buffer and is right opposite to part of the light shielding layer;

a gate insulating layer disposed on the active layer;

the first metal layer is arranged on the grid insulation layer;

a dielectric layer covering the first metal layer and extending to the active layer and the buffer layer;

a first via penetrating from the dielectric layer to a surface of the active layer;

a second via penetrating from the dielectric layer to a surface of the active layer;

the third through hole is formed in one side, far away from the first through hole, of the second through hole, and penetrates from the dielectric layer to the surface of the light shielding layer; and

the fourth through hole is formed in one side, far away from the first through hole, of the third through hole, and penetrates from the dielectric layer to the surface of the light shielding layer;

the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; wherein the source trace is connected to the active layer through the first via; the drain electrode routing is connected to the active layer through the second through hole, and the drain electrode is connected to the light shielding layer through the third through hole; the VDD routing is arranged at the bottom of the fourth through hole and connected to the light shielding layer, wherein a groove is formed by the upper surface of the VDD routing and the side wall of the fourth through hole in a surrounding mode; the VSS wire is arranged on the dielectric layer and is far away from one side of the first through hole; and

and the passivation layer is arranged on the dielectric layer and covers the source electrode wire and the drain electrode wire.

4. The display panel according to claim 3,

the first pixel electrode is arranged in the groove, is connected to the VDD wiring, and extends from the side wall to the bottom wall of the groove to form the laminating groove;

the second pixel electrode is arranged on the VSS wire and extends to the surface of part of the passivation layer.

5. The display panel of claim 1, wherein the substrate layer comprises:

a glass substrate;

a light shielding layer disposed on the glass substrate;

the buffer layer covers the light shielding layer and extends to the glass substrate;

the active layer is arranged on the buffer and is right opposite to part of the light shielding layer;

the grid insulation layer is arranged on the active layer and the buffer layer;

the first metal layer comprises a first grid and a second grid, and the first metal layer is arranged on the grid insulating layer;

a dielectric layer covering the first metal layer and extending to the active layer and the buffer layer;

a first via penetrating from the dielectric layer to a surface of the active layer;

a second via penetrating from the dielectric layer to a surface of the active layer;

the third through hole is formed in one side, far away from the first through hole, of the second through hole, and penetrates from the dielectric layer to the surface of the light shielding layer; and

the fourth through hole is arranged on one side, far away from the first through hole, of the third through hole, and penetrates from the dielectric layer to the surface of the second grid electrode;

the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; wherein the source trace is connected to the active layer through the first via; the drain electrode routing is connected to the active layer through the second through hole, and the drain electrode is connected to the light shielding layer through the third through hole; the VDD routing is arranged at the bottom of the fourth through hole and connected to the second grid, wherein a groove is formed by the upper surface of the VDD routing and the side wall of the fourth through hole in a surrounding mode; the VSS wire is arranged on the dielectric layer and is far away from one side of the first through hole; and

and the passivation layer is arranged on the dielectric layer and covers the source electrode wire and the drain electrode wire, and is provided with a fifth through hole which penetrates through the surface of the VSS wire.

6. The display panel according to claim 5,

the first pixel electrode is arranged in the groove and connected to the VDD wiring, wherein the upper surface of the first pixel electrode and the side wall of the groove form the laminating groove;

the second pixel electrode is connected to the VSS trace through the fifth via and extends to the surface of the passivation layer.

7. The display panel of claim 1, wherein the substrate layer comprises:

a glass substrate;

the first metal layer is arranged on the glass substrate and is patterned to form a grid and a VDD wire;

the grid insulation layer is arranged on the glass substrate and covers the grid;

the active layer is arranged on the gate insulating layer and is opposite to the gate;

the insulating layer is arranged on the gate insulating layer and covers the active layer;

a sixth via penetrating from the insulating layer to a surface of the active layer;

a seventh via penetrating from the insulating layer to a surface of the active layer;

the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; wherein the source trace is connected to the active layer through the sixth via; the drain electrode routing is connected to the active layer through the seventh through hole and extends to the VDD routing; the VSS wiring is arranged on the insulating layer; and

and the passivation layer is arranged on the insulating layer and covers the source electrode wire and part of the drain electrode wire.

8. The display panel according to claim 7,

the first pixel electrode extends from the side wall of the passivation layer to the side wall of the drain electrode routing, is connected to the VDD routing, and forms the laminating groove;

the second pixel electrode is arranged on the passivation layer and extends to a part of the passivation layer.

9. The display panel of claim 1, wherein the substrate layer comprises:

a glass substrate;

the first metal layer is arranged on the glass substrate and is patterned to form a first grid and a second grid;

the grid insulation layer is arranged on the glass substrate and covers the first grid;

the active layer is arranged on the grid insulation layer and is opposite to the first grid;

an eighth through hole penetrating from the gate insulating layer to the surface of the glass substrate;

the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; the source electrode routing and the drain electrode routing are respectively arranged on two sides of the active layer and extend to the surface of the gate insulation layer; the VDD routing is arranged at the bottom of the eighth through hole and is connected to the second gate, wherein a groove is formed by the upper surface of the VDD routing and the side wall of the eighth through hole in a surrounding manner; the VSS wiring is arranged on the grid insulation layer; and

the passivation layer is arranged on the insulating layer and covers the source electrode wire and part of the drain electrode wire;

the first pixel electrode extends from the side wall of the passivation layer to the VDD routing, and the upper surface of the VDD routing and the side wall of the eighth through hole enclose the pressing groove; the second pixel electrode is arranged on the VSS wire and extends to a part of the passivation layer.

10. The display panel according to claim 1, wherein the LED chip comprises:

the epitaxial layer is arranged on the substrate;

the P electrode is arranged on a P type layer of the epitaxial layer; and

the N electrode is arranged on an N type layer of the epitaxial layer;

the P electrode and the epitaxial layer form a first electrode part, and the N electrode and the epitaxial layer form a second electrode part.

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

The Micro LED display technology is considered as a next generation novel display technology due to the advantages of high brightness, low voltage, low energy consumption, good stability, long service life, wide color gamut and the like, and is expected to be widely applied in various fields. Currently, the LED chip of the horizontal structure has advantages in circuit design and bonding (bonding) process of the panel. However, the P-electrode and the N-electrode of the LED chip have a difference in height, and thus the P-electrode and the N-electrode are subjected to different pressures when the LED chip is bonded, which causes a bonding contact failure at the N-electrode and forms a dark spot.

Specifically, there is a height difference of about 1um between the P electrode and the N electrode of the horizontal LED chip, and the diameter of the Conductive particles in the Anisotropic Conductive Film (ACF) is generally between 2 to 3 um. The VDD electrode, the VSS electrode and the source drain electrode layer in the array substrate are arranged in the same layer and are formed by etching the same metal layer.

As shown in fig. 1, when the LED chip 10 is bonded to the array substrate 20, under the combined action of temperature, pressure and time, the ACF conductive particles achieve conduction between the LED chip and the array substrate in the vertical direction and insulation in the horizontal direction. However, due to the height difference between the P electrode and the N electrode, in the process of pressing the LED chip and the array substrate, the P electrode is pressed to the VDD electrode of the array substrate first, and the N electrode and the VSS electrode have a height difference of 1 um.

Therefore, in the process of binding the LED chip and the array substrate, a risk of poor contact between the N electrode and the VSS electrode is easily caused, a large number of dark spots are formed, and the quality of the display panel is affected.

Disclosure of Invention

The invention aims to provide a display panel to solve the technical problem of poor contact caused by a height difference between an N electrode and a VSS electrode in the binding process of an LED chip and an array substrate.

In order to achieve the above object, the present invention provides a display panel, which includes an LED chip and an array substrate bonded and pressed to each other; the LED chip includes: a substrate; and a first electrode portion and a second electrode portion protruding from an upper surface of the substrate; wherein the height of the second electrode portion is lower than the height of the first electrode portion; the array substrate includes: the substrate layer is provided with a laminating groove; the first pixel electrode is arranged in the laminating groove; the second pixel electrode is arranged on the upper surface of the substrate layer; and an anisotropic conductive film disposed on the substrate layer, the first pixel electrode, and the second pixel electrode; when the LED chip and the array substrate are bonded and pressed with each other, the first electrode part is pressed to the pressing groove and connected to the first pixel electrode; the second electrode portion is connected to the second pixel electrode.

Further, a height difference between the second electrode portion and the first electrode portion is the same as a height difference between the first pixel electrode and the second pixel electrode; the height of the first electrode part is the same as the depth of the pressing groove.

Further, the substrate layer includes: a glass substrate; a light shielding layer disposed on the glass substrate; the buffer layer covers the light shielding layer and extends to the glass substrate; the active layer is arranged on the buffer and is right opposite to part of the light shielding layer; a gate insulating layer disposed on the active layer; the first metal layer is arranged on the grid insulation layer; a dielectric layer covering the first metal layer and extending to the active layer and the buffer layer; a first via penetrating from the dielectric layer to a surface of the active layer; a second via penetrating from the dielectric layer to a surface of the active layer; the third through hole is formed in one side, far away from the first through hole, of the second through hole, and penetrates from the dielectric layer to the surface of the light shielding layer; the fourth through hole is formed in one side, far away from the first through hole, of the third through hole, and penetrates from the dielectric layer to the surface of the light shielding layer; the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; wherein the source trace is connected to the active layer through the first via; the drain electrode routing is connected to the active layer through the second through hole, and the drain electrode is connected to the light shielding layer through the third through hole; the VDD routing is arranged at the bottom of the fourth through hole and connected to the light shielding layer, wherein a groove is formed by the upper surface of the VDD routing and the side wall of the fourth through hole in a surrounding mode; the VSS wire is arranged on the dielectric layer and is far away from one side of the first through hole; and the passivation layer is arranged on the dielectric layer and covers the source electrode wire and the drain electrode wire.

Furthermore, the first pixel electrode is arranged in the groove, connected to the VDD trace, and extends from the sidewall to the bottom wall of the groove to form the laminating groove; the second pixel electrode is arranged on the VSS wire and extends to the surface of part of the passivation layer.

Further, the substrate layer includes: a glass substrate; a light shielding layer disposed on the glass substrate; the buffer layer covers the light shielding layer and extends to the glass substrate; the active layer is arranged on the buffer and is right opposite to part of the light shielding layer; the grid insulation layer is arranged on the active layer and the buffer layer; the first metal layer comprises a first grid and a second grid, and the first metal layer is arranged on the grid insulating layer; a dielectric layer covering the first metal layer and extending to the active layer and the buffer layer; a first via penetrating from the dielectric layer to a surface of the active layer; a second via penetrating from the dielectric layer to a surface of the active layer; the third through hole is formed in one side, far away from the first through hole, of the second through hole, and penetrates from the dielectric layer to the surface of the light shielding layer; the fourth through hole is arranged on one side, far away from the first through hole, of the third through hole, and penetrates from the dielectric layer to the surface of the second grid electrode; the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; wherein the source trace is connected to the active layer through the first via; the drain electrode routing is connected to the active layer through the second through hole, and the drain electrode is connected to the light shielding layer through the third through hole; the VDD routing is arranged at the bottom of the fourth through hole and connected to the second grid, wherein a groove is formed by the upper surface of the VDD routing and the side wall of the fourth through hole in a surrounding mode; the VSS wire is arranged on the dielectric layer and is far away from one side of the first through hole; and the passivation layer is arranged on the dielectric layer and covers the source electrode wire and the drain electrode wire, and is provided with a fifth through hole which penetrates through the surface of the VSS wire.

Further, the first pixel electrode is disposed in the groove and connected to the VDD trace, wherein the upper surface of the first pixel electrode and the sidewall of the groove form the laminating groove; the second pixel electrode is connected to the VSS trace through the fifth via and extends to the surface of the passivation layer.

Further, the substrate layer includes: a glass substrate; the first metal layer is arranged on the glass substrate and is patterned to form a grid and a VDD wire; the grid insulation layer is arranged on the glass substrate and covers the grid; the active layer is arranged on the gate insulating layer and is opposite to the gate; the insulating layer is arranged on the gate insulating layer and covers the active layer; a sixth via penetrating from the insulating layer to a surface of the active layer; a seventh via penetrating from the insulating layer to a surface of the active layer; the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; wherein the source trace is connected to the active layer through the sixth via; the drain electrode routing is connected to the active layer through the seventh through hole and extends to the VDD routing; the VSS wiring is arranged on the insulating layer; and the passivation layer is arranged on the insulating layer and covers the source electrode wire and part of the drain electrode wire.

Further, the first pixel electrode extends from the side wall of the passivation layer to the side wall of the drain trace and is connected to the VDD trace to form the lamination groove; the second pixel electrode is arranged on the passivation layer and extends to a part of the passivation layer.

Further, the substrate layer includes: a glass substrate; the first metal layer is arranged on the glass substrate and is patterned to form a first grid and a second grid; the grid insulation layer is arranged on the glass substrate and covers the first grid; the active layer is arranged on the grid insulation layer and is opposite to the first grid; an eighth through hole penetrating from the gate insulating layer to the surface of the glass substrate; the second metal layer is patterned to form a source electrode wire, a drain electrode wire, a VDD wire and a VSS wire; the source electrode routing and the drain electrode routing are respectively arranged on two sides of the active layer and extend to the surface of the gate insulation layer; the VDD routing is arranged at the bottom of the eighth through hole and is connected to the second gate, wherein a groove is formed by the upper surface of the VDD routing and the side wall of the eighth through hole in a surrounding manner; the VSS wiring is arranged on the grid insulation layer; the passivation layer is arranged on the insulating layer and covers the source electrode wire and part of the drain electrode wire; the first pixel electrode extends from the side wall of the passivation layer to the VDD routing, and the upper surface of the VDD routing and the side wall of the eighth through hole enclose the pressing groove; the second pixel electrode is arranged on the VSS wire and extends to a part of the passivation layer.

Further, the LED chip includes: the epitaxial layer is arranged on the substrate; the P electrode is arranged on a P type layer of the epitaxial layer; the N electrode is arranged on the N type layer of the epitaxial layer; the P electrode and the epitaxial layer form a first electrode part, and the N electrode and the epitaxial layer form a second electrode part.

The technical effect of the invention is that the height difference between the P electrode and the N electrode of the LED chip is equal to the height difference between the first pixel electrode and the second pixel electrode of the array substrate, so that the force applied to the P electrode by the first pixel electrode is equal to the force applied to the N electrode by the second pixel electrode, thereby improving the bonding yield of the LED chip and the array substrate.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a conventional display panel.

Fig. 2 is a schematic structural diagram of a display panel provided in embodiment 1 of the present application.

Fig. 3 is a schematic structural diagram of an LED chip and an array substrate bonded and pressed according to embodiment 1 of the present application.

Fig. 4 is a schematic structural diagram of a display panel provided in embodiment 2 of the present application.

Fig. 5 is a schematic structural diagram of a display panel provided in embodiment 3 of the present application.

Fig. 6 is a schematic structural diagram of a display panel provided in embodiment 4 of the present application.

The components of the drawings are identified as follows:

100a, 100b, 100c, 100d display panels;

10. an LED chip; 20. An array substrate;

101. a substrate; 102. An epitaxial layer;

103. a P electrode; 104. An N electrode;

1021. an N-type layer; 1022. A light emitting layer;

1023. a P-type layer; 1024. An ITO transparent conductive layer;

21. a substrate layer; 22. A first pixel electrode;

23. a second pixel electrode; 24. An anisotropic conductive film;

201. a glass substrate; 202. A light-shielding layer;

203. a buffer layer; 204. An active layer;

205. a gate insulating layer; 206. A first metal layer;

207. a dielectric layer; 208. A second metal layer;

209. a passivation layer; 208a, source routing;

208b, drain routing; 208c, VDD routing;

208d, VSS wiring; 206a, a first gate;

206b, a second gate; 40. A pressing groove;

41. a first through hole; 42. A second through hole;

43. a third through hole; 44. A fourth via hole;

45. a groove; 46. A fifth through hole;

47. a sixth through hole; 48. A seventh via hole;

49. an eighth via.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Example 1

As shown in fig. 2, the present embodiment provides a display panel 100a, which includes an LED chip 10 and an array substrate 20 bonded and pressed to each other.

The LED chip 10 includes a substrate 101, an epitaxial layer 102, a P electrode 103, and an N electrode 104.

The epitaxial layer 102 is disposed on the substrate 101, and the epitaxial layer 102 includes an N-type layer 1021, a light emitting layer 1022, a P-type layer 1023, and an ITO transparent conductive layer 1024. The N-type layer 1021 is arranged on the substrate 101; the light emitting layer 1022 is provided on the N-type layer 1021; the N electrode 104 is disposed on the N-type layer 1021; the P-type layer 1023 is provided over the light emitting layer 1022; the ITO transparent conductive layer 1024 is disposed on the P-type layer 1023 and extends to the N-type layer 1021; the P-electrode 103 is connected to the P-type layer 1023 through the ITO transparent conductive layer 1024.

In this embodiment, the P electrode 103 and the epitaxial layer 102 form a first electrode portion, and the N electrode 104 and the epitaxial layer 102 form a second electrode portion. Wherein the height of the second electrode part is lower than that of the first electrode part, the height difference between the second electrode part and the first electrode part is 0.8-1.2 μm, and preferably the height difference between the second electrode part and the first electrode part is 1 μm.

The array substrate 20 includes a substrate layer 21, a first pixel electrode 22, a second pixel electrode 23, and an anisotropic conductive film 24.

The substrate layer 21 is provided with a laminating groove 40, and the first pixel electrode 22 is arranged in the laminating groove 40. The second pixel electrode 23 is disposed on the upper surface of the substrate layer 21. The anisotropic conductive film 24 is provided on the substrate layer 21, the first pixel electrode 22, and the second pixel electrode 23.

In this embodiment, the height difference between the second electrode portion and the first electrode portion is the same as the height difference between the first pixel electrode 22 and the second pixel electrode 23, and the height of the first electrode portion is the same as the depth of the pressing groove.

As shown in fig. 3, when the LED chip 10 and the array substrate 20 are bonded and pressed to each other, the first electrode portion is pressed to the pressing groove 40 and connected to the first pixel electrode 22, and the second electrode portion is connected to the second pixel electrode 23, so that when the P electrode 103 and the N electrode 104 are pressed simultaneously, the stress is uniform, and the bonding yield is improved.

Specifically, the substrate layer 21 includes a glass substrate 201, a light shielding layer 202, a buffer layer 203, an active layer 204, a gate insulating layer 205, a first metal layer 206, a dielectric layer 207, a second metal layer 208, and a passivation layer 209.

The light-shielding layer 202 is provided on the glass substrate 201.

The buffer layer 203 covers the light-shielding layer 202 and extends to the glass substrate 201.

The active layer 204 is disposed on the buffer and faces a portion of the light-shielding layer 202.

The gate insulating layer 205 is disposed on the active layer 204.

The first metal layer 206 is disposed on the gate insulating layer 205. Wherein the first metal layer 206 is a gate.

The dielectric layer 207 covers the first metal layer 206 and extends to the active layer 204 and the buffer layer 203.

The substrate layer 21 is provided with a plurality of through holes. Wherein the first via 41 penetrates from the dielectric layer 207 to the surface of the active layer 204. The second via 42 penetrates from the dielectric layer 207 to the surface of the active layer 204. The third through hole 43 is disposed on a side of the second through hole 42 away from the first through hole 41, and the third through hole 43 penetrates from the dielectric layer 207 to the surface of the light-shielding layer 202. The fourth through hole 44 is disposed on a side of the third through hole 43 away from the first through hole 41, and the fourth through hole 44 penetrates from the dielectric layer 207 to the surface of the light-shielding layer 202.

The second metal layer 208 is patterned to form a source trace 208a, a drain trace 208b, a VDD trace 208c, and a VSS trace 208 d.

In this embodiment, the source trace 208a is connected to the active layer 204 through the first via 41; the drain trace 208b is connected to the active layer 204 through the second via 42, and the drain is connected to the light-shielding layer 202 through the third via 43; the VDD routing line 208c is disposed at the bottom of the fourth through hole 44 and connected to the light shielding layer 202, wherein a groove 45 is defined by an upper surface of the VDD routing line 208c and a sidewall of the fourth through hole 44; the VSS trace 208d is disposed on the dielectric layer 207 and on a side away from the first via 41. The thickness of the VDD trace 208c is the same as the thickness of the VSS trace 208 d.

The passivation layer 209 is disposed on the dielectric layer 207 and covers the source trace 208a and the drain trace 208 b.

In this embodiment, the first pixel electrode 22 is disposed in the groove 45, connected to the VDD trace 208c, and extends from the sidewall to the bottom wall of the groove 45 to form the pressing groove 40; the second pixel electrode 23 is disposed on the VSS trace 208d and extends to a portion of the surface of the passivation layer 209. When the LED chip 10 and the array substrate 20 are bonded and pressed to each other, the height difference between the second electrode portion and the first electrode portion is the same as the height difference between the first pixel electrode 22 and the second pixel electrode 23, so that the force applied to the first pixel electrode 22 by the P electrode 103 is the same as the force applied to the second pixel electrode 23 by the N electrode 104, which is beneficial to improving the bonding yield of the LED chip 10 and the array substrate 20. In addition, in the pressing process, ACF ions in the anisotropic conductive film 24 burst, so that the P electrode 103 of the LED chip 10 and the first pixel electrode 22 are conducted with each other, and the N electrode 104 and the second pixel electrode 23 are conducted with each other, so that the LED chip 10 and the array substrate 20 are conducted with each other, and poor contact between the upper and lower electrodes is prevented, and a large number of dark spots are prevented from being formed on the display panel 100 a.

Example 2

The present embodiment provides a display panel, which includes most of the technical solutions of embodiment 1, and is different in structure of the array substrate.

As shown in fig. 4, the present embodiment provides a display panel 100b, wherein the array substrate 20 includes a glass substrate 201, a light shielding layer 202, a buffer layer 203, an active layer 204, a gate insulating layer 205, a first metal layer 206, a dielectric layer 207, a second metal layer 208, and a passivation layer 209.

The light-shielding layer 202 is provided on the glass substrate 201.

The buffer layer 203 covers the light-shielding layer 202 and extends to the glass substrate 201.

The active layer 204 is disposed on the buffer and faces a portion of the light-shielding layer 202.

The gate insulating layer 205 is disposed on the active layer 204 and on the buffer layer 203.

The first metal layer 206 includes a first gate 206a and a second gate 206b, and the first metal layer 206 is disposed on the gate insulating layer 205.

The dielectric layer 207 covers the first metal layer 206 and extends to the active layer 204 and the buffer layer 203.

The substrate layer 21 further comprises a plurality of through holes. Wherein the first via 41 penetrates from the dielectric layer 207 to the surface of the active layer 204. The second via 42 penetrates from the dielectric layer 207 to the surface of the active layer 204. The third through hole 43 is disposed on a side of the second through hole 42 away from the first through hole 41, and the third through hole 43 penetrates from the dielectric layer 207 to the surface of the light-shielding layer 202. A fourth via 44 is disposed at a side of the third via 43 away from the first via 41, and the fourth via 44 penetrates from the dielectric layer 207 to a surface of the second gate 206 b.

The second metal layer 208 is patterned to form a source trace 208a, a drain trace 208b, a VDD trace 208c, and a VSS trace 208 d. Wherein the source trace 208a is connected to the active layer 204 through the first via 41; the drain trace 208b is connected to the active layer 204 through the second via 42, and the drain is connected to the light-shielding layer 202 through the third via 43; the VDD routing 208c is disposed at the bottom of the fourth through hole 44 and connected to the second gate 206b, wherein a groove 45 is defined by an upper surface of the VDD routing 208c and a sidewall of the fourth through hole 44; the VSS trace 208d is disposed on the dielectric layer 207 and on a side away from the first via 41.

The passivation layer 209 is disposed on the dielectric layer 207 and covers the source trace 208a and the drain trace 208b, and the passivation layer 209 has a fifth through hole 46 penetrating to the surface of the VSS trace 208 d.

In this embodiment, the first pixel electrode 22 is disposed in the groove 45 and connected to the VDD trace 208c, wherein the upper surface of the first pixel electrode 22 and the sidewall of the groove 45 form the pressing groove 40; the second pixel electrode 23 is connected to the VSS trace 208d through the fifth via 46 and extends to the surface of the passivation layer 209, or the second pixel electrode 23 is disposed on the VSS trace 208d and extends to the surface of the passivation layer 209 (not shown).

The first pixel electrode 22 is disposed in the groove 45 and connected to the VDD trace 208c, wherein the upper surface of the first pixel electrode 22 and the sidewall of the groove 45 form the pressing groove 40; the second pixel electrode 23 is connected to the VSS wiring 208d through the fifth via and extends to the surface of the passivation layer 209.

When the LED chip 10 and the array substrate 20 are bonded and pressed to each other, the height difference between the second electrode portion and the first electrode portion is the same as the height difference between the first pixel electrode 22 and the second pixel electrode 23, so that the force applied to the first pixel electrode 22 by the P electrode 103 is the same as the force applied to the second pixel electrode 23 by the N electrode 104, which is beneficial to improving the bonding yield of the LED chip 10 and the array substrate 20. In addition, in the pressing process, ACF ions in the anisotropic conductive film 24 burst, so that the P electrode 103 of the LED chip 10 and the first pixel electrode 22 are conducted with each other, and the N electrode 104 and the second pixel electrode 23 are conducted with each other, so that the LED chip 10 and the array substrate 20 are conducted with each other, and poor contact between the upper and lower electrodes is prevented, and a large number of dark spots are prevented from being formed on the display panel 100 a.

Example 3

This embodiment provides a display panel, which includes the technical solution of the LED chip described in embodiment 1, and is different in the structure of the substrate layer.

As shown in fig. 5, the array substrate 20 includes a glass substrate 201, a first metal layer 206, a gate insulating layer 205, an active layer 204, an insulating layer 300, a second metal layer 208, and a passivation layer 209.

The first metal layer 206 is disposed on the glass substrate 201 and patterned to form a gate and a VDD trace 208 c.

The gate insulating layer 205 is disposed on the glass substrate 201 and covers the gate.

The active layer 204 is disposed on the gate insulating layer 205 and opposite to the gate.

The insulating layer 300 is disposed on the gate insulating layer 205 and covers the active layer 204.

The array substrate 20 further includes a plurality of through holes. Wherein the sixth via 47 penetrates from the insulating layer 300 to the surface of the active layer 204. The seventh via hole 48 penetrates from the insulating layer 300 to the surface of the active layer 204.

The second metal layer 208 is patterned to form a source trace 208a, a drain trace 208b, a VDD trace 208c, and a VSS trace 208 d. Wherein the source trace 208a is connected to the active layer 204 through the sixth via 47; the drain trace 208b is connected to the active layer 204 through the seventh via 48 and extends onto the VDD trace 208 c; the VSS trace 208d is disposed on the insulating layer 300.

The passivation layer 209 is disposed on the insulating layer 300 and covers the source trace 208a and a portion of the drain trace 208 b.

The first pixel electrode 22 extends from the sidewall of the passivation layer 209 to the sidewall of the drain trace 208b and is connected to the VDD trace 208c to form the lamination groove 40; the second pixel electrode 23 is disposed on the passivation layer 209 and extends to a portion of the passivation layer 209.

When the LED chip 10 and the array substrate 20 are bonded and pressed to each other, the height difference between the second electrode portion and the first electrode portion is the same as the height difference between the first pixel electrode 22 and the second pixel electrode 23, so that the force applied to the first pixel electrode 22 by the P electrode 103 is the same as the force applied to the second pixel electrode 23 by the N electrode 104, which is beneficial to improving the bonding yield of the LED chip 10 and the array substrate 20. In addition, in the pressing process, ACF ions in the anisotropic conductive film 24 burst, so that the P electrode 103 of the LED chip 10 and the first pixel electrode 22 are conducted with each other, and the N electrode 104 and the second pixel electrode 23 are conducted with each other, so that the LED chip 10 and the array substrate 20 are conducted with each other, and poor contact between the upper and lower electrodes is prevented, and a large number of dark spots are prevented from being formed on the display panel 100 a.

Example 4

The present embodiment provides a display panel, which includes the LED chip of embodiment 1, and is different in structure from the array substrate.

As shown in fig. 6, the array substrate 20 includes a glass substrate 201, a first metal layer 206, a gate insulating layer 205, an active layer 204, a second metal layer 208, and a passivation layer 209.

The first metal layer 206 is disposed on the glass substrate 201.

The first metal layer 206 is disposed on the glass substrate 201 and patterned to form a first gate 206a and a second gate 206 b.

The gate insulating layer 205 is disposed on the glass substrate 201 and covers the first gate 206 a.

The active layer 204 is disposed on the gate insulating layer 205 and opposite to the first gate 206 a.

And an eighth via hole 49 penetrating from the gate insulating layer 205 to the surface of the glass substrate 201.

The second metal layer 208 is patterned to form a source trace 208a, a drain trace 208b, a VDD trace 208c, and a VSS trace 208 d; the source trace 208a and the drain trace 208b are respectively disposed on two sides of the active layer 204 and extend to the surface of the gate insulating layer 205; the VDD routing line 208c is disposed at the bottom of the eighth via 49 and connected to the second gate 206b, wherein a groove 45 is defined by an upper surface of the VDD routing line 208c and a sidewall of the eighth via 49; the VSS wiring 208d is disposed on the gate insulating layer 205.

The passivation layer 209 is disposed on the insulating layer 300 and covers the source trace 208a and a portion of the drain trace 208 b; the first pixel electrode 22 extends from the sidewall of the passivation layer 209 to the VDD routing line 208c, and the upper surface of the VDD routing line 208c and the sidewall of the eighth through hole 49 enclose the pressing groove 45; the second pixel electrode 23 is disposed on the VSS wiring 208d and extends to a portion of the passivation layer 209.

When the LED chip 10 and the array substrate 20 are bonded and pressed to each other, the height difference between the second electrode portion and the first electrode portion is the same as the height difference between the first pixel electrode 22 and the second pixel electrode 23, so that the force applied to the first pixel electrode 22 by the P electrode 103 is the same as the force applied to the second pixel electrode 23 by the N electrode 104, which is beneficial to improving the bonding yield of the LED chip 10 and the array substrate 20. In addition, in the pressing process, ACF ions in the anisotropic conductive film 24 burst, so that the P electrode 103 of the LED chip 10 and the first pixel electrode 22 are conducted with each other, and the N electrode 104 and the second pixel electrode 23 are conducted with each other, so that the LED chip 10 and the array substrate 20 are conducted with each other, and poor contact between the upper and lower electrodes is prevented, and a large number of dark spots are prevented from being formed on the display panel 100 a.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel provided by the embodiment of the present application is described in detail above, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.