阅读说明：本技术 用于生成读取/编程/擦除电压的补偿电路 (Compensation circuit for generating read/program/erase voltages ) 是由 S.萨尔卡 V.V.卡卢鲁 闵泳善 林智薰 于 2019-06-05 设计创作，主要内容包括：补偿电路可以包括参考电流生成电路,该参考电流生成电路包括被配置为传送第一电流的第一宽度的第一晶体管。参考生成电路可以基于第一电流输出参考电流。补偿电路可以包括补偿电流生成电路,该补偿电流生成电路包括被配置为传送第二电流的第二宽度的第二晶体管。第二晶体管可以基于代码从第一组晶体管当中选择。第一组晶体管可以具有与第一宽度成比例的宽度。补偿电流生成电路可以基于第二电流输出具有与参考电流的幅度成比例地选择的幅度的补偿电流。补偿电路可以包括电流镜电路,该电流镜电路被配置为输出其幅度基于第二电流的幅度和第二宽度的补偿电压。(The compensation circuit may include a reference current generation circuit including a first transistor of a first width configured to pass a first current. The reference generation circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generation circuit including a second transistor of a second width configured to pass a second current. The second transistor may be selected from among the first group of transistors based on a code. The first set of transistors may have a width proportional to the first width. The compensation current generation circuit may output a compensation current having a magnitude selected in proportion to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on the magnitude of the second current and the second width.)

1. a compensation circuit, comprising:

A reference current generating circuit comprising: a first transistor of a first width configured to pass a first current, the reference current generation circuit configured to output a reference current based on the first current;

A compensation current generation circuit comprising: a second transistor of a second width configured to pass a second current, the second transistor selected based on a code from among a first group of transistors, the first group of transistors having a width proportional to the first width, the compensation current generation circuit configured to output a compensation current having a magnitude selected proportional to a magnitude of the reference current based on the second current;

a current mirror circuit configured to output a compensation voltage whose magnitude is based on the magnitude of the second current; and

An output transistor configured to output a sensing voltage based on the compensation voltage,

Wherein, with respect to the first value, the second value, and the third value of the code, when a difference between the first value and the second value is equal to a difference between the second value and the third value, a difference between a first magnitude of the sensing voltage output based on the first value and a second magnitude of the sensing voltage output based on the second value corresponds to a difference between a third magnitude of the sensing voltage output based on the third value and the second magnitude.

2. The compensation circuit of claim 1, wherein the reference current generation circuit further comprises:

A first current source configured to output the reference current; and

A third transistor having the first width and configured to pass a third current for outputting the reference current to the first current source.

3. The compensation circuit of claim 2, wherein the magnitude of the reference current corresponds to a sum of the magnitude of the first current and the magnitude of the third current.

4. The compensation circuit of claim 2, wherein the compensation current generation circuit further comprises:

A second current source configured to output the compensation current; and

A fourth transistor having the second width and configured to pass a fourth current for outputting the compensation current to the second current source.

5. The compensation circuit of claim 4, further comprising a direction selection circuit configured to:

Receiving a first gate voltage and a second gate voltage, wherein the magnitude of the first gate voltage varies with temperature variation and the magnitude of the second gate voltage is uniform regardless of temperature variation;

Outputting the first gate voltage to a gate terminal of the second transistor and the second gate voltage to a gate terminal of the fourth transistor in response to a first logic value of a selection signal; and is

Outputting the first gate voltage to a gate terminal of the fourth transistor and the second gate voltage to a gate terminal of the second transistor in response to a second logic value of the selection signal.

6. The compensation circuit of claim 4 wherein the compensation circuit,

Wherein the second current source comprises a fifth transistor configured to pass a fifth current in response to a reference value of the code for outputting the compensation current, and

Wherein the magnitude of the compensation current is increased by the magnitude of the fifth current based on the value of the code being increased by a reference value.

7. The compensation circuit of claim 4, wherein a magnitude of the compensation current corresponds to a sum of a magnitude of the second current and a magnitude of the fourth current.

8. The compensation circuit of claim 4 wherein the compensation circuit,

Wherein the second transistor includes a gate terminal that receives a first temperature-dependent voltage, and

Wherein the magnitude of the first temperature-dependent voltage varies with temperature.

9. the compensation circuit of claim 8 wherein the fourth transistor includes a gate terminal that receives a second temperature-dependent voltage, and

Wherein the magnitude of the sense voltage is further determined based on a difference between the first temperature dependent voltage and the second temperature dependent voltage.

10. the compensation circuit of claim 4, wherein the fourth transistor is selected from among a second set of transistors based on the code, wherein transistors of the second set of transistors are configured to have a width proportional to the first width.

11. The compensation circuit of claim 4, wherein the current mirror circuit comprises:

A sixth transistor including a first terminal configured to output the compensation voltage, and the sixth transistor is configured to transfer the second current to the second transistor and to transfer the third current to the third transistor; and

a seventh transistor comprising a gate terminal electrically connected to a gate terminal of the sixth transistor, the seventh transistor configured to transfer the first current to the first transistor and to transfer the fourth current to the fourth transistor.

12. The compensation circuit of claim 1, wherein the reference current generation circuit is configured to output the reference current at a fixed magnitude.

13. A compensation circuit, comprising:

A reference current generation circuit configured to output a reference current of a fixed magnitude;

A compensation current generation circuit configured to output a compensation current having a magnitude selected in proportion to a magnitude of the reference current based on a code;

a current mirror circuit configured to output a first current to the reference current generation circuit based on the reference current, output a second current based on the compensation current, and output a compensation voltage based on the first current and the second current; and

An output transistor configured to output a sensing voltage based on the compensation voltage,

Wherein the magnitude of the sense voltage is associated with the magnitude of the second current such that when the code is a reference value, the magnitude of the sense voltage is a reference magnitude and when the value of the code increases by the reference value, the magnitude of the second current increases by the reference magnitude.

14. The compensation circuit of claim 13 wherein the compensation circuit,

Wherein the reference current generation circuit comprises a first transistor having a first width, the first transistor configured to pass a first current for outputting the reference current,

Wherein the compensation current generation circuit includes a second transistor having a second width proportional to the first width of the first transistor, the second transistor configured to pass a second current for outputting the compensation current.

15. The compensation circuit of claim 14 wherein the compensation circuit,

Wherein the second transistor is selected based on the code from among a group of transistors, a transistor of the group of transistors having a width proportional to the first width.

16. The compensation circuit of claim 14 wherein the compensation circuit,

Wherein the compensation current generation circuit further includes a third transistor configured to transfer a third current based on the second current transferred from the second transistor, and

Wherein the magnitude of the compensation current is increased by the magnitude of the third current each time the value of the code is increased by the reference value.

17. A voltage generation circuit comprising:

A compensation circuit configured to output a compensation voltage having a magnitude based on a code based on a first temperature-dependent voltage and a second temperature-dependent voltage, the magnitude of the first temperature-dependent voltage varying with a change in temperature, and the magnitude of the second temperature-dependent voltage being uniform regardless of the change in temperature; and

An output transistor configured to output a sensing voltage whose magnitude is based on the compensation voltage,

Wherein the voltage generation circuit is configured to generate a sense voltage having a magnitude proportional to the value of the code, and the magnitude of the sense voltage is associated with a difference between the magnitude of the first temperature-dependent voltage and the magnitude of the second temperature-dependent voltage.

18. The voltage generation circuit of claim 17 wherein the compensation circuit is configured to receive a feedback voltage having a magnitude based on a magnitude of the sense voltage and to output the compensation voltage further based on the feedback voltage.

19. The voltage generation circuit of claim 17,

Wherein the compensation circuit comprises a plurality of transistors,

Wherein the compensation circuit is configured to select one or more transistors from among the plurality of transistors based on the code such that the selected one or more transistors pass current in response to the first temperature-dependent voltage, and

wherein the compensation voltage is output based on the current.

20. The voltage generation circuit of claim 17,

Wherein the magnitude of the first temperature-dependent voltage is negatively proportional to temperature, and

Wherein the magnitude of the sensing voltage is proportional to a value obtained by subtracting the magnitude of the first temperature-dependent voltage from the magnitude of the second temperature-dependent voltage.

Technical Field

Embodiments of the inventive concepts disclosed herein relate to electronic circuits, and more particularly, to electronic circuits included in memory devices.

Background

With the development and progress of information devices such as computers, mobile phones, and smart phones, a large amount of information may be stored in and processed by the information devices. Therefore, a higher-performance memory device can be used as a component of the information device. Since the semiconductor memory can operate at low power, the semiconductor memory can be used in a memory device.

Examples of the semiconductor memory include volatile memory and nonvolatile memory. Examples of volatile memory may include Static Random Access Memory (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), and the like. Examples of the nonvolatile memory include a flash memory, a phase-change RAM (PRAM), a Magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a Ferroelectric RAM (FRAM), and the like.

The semiconductor memory may include memory cells for storing data. Data stored in a memory cell can be read as a voltage of a particular magnitude is supplied to the memory cell. The characteristics of the memory cell may be affected by conditions such as temperature. Therefore, in order to accurately sense (read/program/erase) data stored in the memory cell, the magnitude of the supplied voltage has a magnitude that can be determined in consideration of conditions affecting the memory cell.

disclosure of Invention

Some embodiments of the inventive concept may provide an electronic circuit configured to generate a voltage for sensing data stored in a memory device.

According to some embodiments, a compensation circuit may be provided. The compensation circuit may include a reference current generation circuit, a compensation current generation circuit, a current mirror circuit, and an output transistor. The reference current generation circuit may include a first transistor of a first width configured to pass a first current, and may be configured to output a reference current based on the first current. The compensation current generation circuit may include a second transistor of a first width selected from among the first group of transistors based on the code. The first set of transistors may have a width proportional to the first width. The compensation current generation circuit may be configured to output a compensation current having a magnitude selected in proportion to a magnitude of the reference current based on the second current. The current mirror circuit may be configured to output a compensation voltage having a magnitude based on a magnitude of the second current. The output transistor may be configured to output the sensing voltage based on the compensation voltage. The code may have a first value, a second value, and a third value. The difference between the first value and the second value may be the same as the difference between the second value and the third value. A difference between a first magnitude of the voltage output based on the first value and a second magnitude of the voltage output based on the first value may correspond to a difference between the second magnitude and a third magnitude of the voltage output based on the third value.

according to some embodiments, a compensation circuit may be provided. The compensation circuit may include a compensation current generation circuit configured as a reference current generation circuit that outputs a reference current of fixed magnitude. The compensation circuit may include a compensation current generation circuit configured to output a compensation current having a magnitude selected in proportion to a magnitude of the reference current based on the code. The compensation circuit may include a current mirror circuit configured to output a first current to the reference current generation circuit based on the reference current, output a second current based on the compensation current, and output a compensation voltage based on the first current and the second current. The compensation circuit may include an output transistor configured to output the sensing voltage based on the compensation voltage. The magnitude of the sensing voltage may be associated with the magnitude of the second current such that when the code is the reference value, the magnitude of the sensing voltage is the reference magnitude, and when the value of the code increases by the reference value, the magnitude of the second current increases by the reference magnitude.

According to some embodiments, a voltage generation circuit may be provided. The voltage generation circuit may include a compensation circuit configured to output a compensation voltage having a code-based magnitude based on the first temperature-dependent voltage and based on the second temperature-dependent voltage. The first temperature-dependent voltage may have an amplitude that varies with temperature, and the second temperature-dependent voltage may have an amplitude that is uniform regardless of temperature. The voltage generation circuit may include an output transistor configured to output the sensing voltage having a magnitude based on a magnitude of the compensation voltage. The voltage generation circuit may be configured to generate the sense voltage having a magnitude proportional to the code value and associated with a difference between a magnitude of the first temperature-dependent voltage and a magnitude of the second temperature-dependent voltage.

Drawings

The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a circuit diagram illustrating a read voltage generation circuit according to some embodiments of the inventive concept.

Fig. 2 is a block diagram illustrating an example configuration of the compensation circuit of fig. 1 according to some embodiments of the inventive concept.

Fig. 3 is a circuit diagram illustrating an example configuration of the compensation circuit of fig. 1 according to some embodiments of the inventive concept.

Fig. 4 is a circuit diagram illustrating a read voltage generation circuit according to some embodiments of the inventive concept.

Fig. 5 is a block diagram illustrating an example configuration of the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

Fig. 6 is a circuit diagram illustrating an example configuration of the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

Fig. 7 is a circuit diagram illustrating an example configuration of the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

Fig. 8 is a circuit diagram illustrating an example configuration of the compensation current generation circuit of fig. 7 according to some embodiments of the inventive concept.

Fig. 9 is a circuit diagram for describing an example operation of the compensation current generation circuit of fig. 8 according to some embodiments of the inventive concept.

fig. 10 is a circuit diagram for describing an example operation of the compensation current generation circuit of fig. 8 according to some embodiments of the inventive concept.

Fig. 11 is a circuit diagram for describing an example operation of the compensation current generation circuit of fig. 8 according to some embodiments of the inventive concept.

Fig. 12 is a graph illustrating voltages received by the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

Fig. 13 is a graph illustrating the read voltage of fig. 4 according to a selection signal, according to some embodiments of the inventive concept.

Fig. 14 is a graph illustrating voltages output from the read voltage generation circuit of fig. 1 and/or 4 according to some embodiments of the inventive concept.

fig. 15 is a graph illustrating voltages output from the read voltage generation circuit of fig. 1 and/or 4 according to some embodiments of the inventive concept.

fig. 16 is a block diagram illustrating an example memory system including the read voltage generation circuit of fig. 1 and/or 4, according to some embodiments of the inventive concepts.

Detailed Description

Some embodiments of the inventive concept may be described in detail and clearly to the extent that the inventive concept can be easily implemented by those skilled in the art.

As used herein, the term "width" may refer to the width of a transistor channel. That is, the width may refer to the length of a direction (e.g., a vertical direction) that intersects the direction in which charge is transferred in the transistor channel. The transistor may be configured to have a width of a certain size.

As used herein, the term "code" may refer to data represented in the form of binary numbers. The n-bit code may be represented by "n" consecutive logical values (logical value "1" or logical value "0"). For example, the values of the 2-bit code may include "00", "01", "10", and "11".

As used herein, the expression "voltage level is proportional to code value" or "voltage level varies linearly with code value" may be used. The voltage level is proportional to the code value or linearly changes with the code value may mean that a difference between a voltage amplitude corresponding to a value of "qth" code of "n" codes and a voltage amplitude corresponding to a value of "qth + 1" code is substantially equal to a difference (q is a natural number) between a voltage amplitude corresponding to a value of "qth + 1" code and a voltage amplitude corresponding to a value of "qth + 2" code.

For example, in an embodiment in which the difference between the magnitude of the voltage corresponding to code value "000" and the magnitude of the voltage corresponding to code value "001" is substantially equal to the difference between the magnitude of the voltage corresponding to code value "001" and the magnitude of the voltage corresponding to code value "010", the magnitude of the voltage may be proportional to code values in the range of code values "000" to "010". Alternatively, the voltage amplitude may vary linearly with code values in the range of code values "000" to "010". However, the two values being substantially equal to each other may include embodiments where the two values are not exactly equal to each other but there is only a slight difference between the two values, as well as embodiments where the two values are exactly equal to each other.

Fig. 1 is a circuit diagram illustrating a read voltage generation circuit according to some embodiments of the inventive concept. A read voltage generation circuit 1000 configured to generate a read voltage Vread1 for reading data will be described with reference to fig. 1, however, it is understood that the read voltage generation circuit 1000 may generate not only the read voltage Vread1, but also other voltages for various purposes in some embodiments. For example, the read voltage generation circuit 1000 may generate a voltage for sensing (reading, programming, erasing, etc.) data.

Referring to fig. 1, the read voltage generation circuit 1000 may include a compensation circuit 1100, a transistor TR0, a resistor R1, and a resistor R2.

The compensation circuit 1100 may receive codes TC1 and TC2, voltages Vztc, Vntc, Vpwr and Vss, a reference voltage Vref, and a feedback voltage Vfb. For example, as will be described with reference to fig. 16, the compensation circuit 1100 may be a component of a memory device included in a memory system. The memory system may include logic circuitry to generate codes TC1 and TC 2. For example, logic circuitry may be included in a component such as a memory controller. The compensation circuit 1100 may receive the codes TC1 and TC2 from the logic circuit.

For example, a memory system may include a voltage generator. The voltage generator may generate voltages Vztc, Vntc, and Vpwr and a reference voltage Vref, which may be used to operate the read voltage generation circuit 1000. The compensation circuit 1100 may receive the voltages Vztc, Vntc, and Vpwr and the reference voltage Vref from the voltage generator. The compensation circuit 1100 may be electrically connected to a node between the resistor R1 and the resistor R2. The compensation circuit 1100 may receive the feedback voltage Vfb from a node between the resistor R1 and the resistor R2. The voltage Vss may be a voltage of an equipotential terminal. For example, the voltage Vss may be a ground voltage.

The compensation circuit 1100 may output the voltage Vout1 based on the codes TC1 and TC2 and the voltages Vztc, Vntc, Vref, Vpwr, and Vss. The compensation circuit 1100 may output the voltage Vout1 to the gate terminal of the transistor TR 0. The configuration and operation of the compensation circuit 1100 will be described with reference to fig. 2 and 3.

The transistor TR0 may include a gate terminal that receives the voltage Vout1 from the compensation circuit 1100. The transistor TR0 may include a first terminal that receives the voltage Vpwr. A second terminal of the transistor TR0 may be electrically connected to a first terminal of the resistor R1. The read voltage Vread1 may be output from a node between the transistor TR0 and the first end of the resistor R1. A second end of the resistor R1 may be electrically connected to a first end of the resistor R2. A second end of the resistor R2 may be electrically connected to an equipotential terminal that provides the voltage Vss.

When the voltage Vout1 is applied to the gate terminal of the transistor TR0, a current may flow through the transistor TR 0. When a current flows through the transistor TR0, a read voltage Vread1 may be formed at a node between the transistor TR0 and the resistor R1. The magnitude of voltage Vread1 may be associated with the magnitude of voltage Vout 1. The read voltage generation circuit 1000 may output the read voltage Vread1 to another component of a memory system (e.g., a memory cell in a memory device). The memory device may output a data signal indicating data stored in the memory cell based on the read voltage Vread1 (refer to fig. 16).

The voltage Vread1 may be divided by a resistor R1 and a resistor R2. In an embodiment where the magnitude of the voltage Vss is "Vss", the magnitude of the voltage Vread1 is "Vread 1", the magnitude of the resistor R1 is "R1", and the magnitude of the resistor R2 is "R2", the magnitude of the feedback voltage Vfb may be represented by the equation "(Vread 1-Vss) × R2/(R1+ R2)". In embodiments where the magnitude of the feedback voltage Vfb is "Vfb" and the magnitude of the voltage Vss is "0", the magnitude of the voltage Vread1 may be represented by the equation "(1 + (R1/R2)) × Vfb". Thus, the magnitude of the feedback voltage Vfb may be associated with the magnitude of the voltage Vread1, and the magnitude of the feedback voltage Vfb may be associated with the magnitude of the voltage Vout 1.

Each of the codes TC1 and TC2 may be expressed as being made up of "n" bits (n is a natural number). In some embodiments, codes TC1 and TC2 may have values that are complementary to each other. For example, when the value of the code TC1 is "000000", the value of the code TC2 may be "111111". The code TC1 may include least significant bits TC1<0> through most significant bits TC1< n-1 >. The code TC2 may include least significant bits TC2<0> through most significant bits TC2< n-1 >. For example, in an embodiment where the code TC1 and the code TC2 are each 6-bit codes, the code TC1 and the code TC2 may have one of values from "000000" to "111111" and a complementary value of the value from "000000" to "11111", respectively.

the logic circuitry may generate the codes TC1 and TC2 based on various conditions associated with memory devices of the memory system. The memory device may provide a read voltage of a particular magnitude for the purpose of reading data stored in the memory cell. The magnitude of the threshold voltage of a memory cell may vary with various conditions (e.g., temperature, stress, etc.). Therefore, the magnitude of the read voltage useful for accurately reading data may also vary with various conditions. As used herein, temperature may refer to the temperature of a memory system that includes the read voltage generation circuit 1000.

For example, the magnitude of the threshold voltage of a memory cell may increase as the temperature decreases. The read voltage of increased magnitude can be used to accurately read data stored in a memory cell having a threshold voltage of increased magnitude. The logic circuit may track the threshold voltage of the memory cell. The logic circuit may determine a magnitude of a read voltage that may be used to accurately read data stored in the memory cell based on the tracked threshold voltage. The logic circuit may determine the magnitude of the voltage Vout1 based on the relationship between the read voltage Vread1 and the voltage Vout 1. The logic circuit may determine the codes TC1 and TC2 such that the read voltage Vread1 having the determined magnitude is output from the read voltage generation circuit 1000.

One or more of the magnitudes of the voltages Vztc and/or Vntc may be correlated to temperature. For example, the amplitude of the voltage Vztc may be uniform regardless of temperature variations. The magnitude of the voltage Vntc may decrease with increasing temperature. In the specification, for convenience of description, an ideal embodiment may be described with respect to a voltage Vztc whose magnitude is uniform regardless of temperature variation and a voltage Vntc whose magnitude is proportional to temperature. However, in some embodiments, the actual amplitudes of voltages Vztc and Vntc may differ slightly from the amplitudes of voltages Vztc and Vntc of an ideal embodiment. The relationship between the voltages Vztc and Vntc and temperature will be described with reference to fig. 12.

Fig. 2 is a block diagram illustrating an example configuration of the compensation circuit of fig. 1 according to some embodiments of the inventive concept.

Referring to fig. 2, the compensation circuit 1100 may include a current mirror circuit 1110, a reference current generation circuit 1120, and a compensation current generation circuit 1130. The current mirror circuit 1110 may receive the voltage Vpwr. The current mirror circuit 1110 may output the voltage Vout1 to the gate terminal of the transistor TR0 of fig. 1. The current mirror circuit 1110 may be electrically connected to the reference voltage generation circuit 1120. The current mirror circuit 1110 may be electrically connected to the compensation current generation circuit 1130.

The reference current generation circuit 1120 may receive a reference voltage Vref, a feedback voltage Vfb, and a code TC 1. The compensation current generation circuit 1130 may receive the voltage Vztc, the voltage Vntc, and the code TC 2. The reference current generation circuit 1120 and the compensation current generation circuit 1130 may be electrically connected to an equipotential terminal supplying the voltage Vss.

The reference current generation circuit 1120 may generate a reference current Iref1 based on the received reference voltage Vref, the received feedback voltage Vfb, and the received code TC 1. The reference current generation circuit 1120 may output the reference current Iref1 to the equipotential terminal. The compensation current generation circuit 1130 may generate the compensation current ITC1 based on the received voltage Vztc, the received voltage Vntc, and the received code TC 2. The compensation current generation circuit 1130 may output the compensation current ITC1 to the equipotential terminal.

When the reference current Iref1 is generated by the reference current generation circuit 1120, the reference current generation circuit 1120 may receive the current I1 from the current mirror circuit 1110. When the compensation current ITC1 is generated by the compensation current generation circuit 1130, the compensation current generation circuit 1130 may receive the current I2 from the current mirror circuit 1110. When the current I1 and the current I2 are output from the current mirror circuit 1110, the voltage Vout1 may be formed in the current mirror circuit 1110. The current mirror circuit 1110 may output the voltage Vout1 to the transistor TR0 of fig. 1.

The current mirror circuit 1110 may be a first stage amplifier configured to output a voltage Vout 1. The transistor TR0 may be a second stage amplifier configured to output a read voltage Vread 1.

The magnitude of the voltage Vout1 may be correlated to temperature. Also, the magnitude of the voltage Vout1 may be associated with the code TC1 and the code TC 2. Thus, the magnitude of the read voltage Vread1 may be associated with temperature and the codes TC1 and TC 2. Hereinafter, operations of the current mirror circuit 1110, the reference current generation circuit 1120, and the compensation current generation circuit 1130 will be described with reference to fig. 3.

Fig. 3 is a circuit diagram illustrating an example configuration of the compensation circuit of fig. 1 according to some embodiments of the inventive concept.

Referring to fig. 3, the current mirror circuit 1110 may include a transistor TR1 and a transistor TR 2. The reference current generating circuit 1120 may include a transistor TR3, a transistor TR4, and a current source CS 1. The compensation current generation circuit 1130 may include a transistor TR5, a transistor TR6, and a current source CS 2.

The transistor TR1 may include a first terminal that receives the voltage Vpwr. A second terminal of the transistor TR1 may be electrically connected to the node N1. The transistor TR2 may include a first terminal that receives the voltage Vpwr. A gate terminal of the transistor TR1 may be electrically connected to a gate terminal of the transistor TR2, a second terminal of the transistor TR2, and the node N2.

The transistor TR3 may include a gate terminal that receives a reference voltage Vref. A first terminal of the transistor TR3 may be electrically connected to the node N1. A second terminal of transistor TR3 may be electrically connected to current source CS 1. The transistor TR4 may include a gate terminal that receives the feedback voltage Vfb. A first terminal of the transistor TR4 may be electrically connected to the node N2. A second terminal of transistor TR4 may be electrically connected to current source CS 1. Current source CS1 may be electrically connected to an equipotential terminal that provides voltage Vss.

the transistor TR5 may include a gate terminal that receives the voltage Vntc. A first terminal of the transistor TR5 may be electrically connected to the node N1. A second terminal of transistor TR5 may be electrically connected to current source CS 2. The transistor TR6 may include a gate terminal that receives the voltage Vztc. A first terminal of the transistor TR6 may be electrically connected to the node N2. A second terminal of transistor TR6 may be electrically connected to current source CS 2. Current source CS2 may be electrically connected to an equipotential terminal that provides voltage Vss.

current source CS1 may output a reference current Iref1 with a variable amount. Current source CS1 may control the magnitude of reference current Iref1 based on code TC 1. For example, current source CS1 may control the magnitude of reference current Iref1 to be negatively proportional to the value of code TC 1. The sum of the magnitude of the current I11 flowing through the transistor TR3 and the magnitude of the current I12 flowing through the transistor TR4 may correspond to the magnitude of the reference current Iref 1.

The current source CS2 may output a compensation current ITC1 having a variable amount. For example, the current source CS2 may control the magnitude of the compensation current ITC1 based on the code TC 2. For example, the current source CS2 may control the magnitude of the compensation current ITC1 to be proportional to the value of the code TC 2. The sum of the magnitude of the current I21 flowing through the transistor TR5 and the magnitude of the current I22 flowing through the transistor TR6 may correspond to the magnitude of the compensation current ITC 1.

the magnitude of the current I11 flowing through the transistor TR3 and the magnitude of the current I12 flowing through the transistor TR4 may vary as the magnitude of the reference current Iref1 varies. The magnitude of the current I21 flowing through the transistor TR5 and the magnitude of the current I22 flowing through the transistor TR6 may vary as the magnitude of the compensation current ITC1 varies. When the magnitude of the current I11 flowing through the transistor TR3 and the magnitude of the current I21 flowing through the transistor TR5 vary, the magnitude of the current ID1 flowing through the transistor TR1 may vary. When the magnitude of the current I12 flowing through the transistor TR4 and the magnitude of the current I22 flowing through the transistor TR6 vary, the magnitude of the current ID2 flowing through the transistor TR2 may vary.

Referring to fig. 2 and 3 together, the magnitude of the current I1 of fig. 2 may correspond to the sum of the magnitude of the current I11 and the magnitude of the current I12. The magnitude of the current I2 of fig. 2 may correspond to the sum of the magnitude of the current I21 and the magnitude of the current I22. When the current I1 and the current I2 flow, a voltage Vout1 may be formed at the node N1. As described with reference to fig. 1, the feedback voltage Vfb may be formed at a node between the resistor R1 and the resistor R2, and the read voltage Vread1 may be output from the read voltage generation circuit 1000. The magnitude of the feedback voltage Vfb may be represented by equation 1.

[ equation 1]

Vfb＝Vref+α*(Vntc-Vztc)

In equation 1, "Vfb" may represent the magnitude of the feedback voltage Vfb, "Vref" may represent the magnitude of the reference voltage Vref, "Vntc" may represent the magnitude of the voltage Vntc, and "Vztc" may represent the magnitude of the voltage Vztc. "α" in equation 1 can be represented by equation 2.

[ equation 2]

In equation 2, "W _ 4" may represent the width of the transistor TR4, "I12" may represent the magnitude of the current I12, "W _ 5" may represent the width of the transistor TR5, "I21" may represent the magnitude of the current I21, and "k" may be a proportionality constant regardless of the temperature, the value of the code TC1, and the value of the code TC 2.

The current source CS1 may be configured to output a reference current Iref1 having a magnitude that is negatively proportional to the value of the code TC 1. The current source CS2 may be configured to output a compensation current ITC1 having a magnitude that is directly proportional to the value of the code TC 2. The magnitude of current I12 and the magnitude of current I21 may vary with the magnitude of reference current Iref1 and compensation current ITC 1. As such, "α" may vary according to equation 2, and the magnitude of the feedback voltage Vfb may vary according to equation 1.

As described with reference to fig. 1, the magnitude of the read voltage Vread1 may correspond to the magnitude of the feedback voltage Vfb. Accordingly, the magnitude of the read voltage Vread1 may vary based on equation 1. Hereinafter, the read voltage Vread1 may be described with reference to equation 1 and equation 2.

The read voltage generation circuit 1000 may be configured to output the read voltage Vread1 having a magnitude varying with a value of the code TC1 and a value of the code TC 2. For example, the read voltage generation circuit 1000 may be configured to output the read voltage Vread1 having an amplitude that becomes larger as the value of the code TC1 and the value of the code TC2 change.

as described with reference to fig. 1, the magnitude of voltage Vntc and/or the magnitude of voltage Vztc may be correlated with temperature. For example, the magnitude of voltage Vntc may be negatively proportional to temperature, and the magnitude of voltage Vztc may be uniform regardless of temperature variations. Accordingly, the read voltage generation circuit 1000 may be configured to output a read voltage Vread1 having a magnitude associated with temperature. For example, the read voltage generation circuit 1000 may be configured to output the read voltage Vread1 having a magnitude that becomes smaller as the temperature increases.

As the magnitude of the read voltage Vread1 varies with temperature and the codes TC1 and TC2, the magnitude of the read voltage Vread1 may vary with the threshold voltage of the memory cell, which varies with various conditions.

fig. 4 is a circuit diagram illustrating a read voltage generation circuit according to some embodiments of the inventive concept. In contrast to fig. 1, the read voltage generation circuit 2000 of fig. 4 may include a compensation circuit 2100 instead of the compensation circuit 1100. Some elements of the read voltage generation circuit 2000 of fig. 4 may be the same as or similar to corresponding elements of the read voltage generation circuit 1000 described with respect to fig. 1-3, and redundant description may be omitted for the sake of brevity.

The compensation circuit 2100 may receive a code TC from the logic circuit. The code TC may be represented as being composed of "n" bits (n is a natural number). The code TC may include least significant bits TC <0> through most significant bits TC < n-1 >. For example, in an embodiment where the code TC is a 6-bit code, the code TC may have one of the values from "000000" to "111111".

For example, the logic circuit may generate the code TC based on various conditions associated with the memory system. The configuration and operation of the read voltage generation circuit 2000 may be similar to those of the read voltage generation circuit 1000. Therefore, additional description may be omitted to avoid redundancy.

Fig. 5 is a block diagram illustrating an example configuration of the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

Referring to fig. 5, the compensation circuit 2100 may include a current mirror circuit 2110, a reference current generation circuit 2120, and a compensation current generation circuit 2130. The current mirror circuit 2110 may receive the voltage Vpwr. The current mirror circuit 2110 may output a voltage Vout2 to a gate terminal of the transistor TR0 of fig. 4. The current mirror circuit 2110 may be electrically connected to the reference current generating circuit 2120 and the compensation current generating circuit 2130.

The reference current generating circuit 2120 may receive a reference voltage Vref and a feedback voltage Vfb. The compensation current generation circuit 2130 may receive the voltage Vztc, the voltage Vntc, and the code TC. The reference current generating circuit 2120 and the compensation current generating circuit 2130 may be electrically connected to an equipotential terminal supplying the voltage Vss.

the reference current generation circuit 2120 may generate the reference current Iref2 based on the received reference voltage Vref and the received feedback voltage Vfb. The reference current generation circuit 2120 may output the reference current Iref2 to an equipotential terminal. The compensation current generation circuit 2130 may generate the compensation current ITC2 based on the received voltage Vztc, the received voltage Vntc, and the received code TC. The compensation current generation circuit 2130 may output the compensation current ITC2 to the equipotential terminal.

When the reference current Iref2 is generated by the reference current generation circuit 2120, the reference current generation circuit 2120 may receive the current I3 from the current mirror circuit 2110. When the compensation current ITC2 is generated by the compensation current generation circuit 2130, the compensation current generation circuit 2130 may receive the current I4 from the current mirror circuit 2110. When the current I3 and the current I4 are output from the current mirror circuit 2110, the current mirror circuit 2110 may output the voltage Vout2 to the transistor TR0 of fig. 4.

Some operations of the current mirror circuit 2110, the reference current generating circuit 2120, and the compensation current generating circuit 2130 will be described with reference to fig. 6.

Fig. 6 is a circuit diagram illustrating an example configuration of the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

The compensation circuit 2100 of fig. 4 may include the compensation circuit 2100a of fig. 6. The compensation current generation circuit 2130 of fig. 5 may include the compensation current generation circuit 2131 of fig. 6. Referring to fig. 6, the current mirror circuit 2110 may include a transistor TR1 and a transistor TR 2. The reference current generating circuit 2120 may include a transistor TR7, a transistor TR8, and a current source CS 3. The compensation current generation circuit 2131 may include a transistor TR9, a transistor TR10, and a current source CS 4.

the transistor TR1 may include a first terminal that receives the voltage Vpwr. A second terminal of the transistor TR1 may be electrically connected to the node N3. The transistor TR2 may include a first terminal that receives the voltage Vpwr. A gate terminal of the transistor TR1 may be electrically connected to a gate terminal of the transistor TR2, a second terminal of the transistor TR2, and the node N4. Transistor TR1 may carry current ID 3. Transistor TR2 may carry current ID 4.

The transistor TR7 may include a gate terminal that receives a reference voltage Vref. A first terminal of the transistor TR7 may be electrically connected to the node N3. A second terminal of transistor TR7 may be electrically connected to a first terminal of current source CS 3. Transistor TR7 may carry current I31. The transistor TR8 may include a gate terminal that receives the feedback voltage Vfb. A first terminal of the transistor TR8 may be electrically connected to the node N4. A second terminal of transistor TR8 may be electrically connected to a first terminal of current source CS 3. Transistor TR8 may carry current I32. A second terminal of current source CS3 may be electrically connected to an equipotential terminal providing voltage Vss.

the transistor TR9 may include a gate terminal that receives the voltage Vntc. A first terminal of the transistor TR9 may be electrically connected to the node N3. A second terminal of transistor TR9 may be electrically connected to a first terminal of current source CS 4. Transistor TR9 may carry current I41. The transistor TR10 may include a gate terminal that receives the voltage Vztc. A first terminal of the transistor TR10 may be electrically connected to the node N4. A second terminal of transistor TR10 may be electrically connected to a first terminal of current source CS 4. Transistor TR10 may carry current I42. A second terminal of current source CS4 may be electrically connected to an equipotential terminal providing voltage Vss.

In fig. 6, each of the transistor TR9 and the transistor TR10 is shown to be implemented with one transistor. However, as shown in fig. 8, for example, each of the transistor TR9 and the transistor TR10 may be one or more transistors selected from among a plurality of transistors based on the code TC. The transistors that can be selected as the transistor TR9 and the transistor TR10 can have different widths. Therefore, the width of the transistor TR9 and the width of the transistor TR10 can be selected according to the code TC.

current source CS3 may output a reference current Iref 2. The sum of the magnitude of the current I31 flowing through the transistor TR7 and the magnitude of the current I32 flowing through the transistor TR8 may correspond to the magnitude of the reference current Iref 2. In an embodiment in which the characteristics of transistor TR7 and transistor TR8 are substantially identical to each other, the magnitude of current I31 may be substantially equal to the magnitude of current I32.

For better understanding, in the description, an embodiment in which the magnitude of the current I31 is substantially equal to the magnitude of the current I32 may be described. However, it is understood that the concept of the invention may include some embodiments in which the currents I31 and I32 have different magnitudes depending on the magnitude of the reference voltage Vref, the magnitude of the feedback voltage Vfb, and the characteristics of the transistors TR7 and TR 8.

The current source CS4 may output a compensation current ITC2 having a magnitude selected by the code TC 2. The sum of the magnitude of the current I41 flowing through the transistor TR9 and the magnitude of the current I42 flowing through the transistor TR10 may correspond to the magnitude of the compensation current ITC 2. In an embodiment in which the characteristics of transistor TR9 and transistor TR10 are substantially identical to each other, the magnitude of current I41 may be substantially equal to the magnitude of current I42. The magnitude of the compensation current ITC2 may be selected based on the code TC. Therefore, the magnitude of the compensation current I41 may be selected based on the code TC.

For better understanding, in the description, an embodiment in which the magnitude of the current I41 is substantially equal to the magnitude of the current I42 may be described. However, it is understood that the concept of the invention may include some embodiments in which the currents I41 and I42 have different amplitudes according to the amplitude of the voltage Vntc, the amplitude of the voltage Vztc, and the characteristics of the transistors (TR9 and TR10) selected by the code TC.

the reference current generation circuit 1120 of fig. 3 may output the reference current Iref1 having an amplitude varying with the code TC1 and temperature, but the reference current generation circuit 2120 of fig. 6 may output the reference current Iref2 of a fixed value. The compensation circuit 2100a can adjust the amplitude of the voltage Vout2, which varies due to the code TC and the temperature, mainly according to the operation of the compensation current generation circuit 2131.

Referring to fig. 5 and 6 together, the magnitude of the current I3 of fig. 5 may correspond to the sum of the magnitude of the current I31 and the magnitude of the current I32. The magnitude of the current I4 of fig. 5 may correspond to the sum of the magnitude of the current I41 and the magnitude of the current I42. When the current I3 and the current I4 flow, a voltage Vout2 may be formed at the node N3. As described with reference to fig. 4, the feedback voltage Vfb may be formed at a node between the resistor R1 and the resistor R2, and the read voltage Vread2 may be output from the read voltage generation circuit 2000. The magnitude of the feedback voltage Vfb may be represented by equation 3.

[ equation 3]

Vfb＝Vref+α*(Vntc-Vztc)

In equation 3, "Vfb" may represent the magnitude of the feedback voltage Vfb, "Vref" may represent the magnitude of the reference voltage Vref, "Vntc" may represent the magnitude of the voltage Vntc, and "Vztc" may represent the magnitude of the voltage Vztc. As described with reference to fig. 1, the magnitude of voltage Vntc and/or the magnitude of voltage Vztc may be correlated with temperature. For example, the magnitude of the voltage Vntc may be configured to have a value proportional to the temperature, and the magnitude of the voltage Vztc may be configured to have a value uniform regardless of temperature variation. The magnitude "Vfb" of the feedback voltage Vfb may be determined based on the difference between the magnitude of the voltage Vntc and the magnitude of the voltage Vztc. "α" in equation 3 can be represented by equation 4.

[ equation 4]

In equation 4, "W _ 8" may represent the width of the transistor TR8, "I32" may represent the amplitude of the current I32, "W _ 9" may represent the width of the transistor TR9, "I41" may represent the amplitude of the current I41, and "k" may be a proportionality constant regardless of the temperature and the value of the code TC.

Referring to equations 3 and 4, the magnitude of the feedback voltage Vfb may include a non-linear term with respect to both the code TC and the temperature caused by "α". That is, due to the items included in "αthe magnitude of the feedback voltage Vfb may include a value that varies non-linearly with the temperature and the value of the code TC.

In detail, since the currents I41 and I32 are drain currents of the transistors TR9 and TR8, respectively, the magnitude of the current I41 and the magnitude of the current I32 may vary with temperature. The rate of change of the feedback voltage Vfb with respect to temperature according to the relationship described with reference to equations 3 and 4Can be calculated as "Vntc-Vztc" may be linear with temperature, but "Vntc-Vztc" may be non-linear with temperature.

Due to the fact thatCorresponds to the square root of the value varying with temperature, soMay be a non-linear term of temperature change. Therefore, the magnitude of the feedback voltage Vfb calculated according to equations 3 and 4 may include a non-linear term of temperature change.

Also, "W _ 9" and "I41" may vary depending on the value of the code TC as described with reference to the transistors TR9 and TR 10. Due to the fact thatthe term is the square root of the value that can vary with the value of the code TC,May be a non-linear term for the value of the code TC. Therefore, the magnitude of the feedback voltage Vfb calculated according to equations 3 and 4 may include a non-linear term with respect to the value of the code TC.

As described with reference to fig. 4, the magnitude of the read voltage Vread2 may correspond to the magnitude of the feedback voltage Vfb. Therefore, the magnitude of the read voltage Vread2 may vary based on equation 3. Hereinafter, the read voltage Vread2 may be described with reference to equation 3 and equation 4.

In embodiments where the magnitude of the feedback voltage Vfb is non-linear with the temperature and the value of the code TC, the computational burden of the logic circuit may be increased to calculate the read voltage Vread2 with a magnitude for accurately reading the data of the memory cell. Logic circuitry configured to handle a large number of operations may consume a large amount of power. Also, logic circuits configured to handle a large number of operations may be implemented with chips placed in a large area.

According to the concept of the present invention, in the operation of the compensation circuit 2100a, "W _ 9" and "I41" may vary with the code TC, so that the magnitude of the feedback voltage Vfb calculated according to equations 3 and 4 does not include a non-linear term with respect to the temperature variation and the value of the code TC (e.g.,May have a value independent of the temperature and the value of the code TC). For example, "W _ 9" and "I41" may be set to multiples of "W _ 8" and "I32", respectively, to improve the linearity of the temperature compensation.

Examples of "W _ 9" and "I41" selected differently according to the code TC will be described with reference to fig. 8 to 11.

fig. 7 is a circuit diagram illustrating an example configuration of the compensation circuit of fig. 4 according to some embodiments of the inventive concept.

The compensation circuit 2100 of fig. 4 may include the compensation circuit 2100b of fig. 7. Compared to the compensation circuit 2100a of fig. 6, the compensation circuit 2100b of fig. 7 may further include a direction selection circuit 2132. Some elements of the read compensation circuit 2100b of fig. 7 may be the same as or similar to corresponding elements of the compensation circuit 2100a of fig. 6 described with reference to fig. 6, and redundant description may be omitted for the sake of brevity.

Direction selection circuit 2132 may receive voltage Vztc and voltage Vntc. The direction selection circuit 2132 may receive a selection signal SEL from the logic circuit. The direction selection circuit 2132 may output the voltage Va and the voltage Vb in response to a selection signal SEL. The direction selection circuit 2132 may output the voltage Va to the gate terminal of the transistor TR 9. The direction selection circuit 2132 may output a voltage Vb to the gate terminal of the transistor TR 10.

The direction selection circuit 2132 may output a voltage Va and a voltage Vb each of which selectively has one of values corresponding to the voltage Vztc and the voltage Vntc based on a logical value of the selection signal SEL. For example, in some embodiments, when selection signal SEL indicates a logical value of "1", voltage Va may correspond to voltage Vztc and voltage Vb may correspond to voltage Vntc, and when selection signal SEL indicates a logical value of "0", voltage Va may correspond to voltage Vntc and voltage Vb may correspond to voltage Vztc. However, embodiments of the inventive concept are not limited thereto.

Hereinafter, for convenience of description, an embodiment in which the voltage Vztc is applied to the gate terminal of the transistor TR9 (i.e., the voltage Vztc is selected as the voltage Va) and the voltage Vntc is applied to the gate terminal of the transistor TR10 (i.e., the voltage Vntc is selected as the voltage Vb) in response to the selection signal SEL having the logic value "1", and an embodiment in which the voltage Vntc is applied to the gate terminal of the transistor TR9 (i.e., the voltage Vntc is selected as the voltage Va) and the voltage Vztc is applied to the gate terminal of the transistor TR10 (i.e., the voltage Vztc is selected as the voltage Vb) in response to the selection signal SEL having the logic value "0" will be described.

However, it is understood that the concept of the present invention may include other embodiments in which one of a voltage having a magnitude corresponding to the magnitude of the voltage Vntc and a voltage having a magnitude corresponding to the magnitude of the voltage Vztc is applied to the gate terminal of the transistor TR9 and the other thereof is applied to the gate terminal of the transistor TR10 in response to any logical value of the selection signal SEL.

Just as the magnitude of the voltage Vout2 may vary with the voltage Va and the voltage Vb selected by the select signal SEL, and the magnitudes of the feedback voltage Vfb and the read voltage Vread2 may vary with the voltage Va and the voltage Vb selected by the select signal SEL. The relationship between the selection signal SEL and the read voltage Vread2 will be described with reference to fig. 13.

Fig. 8 is a circuit diagram illustrating an example configuration of the compensation current generation circuit of fig. 6 and/or 7 according to some embodiments of the inventive concept. Fig. 8 shows a transistor TR9 that receives the voltage Va and a transistor TR10 that receives the voltage Vb (corresponding to the example of fig. 7). For example, in response to the selection signal SEL "0", the transistor TR9 may receive the voltage Vntc, and the transistor TR10 may receive the voltage Vztc.

Referring to fig. 8, the transistor TR9 of fig. 6 and/or 7 may be at least one enable transistor selected from a plurality of transistors (transistors of a group corresponding to a reference numeral "TR 9"). The transistor TR10 of fig. 6 and/or 7 may be at least one enable transistor selected from a plurality of transistors (transistors of a group corresponding to reference numeral "TR 10"). For example, the transistor TR9 may be one or more of the transistors TR9_1 to TR9_4, the transistor of the group G1, and the transistor of the group G2 that are enabled. The transistor TR10 may be one or more of the transistors TR10_1 to TR10_4, the transistor of the group G3, and the transistor of the group G4 that are enabled.

the width of the transistor that can be selected as the transistor TR9 may be different. For example, the width of the transistor TR9_1 may be "8W", the width of the transistor TR9_2 may be "4W", the width of the transistor TR9_3 may be "2W", and the width of the transistor TR9_4 may be "W". The width of each transistor in groups G1 and G2 may be "W". In other words, the width of the transistor TR9_1 may be about eight times the width "W", the width of the transistor TR9_2 may be about four times the width "W", and the width of the transistor TR9_3 may be about two times the width "W". In embodiments where the series connected transistors of group G1 are selected together, the transistors of group G1 may work together. In embodiments where the series connected transistors of group G2 are selected together, the transistors of group G2 may work together.

In embodiments where the transistors are connected in series, the channel length through which current flows may be increased, and thus the ratio of the channel width to the channel length may be decreased. Thus, the transistors in series can operate like transistors, with a width that is narrower than the width of each transistor. For example, transistors in series may behave like transistors, with the width being inversely proportional to the number of transistors in series. Thus, in embodiments where the series connected transistors of group G1 operate together, the operation of two transistors in group G1 may be similar to the operation of a transistor having a width of "(1/2) × W" or a width of about half of the width "W". As in the above description, the operation of the four transistors in group G2 may be similar to the operation of transistors having a width of "(1/4) × W" or a width of about one quarter of the width "W".

In the embodiment of fig. 8, the transistors that may be selected for the transistor TR9 may operate as transistors having widths of "(1/4) × W", "(1/2) × W", "2W", "4W", and "8W". That is, the transistor that can be selected for the transistor TR9 can operate as a transistor having a width of "(2 i) × W" (i is an integer, -2 ≦ i ≦ 3). In embodiments where each of the transistors TR7 and TR8 of the current source CS3 has a width "W," the width of the transistor that may be selected as transistor TR9 may be proportional to the width of transistors TR7 and TR8, respectively. While some embodiments of values for i in the range "-2 ≦ i ≦ 3" may be described with reference to FIG. 8, it should be understood that the inventive concept may include embodiments for other ranges of integers "i".

Therefore, one of various values may be selected as the width "W _ 9" of the transistor TR9 in equation 4. In an embodiment where the width "W _ 8" of the transistor TR8 is "W", a value that may be selected as "W _ 9" may be proportional to "W _ 8". The transistor TR9 may be configured such that a value proportional to "W _ 8" may be selected as "W _ 9". The transistor TR10 may have a configuration similar to that of the transistor TR 9. Therefore, additional description will be omitted to avoid redundancy.

In the example embodiment of FIG. 8, the code TC may be represented by 6 bits of data (i.e., TC<0>To TC<5>Each of which may be represented by 1-bit data). TC (tungsten carbide)<0>To TC<5>"2" which can indicate 6-bit data respectively⁰To 2⁵"value of position. For example, in the case of some embodiments, when the code TC is represented by "100010," TC<1>"and" TC<5>"can be" 1 "," TC<0>”、“TC<2>”、“TC<3>"and" TC<4>"may be" 0 ".

Referring to fig. 8, the current source CS4 may include a switching unit SW. The switching unit SW may include switches SW1 to SW 6. The switches SW1 through SW6 may receive corresponding bits of the code TC including TC <5> through TC <0 >. Each of TC <0> to TC <5> may be a logical value "0" or a logical value "1". Each of the switches SW1 through SW6 may be turned on in response to a logical value "1" and may be turned off in response to a logical value "0" of a corresponding bit of the code TC. For example, the logic values "1" and "0" of TC <0> to TC <5> may correspond to particular voltage amplitudes, respectively.

For example, in some embodiments, when code TC is represented by "100010" (i.e., when TC <1> and TC <5> are "1" and TC <0>, TC <2>, TC <3>, and TC <4> are "0"), switch SW1 and switch SW5 may be turned on, and switch SW2, switch SW3, switch SW4, and switch SW6 may be turned off.

When a particular switch of the switches SW 1-SW 6 is turned on, current may flow through the particular switch and the bias transistor in the current source CS4 connected to the particular switch and the differential pair in the transistor TR9 and the transistor TR 10. For example, in some embodiments, when switch SW1 is on, current may flow through transistor TR11_1 connected to switch SW 1. For example, in some embodiments, when switch SW5 is turned on, current may flow through the transistors of group G5 connected to switch SW5 and the differential pair of transistors TR9 and TR 10.

Current source CS4 may be a current mirror circuit corresponding to a replica of current source CS 3. The voltage Vbias may be a bias voltage commonly provided to current source CS3 and current source CS 4. Accordingly, in some embodiments, when the switches SW1 through SW6 are turned on, the mirror current obtained by mirroring the reference current Iref2 may flow through the bias transistors TR11_1 through TR11_4, the transistors of the group G5, and the transistors of the group G6, which are connected to the switches SW1 through SW 6. In detail, the magnitude of the current flowing through current source CS4 may be proportional to the magnitude of reference current Iref 2.

Also, as the width of the transistor becomes larger, the magnitude of the current flowing through the transistor may become larger. For example, the magnitude of the current flowing through the transistor may be proportional to the width of the transistor. The widths of the bias transistors TR11_1 to TR11_4 may be "16W", "8W", "4W", and "2W", respectively. The width of each transistor in group G5 and group G6 may be "2W". As described with reference to the transistors of groups G1-G4, the transistors of group G5 in series can operate as transistors having a width of "W". The transistors of group G6 in series may operate as a single transistor having a width of "(1/2) × W".

For example, in some embodiments, when only switch SW1 is on (in some embodiments, when only TC is<5>Is "1" and TC<0>To TC<4>At "0"), a current having a magnitude of "(Iref 2)/2" can flow through the transistor TR11_1 having a width of "16W". As in the above description, a current having a magnitude of "(Iref 2)/4" may flow through the transistor TR11_2 having a magnitude of "(Iref 2)/4"(Iref 2)/8" current may flow through transistor TR11_3, current having a magnitude of "(Iref 2)/16" may flow through transistor TR11_4, current having a magnitude of "(Iref 2)/32" may flow through the transistors of group G5, and current having a magnitude of "(Iref 2)/64" may flow through the transistors of group G6. That is, having an amplitude of "(2)^j) Current of (Iref2) "may flow through the transistors TR11_1 to TR11_4, the transistors of group G5 and the transistors of group G6 (j is an integer, -6 ≦ j ≦ -1). An exemplary range of "-6 ≦ j ≦ -1" is described with reference to FIG. 8, however, it should be understood that embodiments of other ranges of the integer "j" may be included with the inventive concept.

in some embodiments, when only one of the switches SW 1-SW 6 is turned on, the magnitude of the current flowing through the current source CS may be one of "(Iref 2)/2", "(Iref 2)/4", "(Iref 2)/8", "(Iref 2)/16", "(Iref 2)/32", and "(Iref 2)/64". In some embodiments, when two or more of the switches SW1 to SW6 are turned on, the magnitude of the current flowing through the current source CS may correspond to the sum of the magnitudes of the currents flowing through the turned-on switches among "(Iref 2)/2", "(Iref 2)/4", "(Iref 2)/8", "(Iref 2)/16", "(Iref 2)/32", and "(Iref 2)/64". Thus, the magnitude of the current flowing through current source CS4 may correspond to a current of "(2 ″)^j) And (Iref2) "represents the sum of the numbers. That is, the magnitude of the current flowing through current source CS4 may be selected to be proportional to the magnitude of reference current Iref2 according to code TC.

The compensation current ITC2 may be output as a current flowing through the switching unit SW. Accordingly, the magnitude of compensation current ITC2 may correspond to the magnitude of the current flowing through current source CS4 (e.g., the magnitudes may be substantially equal to each other). This may mean that the magnitude of the compensation current ITC2 is selected to be proportional to the magnitude of the reference current Iref 2.

For example, in some embodiments, when the code TC has a reference value, it may be output with the smallest of the selectable amplitudes (e.g., reference current amplitude: e.g., 2)^-6Iref2)) of the compensation current ITC 2. In some embodiments, therefore, when the value of the code TC increases by the reference value,The magnitude of the offset current ITC2 may increase the reference current magnitude.

For example, in some embodiments, when the reference value of the code TC is "000001", the magnitude of the compensation current ITC2 may increase by "(Iref 2)/64" whenever the value of the code TC increases by "000001", where "(Iref 2)/64" may be the magnitude of the current flowing through the switch SW6 and the transistors of the group G6. For example, the magnitude of the compensation current ITC2 selected by the code TC having the value "000100" is "(Iref 2)/16", and the magnitude of the compensation current ITC2 selected by the code TC having the value "000101" is "(Iref 2)/64+ (Iref 2)/16".

As described with reference to fig. 6, in an embodiment in which the characteristics of the transistor TR9 and the transistor TR10 selected by the code TC are substantially identical to each other, the magnitude of the current I41 may be substantially equal to the magnitude of the current I42. Thus, the magnitude of the current flowing through current source CS4 may be proportional to the magnitude of reference current I41. Also, in an embodiment in which the characteristics of the transistor TR7 and the transistor TR8 are substantially the same as each other, the magnitude of the current I31 may be substantially equal to the magnitude of the current I32. Thus, the magnitude of current I32 of fig. 6 may be proportional to the magnitude of reference current Iref 2.

The magnitude of current I32 may be proportional to the magnitude of reference current Iref2, and the magnitude of current I41 may also be proportional to the magnitude of reference current Iref 2. According to the above description, in equations 3 and 4, "I41" may have a value proportional to "I32". The compensation current generation circuit 2131 may be configured to output a current I41 having a magnitude proportional to the magnitude of the current I32 based on the procedure described with reference to the operation of the current source CS 4.

In equations 3 and 4, in an embodiment where "W _ 9" has a value proportional to "W _ 8" and "I41" has a value proportional to "I32",May have a value independent of the temperature and the value of the code TC. Therefore, the magnitude of the feedback voltage Vfb calculated according to equations 3 and 4 may be linear with the values of the temperature and the code TC. Since the magnitude of the read voltage Vread2 correspondsThe magnitude of the read voltage Vread2 can be linear with the temperature and the value of the code TC due to the magnitude of the feedback voltage Vfb. For example, the magnitude of the read voltage Vread2 may have a reference voltage value in response to the code TC of the reference value. Also, the magnitude of the read voltage Vread2 may increase the reference voltage magnitude each time the value of the code TC increases the reference magnitude.

The read voltage generation circuit 2000 may be configured to output a read voltage Vread2 having a magnitude linear with the temperature and the value of the code TC. Since the magnitude of the read voltage Vread2 may correspond to the magnitude of the feedback voltage Vfb, the read voltage generation circuit 2000 may be configured to output the read voltage Vread2 including a magnitude linear with the temperature and the value of the code TC. Some embodiments of selecting the transistor TR9 and the transistor TR10 by the code TC will be described with reference to fig. 9 to 11.

fig. 9 is a circuit diagram for describing an example operation of the compensation current generation circuit of fig. 8 according to some embodiments of the inventive concept. In the operation shown in fig. 9, one transistor TR9_1 may be selected as the transistor TR9, and one transistor TR10_1 may be selected as the transistor TR 10.

For example, the switching element SW of the current source CS4 may receive a code TC having "100000" (i.e. only the code value TC <5> is "1" and the remaining values are "0") from the logic circuit. When the switch SW1 is turned on in response to the logic value "1", a current of (Iref2)/2 "can flow through the transistor TR11_ 1.

When a current of "I41 + I42" flows through the transistor TR11_1, a current I41 may flow through the transistor TR9_1, and a current I42 may flow through the transistor TR10_1 electrically connected to the transistor TR11_ 1. When the current I41 and the current I42 flow through the transistors TR9_1 and TR10_1, respectively, the current I41 and the current I42 may be input to the transistor TR9 and the transistor TR10, respectively. In an embodiment in which the transistor TR7 and the transistor TR8 of the reference current generating circuit 2120 are symmetrical to each other, the magnitude of the current I32 may be "I41 + I42".

Therefore, based on the code TC of "100000", the magnitudes of the current I41 and the current I42 may be selected as specific values, the transistor TR9_1 may be selected as the transistor TR9, and the transistor TR10_1 may be selected as the transistor TR 10.

fig. 10 is a circuit diagram for describing an example operation of the compensation current generation circuit of fig. 8 according to some embodiments of the inventive concept. In the operation shown in fig. 10, two or more transistors TR9_5 and TR9_6 may be selected as the transistor TR9, and two or more transistors TR10_5 and TR10_6 may be selected as the transistor TR 10.

For example, the switching cell SW of the current source CS4 may receive a code TC having "000010" from the logic circuit (i.e. only the code value TC <1> is "1" and the remaining values are "0"). When the switch SW _5 is turned on in response to the logic value "1", a current of "I41 + I42" may flow through the transistors TR11_5 and TR11_6 of the group G5.

When a current of "I41 + I42" flows through the transistors TR11_5 and TR11_6, the current I41 may flow through the transistors TR9_5 and TR9_6 of the G1 group electrically connected to the transistor TR11_5, and the current I42 may flow through the transistors TR10_5 and TR10_6 of the G3 group electrically connected to the transistor TR11_ 5. When the current I41 flows through the transistors TR9_5 and TR9_6 and through the transistors TR10_5 and TR10_6, the current I41 and the current I42 may be input to the transistor TR9 and the transistor TR10, respectively. In an embodiment in which the transistor TR7 and the transistor TR8 of the reference current generating circuit 2120 are symmetrical to each other, the magnitude of the current I32 may be "I41 + I42".

Therefore, based on the code TC of "000010", the magnitudes of the current I41 and the current I42 may be selected as specific values, the transistors TR9_5 and TR9_6 of the group G1 may be selected as the transistor TR9, and the transistors TR10_5 and TR10_6 of the group G3 may be selected as the transistor TR 10.

Fig. 11 is a circuit diagram for describing an example operation of the compensation current generation circuit of fig. 8 according to some embodiments of the inventive concept. In the operation shown in fig. 11, the transistor TR9_1 and the transistors TR9_5 and TR9_6 of the group G1 may be selected together as the transistor TR 9. The transistor TR10_1 and the transistors TR10_5 and TR10_6 of the group G3 may be selected together as the transistor TR 10.

In embodiments where the transistors are connected in parallel, current may flow through a channel of wider width. Thus, the operation of the transistors connected in parallel may be similar to the operation of one transistor whose width corresponds to the sum of the transistor widths. In an operation in which a parallel-connected transistor is selected as the transistor TR9, "W _ 9" of equation 4 may correspond to the sum of the widths of the selected transistors. For example, in an operation in which the transistor TR9_1 and the transistors TR9_5 and TR9_6 operate together as the transistor TR9, "W _ 9" may be "(8 +1/2) × W", which corresponds to the sum of "8W" and "(1/2) × W".

In the operation shown in fig. 11, the switching element SW of the current source CS4 may receive the code TC represented by "100010" from the logic circuit (i.e., the code values TC <1> and TC <5> are "1", and the remaining values are "0"). When the switch SW _5 is turned on in response to the logic value "1", a current of "I41 _2+ I42_ 2" may flow through the transistors TR11_5 and TR11_6 of the group G5. When the switch SW _1 is turned on in response to the logic value "1", a current of "I41 _1+ I42_ 1" may flow through the transistor TR11_ 1.

For example, when a current of "I41 _2+ I42_ 2" flows through the transistors TR11_5 and TR11_6, the current I41_2 may flow through the transistors TR9_5 and TR9_6 of the G1 group electrically connected to the transistor TR11_5, and the current I42_2 may flow through the transistors TR10_5 and TR10_6 of the G3 group electrically connected to the transistor TR11_ 5. When a current of "I41 _1+ I42_ 1" flows through the transistor TR11_1, a current I41_1 may flow through the transistor TR9_1, and a current I42_1 may flow through the transistor TR10_ 1.

When current flows through the transistors TR9_5 and TR9_6, the transistors TR10_5 and TR10_6, the transistor TR9_1, and the transistor TR10_1, the current I41 and the current I42 may be input to the transistor TR9 and the transistor TR10, respectively. Also, in an embodiment in which the transistor TR7 and the transistor TR8 of the reference current generating circuit 2120 are symmetrical to each other, the magnitude of the current I32 may be "I41 + I42".

That is, based on the code TC of "100010", the magnitudes of the current I41 and the current I42 may be selected as specific values, the transistors TR9_5 and TR9_6 and the transistor TR9_1 of the group G1 may be selected as the transistor TR9, and the transistors TR10_5 and TR10_6 and the transistor TR10_1 of the group G3 may be selected as the transistor TR 10.

As described with reference to fig. 9 to 11, in the embodiment of fig. 8, "W _ 9" of equation 4 may selectively have one of "(1/4) × W", "(1/2) × W", "2W", "4W", and "8W", or a sum of two or more of "(1/4) × W", "(1/2) × W", "2W", "4W", and "8W", depending on the value of the code TC. That is, the width "W _ 9" of the transistor TR9 in equation 4 may be variously selected to have a value proportional to the width "W" of the transistor TR 8.

Also, as described with reference to fig. 8, depending on the value of the code TC, the magnitude of the compensation current ITC2 may selectively have one of "(Iref 2)/2", "(Iref 2)/4", "(Iref 2)/8", "(Iref 2)/16", "(Iref 2)/32" and "(Iref 2)/64", or a sum of two or more of "(Iref 2)/2", "(Iref 2)/4", "(Iref 2)/8", "(Iref 2)/16", "(Iref 2)/32" and "(Iref 2)/64".

Since the magnitude of the current I41 may be proportional to the magnitude of the compensation current ITC2 (e.g., the magnitude of the current I41 may be 1/2 times the magnitude of the compensation current ITC 2), the "I41" may be differently selected to have a value proportional to the magnitude of the reference current Iref 2. Since the magnitude of the current I32 may be proportional to the magnitude of the reference current Iref2 (e.g., the magnitude of the current I32 may be 1/2 times the magnitude of the reference current Iref2), the "I32" may be differently selected to have a value proportional to the magnitude of the reference current Iref 2. Accordingly, "I41" in equation 4 may be variously selected to have a value proportional to "I32".

fig. 12 is a graph illustrating voltages received by the compensation circuit of fig. 4 according to some embodiments of the inventive concept. In the example of the graph of fig. 12, the x-axis may represent temperature in units of c, and the y-axis may represent the magnitude of voltage in units of V. The graph of fig. 12 represents the amplitude of the voltages Vztc and Vntc as a function of temperature at a particular value of the code TC.

Referring to fig. 12, the magnitude of the voltage Vntc may be in negative proportion to the temperature. The amplitude of the voltage Vztc may be uniform regardless of temperature variations. As described with reference to fig. 1, the voltage Vztc and the voltage Vntc may be received from a voltage generator included in the memory system. For example, the voltage generator may detect a temperature change of the memory system. The voltage generator may output voltages Vztc and Vntc of magnitudes corresponding to the detected temperature. For example, in the operation at the temperature "T1", the voltage generator may output the voltage Vztc of "V1" and the voltage Vntc of "V2". For example, in the operation at the temperature "T2", the voltage generator may output the voltage Vztc of "V1" and the voltage Vntc of "V1" equal in magnitude to the voltage Vztc.

Fig. 13 is a graph illustrating the read voltage of fig. 4 according to a selection signal, according to some embodiments of the inventive concept. In the graph of fig. 13, the x-axis may represent the value of the code TC, and the y-axis may represent the magnitude of the read voltage Vread 2.

The graph of fig. 13 is shown with respect to a continuous value of the code TC, but in some embodiments, the actual value of the code TC may not be continuous. However, in order to easily describe how the magnitude of the read voltage Vread2 varies with the value of the code TC, the graph may be shown to be continuous with respect to the value of the code TC.

As described with reference to fig. 7, in some embodiments, when the selection signal SEL has a logic value of "1", the voltage Vztc may be selected as the voltage Va, and the voltage Vntc may be selected as the voltage Vb. Also, when the selection signal SEL has a logic value "0", the voltage Vntc may be selected as the voltage Va, and the voltage Vztc may be selected as the voltage Vb.

Referring to equation 3, the magnitude of the voltage Vout2 in fig. 7 may be represented by equation 5.

[ equation 5]

Vfb＝Vref+α*(Va-Vb)

the value of "Vntc" may be negative proportional to temperature. Also, "Vztc" may have a value that is uniform regardless of temperature. In equation 5, "Vfb" may be calculated as a value that is negatively proportional to temperature in an operation in which "Va" is "Vntc" and "Vb" is "Vztc" (for example, the logical value of the selection signal SEL is "0"). In equation 5, "Vfb" may be calculated as a value proportional to the temperature in an operation in which "Va" is "Vztc" and "Vb" is "Vntc" (for example, the logical value of the selection signal SEL is "1").

as described with reference to fig. 4, the magnitude of the read voltage Vread2 may correspond to the magnitude of the feedback voltage Vfb, and the magnitude of the feedback voltage Vfb may correspond to the magnitude of the voltage Vout 2.

since the threshold voltage of the memory cell varies with various conditions, the read voltage Vread2 having a magnitude varying with the threshold voltage of the memory cell may be provided to accurately read data stored in the memory cell. In an embodiment where the read voltage Vread2 is expected to have an increasing magnitude according to an increase in the value of the code TC, the logic circuit may output the selection signal SEL having a logic value "1". In an embodiment where the read voltage Vread2 is expected to have a magnitude that decreases according to an increase in the value of the code TC, the logic circuit may output the selection signal SEL having a logic value of "0".

Fig. 14 is a graph illustrating voltages output from the read voltage generation circuit of fig. 1 and/or 4 according to some embodiments of the inventive concept. In the example of the graph of fig. 14, the x-axis may represent temperature in units of ° c, and the y-axis may represent voltage amplitude in units of V.

Referring to fig. 14, the magnitude of the read voltage Vread1 and the magnitude of the read voltage Vread2 may decrease as the temperature increases. Over the temperature domain of fig. 14, the variation of the differential non-linearity (DNL) value of the voltage Vout1 may be larger than the variation of the DNL value of the read voltage Vread 2.

The DNL value may be associated with the difference between the magnitude of the ideal linear voltage and the magnitude of the actual voltage over a particular domain. That is, the DNL value may be associated with the linearity of the voltage amplitude over a particular domain. In the specification, the high linearity of the voltage may mean that a variation of the DNL value of the voltage amplitude on a specific domain is small.

as described with reference to fig. 4 to 11, since the voltage generation circuit 2000 is configured to output the read voltage Vread2 whose magnitude is proportional to temperature, the magnitude of the read voltage Vread2 output from the voltage generation circuit 2000 may have high linearity over a temperature domain. Referring to fig. 1 and 4, the linearity of the read voltage Vread2 output from the voltage generation circuit 2000 may be higher than the linearity of the read voltage Vread1 output from the voltage generation circuit 1000 over a temperature domain.

As described with reference to fig. 8, "W _ 9" and "I41" of equation 4 may be selected to have values proportional to "W _ 8" and "I32". Therefore, "α" of equation 4 can be calculated as a constant independent of temperature. However, "α" of equation 2 may include a square root term (a term that is non-linear with temperature). Therefore, the linearity of the read voltage Vread2 may be higher than that of the read voltage Vread1 over a temperature domain.

Fig. 15 is a graph illustrating voltages output from the read voltage generation circuit of fig. 1 and/or 4 according to some embodiments of the inventive concept. In the example of the graph of fig. 15, the x-axis may represent the value of the code TC, TC1, or TC2, and the y-axis may represent the magnitude of the voltage in units of V.

Referring to fig. 15, the magnitude of the read voltage Vread1 and the magnitude of the read voltage Vread2 may increase as the value of the code TC increases. On a code domain, the change in the DNL value of the read voltage Vread1 may be greater than the change in the DNL value of the read voltage Vread 2.

As described with reference to fig. 4 to 11, since the read voltage generation circuit 2000 is configured to output the read voltage Vread2 whose magnitude is proportional to the value of the code TC, the magnitude of the read voltage Vread2 output from the compensation circuit 2100 may have high linearity over the code domain. Referring to fig. 1 and 4, the linearity of the read voltage Vread2 output from the voltage generation circuit 2000 may be higher than the linearity of the read voltage Vread1 output from the read voltage generation circuit 1000 in a code domain.

As described with reference to fig. 8, "W _ 9" and "I41" of equation 4 may be selected to have values proportional to "W _ 8" and "I32". Therefore, "α" of equation 4 can be calculated as a constant regardless of the value of the code TC. However, "α" of equation 2 may include square root terms (terms that are non-linear with codes TC1 and TC 2). Thus, the linearity of the read voltage Vread2 may be higher than the linearity of the read voltage Vread1 over the code domain.

Fig. 16 is a block diagram illustrating an example memory system including the read voltage generation circuit of fig. 1 and/or 4, according to some embodiments of the inventive concepts.

Memory system 3000 may include a host 3100, a memory controller 3200, and a memory device 3300. Memory device 3300 may include memory devices 3300_1 through 3300_ n. Each of the memory devices 3300_1 to 3300_ n may include a logic circuit and a voltage generator. For example, the memory device 3300_1 may include a logic circuit 3210_1 and a voltage generator 3220_ 1.

Memory controller 3200 may exchange command signals CMD, data signals DAT, and address signals ADDR with host 3100. The command signals CMD may be associated with the operation of the memory device 3300. The data signals DAT may indicate data stored or to be stored in the memory device 3300. The address signal ADDR may indicate an address of a particular memory cell in the memory device 3300 corresponding to a location where data is stored or is to be stored.

The voltage generator 3220_1 may generate the voltages Vztc and Vntc of fig. 1 and 4 and the reference voltage Vref. For example, the voltage generator 3220_1 may generate the voltages Vztc and Vntc based on the temperature of the memory system 3000. The logic circuit 3210_1 may generate the codes TC1 and TC2 of fig. 1 and the code TC of fig. 4.

Each of the memory devices 3300_1 to 3300_ n may include at least one of the read voltage generation circuits 1000 and 2000 of fig. 1 and 4. Each of the memory devices 3300_1 to 3300_ n may generate a read voltage Vread1 or Vread2 based on the voltages Vztc and Vntc, the reference voltage Vref, the codes TC1 and TC2, and the code TC. For example, logic 3220 may track changes in threshold voltages of memory cells in memory device 3300 to determine the values of codes TC1 and TC2, as well as the value of code TC. Logic 3220 may output the codes TC1, TC2, and TC of the determined values to memory device 3300.

The memory devices 3300_1 to 3300_ n of the memory device 3300 may store or output data under the control of the memory controller 3200. The memory devices 3300_1 to 3300_ n may read data by using a read voltage Vread1 or Vread 2. The memory devices 3300_1 to 3300_ n may have the same configuration or may have a similar configuration. Alternatively, the memory devices 3300_1 to 3300_ n may have different configurations.

For example, each of the memory devices 3300_1 to 3300_ n may include volatile memory (such as SRAM, DRAM, SDRAM, etc.), or nonvolatile memory (such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc.). Alternatively, memory devices 3300_1 through 3300_ n may include heterogeneous memory.

According to some embodiments of the inventive concept, an electronic circuit may be provided that generates a read voltage whose amplitude varies with changes in temperature and code value.

While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.