阅读说明：本技术 垂直全环栅库架构 (Vertical all-around grid library architecture ) 是由 理查德·T·舒尔茨 于 2018-04-27 设计创作，主要内容包括：描述了一种用于创建垂直全环栅标准单元的布局的系统和方法。环绕在硅衬底上形成的两个垂直纳米线片布置金属栅极。在所述两个垂直纳米线片之间在所述金属栅极上形成栅极触点。将栅极延伸金属(GEM)布置在所述金属栅极上方至少所述栅极触点上。在所述GEM上的某个位置处形成栅极通孔,在所述位置处可使用局部互连层来布线栅极连接。布置局部金属层被以用于连接局部路线和电源连接。(A system and method for creating a layout of vertical full gate-all-around standard cells is described. A metal gate is disposed around two vertical nanowire slices formed on a silicon substrate. Forming a gate contact on the metal gate between the two vertical nanowire sheets. A Gate Extension Metal (GEM) is arranged over the metal gate at least on the gate contact. A gate via is formed at a location on the GEM where a local interconnect layer may be used to route a gate connection. A local metal layer is arranged for connecting the local routes and the power supply connections.)

1. A semiconductor device processing method for creating a standard cell layout, comprising:

Forming a plurality of vertical nanowire sheets on a silicon substrate;

disposing a metal gate around the plurality of vertical nanowire sheets;

Forming a gate contact on the metal gate between two vertical nanowire slices of the plurality of vertical nanowire slices;

Disposing a Gate Extension Metal (GEM) over the metal gate on the gate contact; and

A gate Via (VGEM) is formed at a location on the GEM where a local interconnect layer may be used to route a gate connection.

2. The semiconductor device processing method of claim 1, wherein the GEM allows connections between the local interconnect layer and the metal gate to occur along a length of a corresponding device.

3. The semiconductor device processing method of claim 1, wherein a first of the two vertical nanowire slices is used to create a p-channel device and a second of the two vertical nanowire slices is used to create an n-channel device.

4. The semiconductor device processing method of claim 1, wherein the local interconnect layer for routing the gate connection is a local metal zero layer.

5. The semiconductor device processing method of claim 1, further comprising forming two metal contacts on the two vertical nanowire slices to create a source region and a drain region, wherein each of the GEM and the VGEM is not connected to the two metal contacts.

6. The semiconductor device processing method of claim 5, wherein each of the source and drain regions uses at least a titanium silicide contact to connect a local interconnect comprising a metal zero layer.

7. The semiconductor device processing method of claim 6, wherein the method further comprises disposing a Gate Extension Metal (GEM) on the titanium silicide contact and the metal contact over one or more of the two vertical nanowire slices.

8. the semiconductor device processing method of claim 5, wherein the method further comprises disposing a local metal layer within the standard cell for connecting local routing and power connections.

9. A semiconductor structure, comprising:

A plurality of vertical nanowire tiles located on a silicon substrate;

A metal gate disposed around the plurality of vertical nanowire tiles;

A gate contact formed on the metal gate between two of the plurality of vertical nanowire slices;

a Gate Extension Metal (GEM) disposed over the metal gate on the gate contact; and

A gate Via (VGEM) formed at a location on the GEM where a gate connection may be routed using a local interconnect layer.

10. The standard cell layout of claim 9, wherein the GEM allows connections between the local interconnect layer and the metal gates to occur along a length of a corresponding device.

11. The standard cell layout of claim 9, wherein a first of the two vertical nanowire tiles is used to create a p-channel device and a second of the two vertical nanowire tiles is used to create an n-channel device.

12. The standard cell layout of claim 9 wherein the local interconnect layer used to route the gate connection is a local metal zero layer.

13. The standard cell layout of claim 9, further comprising two metal contacts formed on the two vertical nanowire slices to create a source region and a drain region, wherein each of the GEM and the VGEM are not connected to the two metal contacts.

14. the standard cell layout of claim 13 wherein each of the source and drain regions uses at least a titanium silicide contact to connect a local interconnect comprising a metal zero layer.

15. a non-transitory computer readable storage medium storing program instructions, wherein the program instructions for executing a semiconductor processing method are executable by a processor to:

forming a plurality of vertical nanowire sheets on a silicon substrate;

Disposing a metal gate around the plurality of vertical nanowire sheets;

Forming a gate contact on the metal gate between two vertical nanowire slices of the plurality of vertical nanowire slices;

disposing a Gate Extension Metal (GEM) over the metal gate on the gate contact; and

A gate Via (VGEM) is formed at a location on the GEM where a local interconnect layer may be used to route a gate connection.

16. the non-transitory computer-readable storage medium of claim 15, wherein the GEM allows connections between the local interconnect layer and the metal gate to occur along a length of a corresponding device.

17. The non-transitory computer-readable storage medium of claim 15, wherein a first of the two vertical nanowire tiles is used to create a p-channel device and a second of the two vertical nanowire tiles is used to create an n-channel device.

18. The non-transitory computer readable storage medium of claim 15, wherein the program instructions are further executable by a processor to form two metal contacts on the two vertical nanowire slices to create a source region and a drain region, wherein each of the GEM and the VGEM are not connected to the two metal contacts.

19. The non-transitory computer readable storage medium of claim 18, wherein each of the source and drain regions connects a local interconnect comprising a metal zero layer using at least a titanium silicide contact.

20. the non-transitory computer readable storage medium of claim 19, wherein the program instructions are further executable by a processor to arrange a Gate Extension Metal (GEM) on a metal contact over the titanium silicide contact and one or more of the two vertical nanowire slices.

Background

drawings

The above advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings in which:

fig. 1 is a generalized diagram of a top view of a layout for processing a vertical full gate all around standard cell.

fig. 2 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 3 is a generalized diagram of another top view of a layout for processing a vertical full gate all standard cell.

Fig. 4 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 5 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 6 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 7 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 8 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 9 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 10 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 11 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 12 is a generalized diagram of another top view of a layout for processing a vertical full gate all standard cell.

Fig. 13 is a generalized diagram of another top view of a layout for processing a vertical full gate all around standard cell.

Fig. 14 is a generalized diagram of a cross-sectional view of a semiconductor structure for a vertical all-around gate device to be processed.

FIG. 15 is a generalized diagram of a method for creating a layout of a vertical full gate all around standard cell.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the appended claims.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the methods and mechanisms presented herein. However, it will be recognized by one of ordinary skill in the art that various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the methods described herein. It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements.

Systems and methods for creating a layout of vertical full gate-all standard cells are contemplated. In various embodiments, a semiconductor device processing method for creating a vertical Gate All Around (GAA) standard cell layout forms a plurality of vertical nanowire tiles on a silicon substrate. The method arranges the metal full-wrap gate vertical nanowire slices and forms a gate contact on the metal gate, the gate contact being located between two vertical nanowire slices. A first vertical nanowire slice of the two vertical nanowire slices is used to create a p-channel device and a second vertical nanowire slice is used to create an n-channel device.

The method arranges a Gate Extension Metal (GEM) on a gate contact over a metal gate without connecting to the metal gate. GEM allows the connection between the local interconnect layer and the metal gate to occur along the length of the corresponding device. Further, the method forms a gate Via (VGEM) at a location on the GEM where a local interconnect layer may be used to route the gate connection. The method then forms two metal contacts on the two vertical nanowire sheets to create a source region and a drain region. Each of the GEM and VGEM is not connected to two metal contacts. A local metal layer is arranged for connecting the local routes and the power supply connections.

In the following description, the vertical all-gate standard cell layout architecture shown in fig. 1-13 provides a standard cell of a vertical all-Gate (GAA) device, where the standard cell uses power stubs or posts rather than power rails routed across the standard cell. The layout architecture of standard cells using vertical GAA devices is different from the layout architecture of standard cells using horizontal GAA devices or Trigate devices. Fig. 1 through 13 illustrate the layout of the multiplexer recombination gate using vertical GAA devices. However, the layout techniques shown in fig. 1-13 may be used for various other standard cells for other composite gates and functional cells.

Turning now to fig. 1, a generalized block diagram of a top view of a standard cell layout 100 is shown. A cross-section of the vertical gate semiconductor structure 120 follows the layout 100. The standard cell layout 100 for the multiplexer uses six p-type Metal Oxide Semiconductor (MOS) Field Effect Transistors (FETs) or p-channel non-planar devices on top of the layout. In addition, the standard cell layout 100 for the multiplexer uses six n-type MOSFETs or n-channel non-planar devices at the bottom of the layout. For the top left p-type device, the active region 102 is highlighted. The vertical nanowire sheet 146A comes out of the page in three dimensions. The vertical nanowire patch 146A is contained in a region within the inner rectangle within the active region 102. The Gate All Around (GAA) metal 124 wraps around the vertical nanowire 146A in the gate region in a 360 degree manner. Layer 108 is used to cut the gate layer and shows the starting and ending locations of the metal gates. Titanium silicide (ti-silicide) contacts 122 are used to provide local interconnects to active regions, such as source and drain regions. In some embodiments, titanium silicide contact 122 uses titanium disilicide (TiSi 2).

Starting from the left, the second and fifth columns in layout 100 do not have metal gates running continuously from p-type mosfet (pfet) to n-type mosfet (nfet), so these devices are disconnected at the gate terminal. In contrast, the first, third, fourth and sixth columns have metal gates running continuously from pfet to nfet, so these devices are connected at the gate terminals. For example, the connected devices may be used in an inverter circuit. In some implementations, self-aligned double patterning (SADP) techniques are used to form the metal gate.

The semiconductor structure 120 illustrates a cross-sectional view of a processing technique for a vertical GAA device and follows the layout 100. Current for a vertical GAA device flows from the bottom silicon substrate 144 up through the vertical nanowire slices 146A-146B in the gate region, through the Metal contact 128, through the Metal contact 130, through the Metal zero layer (M0 or Metal0)140, through the Metal via 136 and through the Metal one layer (M1 or Metal1) 142. In the illustrated embodiment, the metal contact 130 skips over the Gate Extension Metal (GEM) 132. The metal contacts 130 are copper, tungsten, or cobalt, and the materials used are based on a design tradeoff between resistance and process reliability.

Titanium silicide (TiSi2) contacts 122 are used for the source and drain regions. The metal gate 124 wraps around the vertical nanowire patch 146A-146B in the gate region in a 360 degree manner and does not pass through the vertical nanowire patch 146A-146B and does not sit on top of the vertical nanowire patch 146A-146B. A gate contact 126 connects the metal gate 124 to a Gate Extension Metal (GEM) 132. In the implementation shown, GEM132 is used only over gate contact 126.

Turning now to fig. 2, a generalized block diagram of a top view of a standard cell layout 200 is shown. The cross-section of the vertical gate semiconductor structure 120 follows the layout 200. The contacts, materials and structures described previously are numbered the same. Metal contacts 128 are formed to create contacts that connect to the vertical nanowire patches 146A-146B over the metal gate 124, but not to the metal gate 124. Metal contacts 128 are formed horizontally from one device to another to connect the source or drain in the circuit. Although not shown, in some embodiments, the metal contacts 128 are formed vertically when the gate contact 126 is not present, so as to connect the source and drain regions of a p-channel device to the source and drain regions of an n-channel device. If the bottom of a given device is the drain region, then the top of the given device is the source region, and vice versa.

Next, gate-on (GO) contacts 126 are formed in the standard cell layout 200. Each device has a single gate connection using gate contact 126. The gate contact 126, the first column from the left, and the third, fourth, and sixth columns may be shared as is. As previously described, these pfets and nfets have connected gate terminals.

The second and fifth columns have open gates and, therefore, each of pfets and nfets has a respective gate contact 126. For the second and fifth columns, separate gate contacts 126 are seen at the top of the cell and at the bottom of the cell. As previously described, the gate cut layer 108 is shown to disconnect the metal gates of the second and fifth columns.

It should be noted that for horizontal devices (transistors), the gate contact 126 can be placed in several locations on the top of the cell, in the middle of the cell, and at the bottom of the cell, such as over the active area, between the devices (pfet and nfet). This flexible arrangement also exists for horizontal GAA devices. However, vertical GAA devices do not have such a flexible arrangement. Looking at the layout 200, it can be seen that if the gate contact 126 moves too much, it will form an electrical short (connection) with the vertical nanowire patch 146A-146B, and then the gate terminal is shorted to either the source terminal or the drain terminal. Thus, for a vertical GAA device, the gate contact 126 is disposed in only one of the three locations.

The three locations of gate contact 126 include the top of cell layout 200, the middle of cell layout 200, and the bottom of cell layout 200. Each of these three locations is located away from the vertical slice shown in cell layout 200 (such as vertical slice 146A). Contacts 130 are then formed in cell layout 300. As shown, contact 130 terminates on either Titanium Silicide (TS) contact 122 or metal contact 128. Contacts 130 are used for the source and drain regions.

Referring to fig. 3, a generalized block diagram of a top view of a standard cell layout 300 is shown. The cross-section of the vertical gate semiconductor structure 120 follows the layout 300. The contacts, materials and structures described previously are numbered the same. Here, a Gate Extension Metal (GEM)132 is formed. Brackets and dashed boxes indicate the location of GEM132 in cell layout 300. As shown in structure 120, each of the GEM132 is also disposed on top of a gate-on (GO) contact 126 in the cell layout 300. As shown, in various implementations, GEM132 is not centered on GO contact 126. However, GEM132 is aligned over metal gate 124 and GO contact 126. This arrangement allows the gate 124 to be connected to an upper metal layer.

In the absence of GEM132, connections to the gate terminal, such as through GO contact 126, may only occur at the top, middle, or bottom of cell 300. There are only three horizontal rails available for routing the gate terminals of pfets and nfets. In the presence of GEM132, connections to the gate terminals can occur in more locations in cell layout 300, providing better routing flexibility. GEM132 allows the connection to the gate to occur vertically above the GO contact 126 and to either horizontal metal zero (M0)140 or vertical metal one (M1) 142. GEM132 allows the connection between a local interconnect layer (such as a later-disposed metal0 layer 140) and metal gate 124 through gate contact 126 to occur along the length of the corresponding device.

Referring to fig. 4, a generalized block diagram of a top view of a standard cell layout 400 is shown. The cross-section of the vertical gate semiconductor structure 120 follows the layout 400. The contacts, materials and structures described previously are numbered the same. Gate Vias (VGEM)134 for connecting GEM132 to horizontal M0140 are arranged in cell layout 400. Also, curly brackets indicate the location of GEM 132. The gate Via (VGEM)134 is not connected to the metal contact 128 or the metal gate 124. A gate Via (VGEM)134 is disposed at the location where GEM132 intersects a later Metal 0140.

Referring to fig. 5 through 7, generalized block diagrams of top views of standard cell layouts 500, 600, and 700 are shown. The cross-section of the vertical gate semiconductor structure 120 follows the layouts 500, 600 and 700. The contacts, materials and structures described previously are numbered the same. In fig. 5, horizontal Metal zero (Metal 0, M0) connections 140 are arranged in cell layout 500. The wiring can now be used both horizontally and vertically in the cell. It should be noted that the gate Vias (VGEM)134 are disposed at locations where the GEM layer 132 intersects the Metal0 layer 140.

Next, the connection from horizontal Metal0140 to vertical Metal 1142 is completed so that Metal vias 136 are arranged as shown in FIG. 6. Next, the vertical Metal1 layers 142 are arranged as shown in FIG. 7. The input and output pins may be selected to connect in Metal0140 or Metal 1142. A power (VDD) pin connection is shown at the top of cell layout 700 and a ground (VSS, GND) connection is formed at the bottom of cell layout 700. It should also be noted that no routing in the signal traces (GEM layer 132, horizontal Metal0140, and vertical Metal 1142) use a bend or L-shape. Metal layers that do not have a curvature or L-shape are referred to as unidirectional layers. The metal layer having a bent or L-shape is called a bidirectional layer, and the bidirectional layer blocks a wiring track, thus reducing wiring flexibility.

the above description for fig. 1-7 describes the steps for creating a vertical Gate All Around (GAA) standard cell layout using the Gate Extension Metal (GEM)132 only on the gate contact 126. However, in other implementations, the GEM132 is additionally disposed on the metal contacts 130 over the titanium silicide contacts 122 in the source and drain regions. Fig. 8 to 13 show these alternative steps. Referring to fig. 8, a generalized block diagram of a top view of a standard cell layout 800 is shown. The cross-section of the vertical gate semiconductor structure 820 follows the layout 800. The contacts, materials and structures described previously are numbered the same. As shown, the semiconductor structure 820 also uses a Gate Extension Metal (GEM)132 at the source and drain regions. The cell layout 800 on the right has been performed at each processing step prior to forming the GEM132 layer.

in the illustrated embodiment, the GEM132 is used in the gate region over the gate contact 126, as previously described, and is now additionally used in each of the source and drain regions over the titanium silicide contact 122. As shown, each of the metal contacts 130 immediately to the left and right of the middle GEM132 is a contact that skips the use of GEM 132. The metal contacts 130 and 138 are copper, tungsten or cobalt in use and the materials used are based on a design tradeoff between resistance and process reliability.

Referring to fig. 9, a generalized block diagram of a top view of a standard cell layout 900 is shown. The cross-section of the vertical gate semiconductor structure 820 follows the layout 900. The contacts, materials and structures described previously are numbered the same. In the illustrated embodiment, a GEM132 is formed. The dashed lines indicate the location of GEM132 in cell layout 900. Comparing fig. 9 with earlier fig. 3, it can be seen that when GEM132 is used in the source and drain regions, there are more GEM132 in the cell layout 900. GEM132 allows the connection between a local interconnect layer (such as a later-disposed metal0 layer 140) and metal gate 124 through gate contact 126 to occur along the length of the corresponding device.

Referring to fig. 10, a generalized block diagram of a top view of a standard cell layout 1000 is shown. The cross-section of the vertical gate semiconductor structure 820 follows the layout 1000. The contacts, materials and structures described previously are numbered the same. Gate Vias (VGEM)134 for connecting GEM132 to horizontal M0140 are arranged in cell layout 1000. Also, the dashed line indicates the location of GEM 132. The gate Via (VGEM)134 is not connected to the metal contact 128 or the metal gate 124. A gate Via (VGEM)134 is disposed at the location where GEM132 intersects a later Metal 0140.

Referring to fig. 11 through 13, generalized block diagrams of top views of standard cell layouts 1100, 1200 and 1300 are shown. The cross-section of the vertical gate semiconductor structure 820 follows the layouts 1100, 1200 and 1300. The contacts, materials and structures described previously are numbered the same. In fig. 11, horizontal Metal zero (Metal 0, M0) connections 140 are arranged in cell layout 1100. The wiring can now be used both horizontally and vertically in the cell. It should be noted that the gate Vias (VGEM)134 are disposed at locations where the GEM layer 132 intersects the Metal0 layer 140. It should also be noted that the horizontal Metal0140 route is a one-way route.

Next, the connection from horizontal Metal0140 to vertical Metal 1142 is completed so that Metal vias 136 are arranged as shown in FIG. 12. Next, the vertical Metal1 layers 142 are arranged as shown in FIG. 13. The input and output pins may be selected to connect in Metal0140 or Metal 1142. A power (VDD) pin connection is shown at the top of the cell layout 1300, and a ground (VSS, GND) connection is formed at the bottom of the cell layout 1300. It should also be noted that no routing in the signal routing (GEM layer 132, horizontal Metal0140, and vertical Metal 1142) uses unidirectional routing.

The above description for fig. 8-13 describes the steps for creating a vertical Gate All Around (GAA) standard cell layout using Gate Extension Metal (GEM)132 on the gate contact 126 and on the metal contact 130 over the titanium silicide contact 122 and additionally on the metal contact 130 over the vertical nanowire slices 146A-146B. However, in other implementations, the GEM132 is additionally disposed on the metal contacts 130 over the vertical nanowire sheets 146A-146B. Referring to fig. 14, a generalized block diagram of a cross-sectional view of a vertical gate semiconductor structure 1420 is shown. The contacts, materials and structures described previously are numbered the same. In various embodiments, the processing steps used to create the vertical standard cell layout of structure 1420 use similar steps previously described for structures 120 and 820.

referring now to fig. 15, one embodiment of a method 1500 for creating a layout of a vertical Gate All Around (GAA) standard cell is shown. The steps in this embodiment are shown in sequence for discussion purposes. However, in other embodiments, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

A metal gate is disposed around two vertical nanowire slices formed on a silicon substrate (block 1502). A gate contact is formed on the metal gate between the two vertical nanowire slices (block 1504). A Gate Extension Metal (GEM) is disposed over the metal gate at least on the gate contact (block 1506). A gate Via (VGEM) is formed at a location on the GEM where a gate connection may be routed using a local interconnect layer (block 1508). A local metal layer is arranged for connecting the local routes and the power connections (block 1510).

It should be noted that one or more of the above-described embodiments include software. In such embodiments, the program instructions implementing the methods and/or mechanisms are transmitted or stored on a computer readable medium. Various types of media which are configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (proms), Random Access Memory (RAM), and various other forms of volatile or non-volatile memory. Generally, a computer-accessible storage medium includes any storage medium that is accessible by a computer during use for providing instructions and/or data to the computer. For example, a computer-readable storage medium includes a storage medium such as a magnetic or optical medium (e.g., a diskette (fixed or removable)), a tape, a CD-ROM or DVD-ROM, a CD-R, CD-RW, a DVD-R, DVD-RW, or Blu-ray. The storage medium also includes volatile or non-volatile storage media such as RAM (e.g., Synchronous Dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.), SDRAM, low power DDR (LPDDR2, etc.), SDRAM, Rambus DRAM (RDRAM), static RAM (sram), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory) accessed via a peripheral interface such as a Universal Serial Bus (USB) interface, etc. Storage media includes microelectromechanical systems (MEMS) and storage media accessible via communication media such as a network and/or a wireless link.

Additionally, in various embodiments, the program instructions include behavioral level descriptions or Register Transfer Level (RTL) descriptions of hardware functionality in a high-level programming language such as C or a design language (HDL) such as Verilog, VHDL, or a database format such as GDS II flow format (GDSII). In some cases, the description is read by a synthesis tool that synthesizes the description to produce a netlist comprising a series of gates from a synthesis library. The netlist comprises a collection of gates that also represent the functionality of the hardware comprising the system. The netlist can then be placed and routed to produce a data set describing the geometry to be applied to the mask. The mask is then used in various semiconductor processing steps to produce a semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are the netlist (with or without a synthesis library) or the dataset, as desired. Or, instructions are utilized to facilitate the transfer of data from a supplier (such as,and Mentor) The hardware-based type of simulator of (1) performs the simulation.

Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.