阅读说明：本技术 工作周期调整系统、调整工作周期的方法及电路 (Work period adjusting system, method and circuit for adjusting work period ) 是由 沈瑞滨 蔡铭宪 蔡宗宪 于 2021-02-22 设计创作，主要内容包括：一种工作周期调整系统、调整工作周期的方法及电路,工作周期调整系统包括：一时间数字转换器,用以自一输入信号产生多个时间数字码；一工作周期索引产生器,用以基于所述多个时间数字码来计算该输入信号的一工作周期,且基于被计算的该工作周期来指派一工作周期索引；一输入相位指派产生器,用以基于该工作周期索引来产生一第一输出及一第二输出；一第一延迟线,用以延迟该第一输出以产生一第三输出；以及一工作周期产生器,用以基于该第三输出及该第二输出来调整该输入信号的该工作周期。此外,调整工作周期的方法及电路亦在此揭露。(A work period adjusting system, a method and a circuit for adjusting work period are provided, the work period adjusting system includes: a time-to-digital converter for generating a plurality of time-to-digital codes from an input signal; a duty cycle index generator for calculating a duty cycle of the input signal based on the plurality of time-to-digital codes and assigning a duty cycle index based on the calculated duty cycle; an input phase assignment generator for generating a first output and a second output based on the duty cycle index; a first delay line for delaying the first output to generate a third output; and a duty cycle generator for adjusting the duty cycle of the input signal based on the third output and the second output. In addition, a method and a circuit for adjusting the duty cycle are also disclosed.)

1. A duty cycle adjustment system, comprising:

a time-to-digital converter for generating a plurality of time-to-digital codes from an input signal;

a duty cycle index generator for calculating a duty cycle of the input signal based on the plurality of time-to-digital codes and assigning a duty cycle index based on the calculated duty cycle;

an input phase assignment generator for generating a first output and a second output based on the duty cycle index;

a first delay line for delaying the first output to generate a third output; and

a duty cycle generator for adjusting the duty cycle of the input signal based on the third output and the second output.

2. The duty cycle adjustment system of claim 1, wherein the time-to-digital converter comprises a second delay line having a plurality of delay stages, and wherein each of the plurality of delay stages generates one of the plurality of time-to-digital codes, an

Each of the plurality of delay stages includes a sampling unit to sample a fourth output from the associated one of the plurality of delay stages based on a sampling clock signal to generate the plurality of time-to-digital codes.

3. The duty cycle adjustment system of claim 1, wherein the duty cycle index generator is configured to count a number of the plurality of time-digital codes having a plurality of consecutive 1's and a plurality of consecutive 0's, and count the number of the plurality of time-digital codes having adjacent 0's and 1's to calculate the duty cycle of the input signal.

4. The duty cycle adjustment system of claim 1, wherein the duty cycle index is a first predetermined index value if the calculated duty cycle is equal to a first predetermined duty cycle value,

if the calculated duty cycle is less than a second predetermined duty cycle value, the duty cycle index is a second predetermined index value, an

If the calculated duty cycle is greater than a third predetermined duty cycle value, the duty cycle index is a third predetermined index value.

5. The duty cycle adjustment system of claim 1, wherein the input phase assignment generator comprises a first multiplexer and a second multiplexer, wherein each of the first multiplexer and the second multiplexer is configured to receive the input signal as a first input and an inverted input signal as a second input, wherein the first multiplexer is configured to receive a first portion of the duty cycle index to select the first input or the second input as the first output, and the second multiplexer is configured to receive a second portion of the duty cycle index to select the first input or the second input as the second output.

6. A method for adjusting a duty cycle, comprising:

generating a plurality of time-to-digital codes from an input signal through a time-to-digital converter of a duty cycle adjustment system;

counting, by a duty cycle index generator of the duty cycle adjustment system, a number of the plurality of time-digital codes having a plurality of consecutive 1 values, a plurality of consecutive 0 values, and adjacent 0 and 1 values for calculating a duty cycle and assigning a duty cycle index based on the calculated duty cycle;

generating, by an input phase assignment generator, a first output and a second output based on the duty cycle index; and

adjusting the duty cycle of the input signal based on the first output and the second output by a duty cycle generator of the duty cycle adjustment system.

7. The method of claim 6, wherein:

if the calculated work cycle is equal to a predetermined work cycle value, the work cycle index is a first predetermined index value;

if the calculated work period is less than the preset work period value, the work period index is a second preset index value; and is

If the calculated duty cycle is greater than the predetermined duty cycle value, the duty cycle index is a third predetermined index value.

8. The method of claim 6, wherein the input phase assignment generator comprises a first multiplexer and a second multiplexer, and wherein the method further comprises:

inputting the input signal as a first input and an inverted input signal as a second input into each of the first multiplexer and the second multiplexer;

inputting a first portion of the duty cycle index to the first multiplexer for selecting the first input or the second input as the first output; and

a second portion of the duty cycle index is input to the second multiplexer for selecting the first input or the second input as the second output.

9. A circuit for adjusting a duty cycle, comprising:

a first circuit for generating a duty cycle index from an input signal;

a first multiplexer for receiving the input signal as a first input, an inverted input signal as a second input, and a first bit of the duty cycle index as a select input to generate a first output, wherein the first output is the inverted input signal if the duty cycle index indicates a calculated duty cycle of the input signal is less than a predetermined duty cycle value, and the first output is the input signal if the duty cycle index indicates the calculated duty cycle of the input signal is greater than the predetermined duty cycle value;

a second multiplexer for receiving the input signal as the first input, the inverted input signal as the second input, and a second bit of the duty cycle index as the select input to generate a second output, wherein the second output is the input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is less than the predetermined duty cycle value, and the second output is the inverted input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is greater than the predetermined duty cycle value; and

a second circuit for adjusting a duty cycle of the input signal based on the first output and the second output.

10. The circuit of claim 9, further comprising:

a master delay line for receiving the input signal and generating a plurality of time-to-digital codes, wherein the duty cycle index is generated from the plurality of time-to-digital codes; and

a slave delay line for receiving the first output and generating a third output, wherein the third output is input to the second circuit together with the second output.

Technical Field

The present disclosure relates to a duty cycle adjustment system.

Background

Pulse signals are commonly used in digital circuits for various purposes, such as signaling memory read/write times, indicating the occurrence of events, providing timing synchronization, and the like. Proper functioning of the circuit typically requires that the pulse signal have a specified width. Failure to provide pulses for a sufficiently long time may result in incomplete downstream processing or may be completely undetected. Providing pulses for too long a time can result in erroneous downstream circuit operation (e.g., what should be a single pulse may be interpreted as multiple pulses). As circuit sizes scale down and operating speeds increase, it becomes important for power and circuit area efficiency, including proper pulse generation. However, the current configuration of the mechanism for generating pulses has limitations.

Disclosure of Invention

The present disclosure includes a duty cycle adjustment system. The duty cycle adjustment system includes: a time-to-digital converter is used for generating a plurality of time-to-digital codes from an input signal. A duty cycle index generator for calculating a duty cycle of the input signal based on the plurality of time-to-digital codes and assigning a duty cycle index based on the calculated duty cycle. An input phase assignment generator for generating a first output and a second output based on the duty cycle index. A first delay line for delaying the first output to generate a third output. And a duty cycle generator for adjusting the duty cycle of the input signal based on the third output and the second output.

The present disclosure includes a method of adjusting a duty cycle. The method comprises the following steps: generating a plurality of time-to-digital codes from an input signal through a time-to-digital converter of a duty cycle adjustment system; counting, by a duty cycle index generator of the duty cycle adjustment system, a number of time-digital codes having a plurality of consecutive 1 values, a plurality of consecutive 0 values, and adjacent 0 and 1 values for calculating a duty cycle and assigning a duty cycle index based on the calculated duty cycle; generating a first output and a second output based on the duty cycle index by an input phase assignment generator; a duty cycle generator of the duty cycle adjustment system adjusts the duty cycle of the input signal based on the first output and the second output.

The present disclosure includes a circuit for adjusting a duty cycle. The circuit comprises a first circuit, a first multiplexer, a second multiplexer and a second circuit. The first circuit is used for generating a duty cycle index from an input signal. The first multiplexer is configured to receive the input signal as a first input, an inverted input signal as a second input, and a first bit of the duty cycle index as a select input to generate a first output, wherein the first output is the inverted input signal if the duty cycle index indicates a calculated duty cycle of the input signal is less than a predetermined duty cycle value, and the first output is the input signal if the duty cycle index indicates a calculated duty cycle of the input signal is greater than the predetermined duty cycle value. The second multiplexer is configured to receive the input signal as a first input, the inverted input signal as a second input, and a second bit of the duty cycle index as a select input to generate a second output, wherein the second output is the input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is less than the predetermined duty cycle value, and the second output is the inverted input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is greater than the predetermined duty cycle value. The second circuit is used for adjusting a working period of the input signal based on the first output and the second output.

Drawings

Aspects of the present disclosure are better understood from the following detailed description when read with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is an exemplary block diagram of a duty cycle adjustment system according to some embodiments;

FIG. 2 is an exemplary block diagram of a time-to-digital converter of the duty cycle adjustment system of FIG. 1 in accordance with some embodiments;

FIG. 3 is an exemplary block diagram showing additional details of the time-to-digital converter of FIG. 2 according to some embodiments;

FIG. 4 is an exemplary timing diagram of the time-to-digital converter of FIG. 2 according to some embodiments;

FIG. 5 is an exemplary block diagram illustrating how a duty cycle index generator of the duty cycle adjustment system of FIG. 1 calculates a duty cycle of an input signal, in accordance with some embodiments;

FIG. 6 is an input phase assignment generator, a slave delay line and a duty cycle generator of the duty cycle adjustment system of FIG. 1 in accordance with some embodiments;

FIG. 7 is an exemplary timing diagram illustrating duty cycle adjustment according to some embodiments;

FIG. 8 is another exemplary timing diagram illustrating duty cycle adjustment according to some embodiments;

FIGS. 9 and 10 are exemplary graphs illustrating the advantages of the duty cycle adjustment system of FIG. 1 compared to a conventional duty cycle adjustment mechanism, in accordance with some embodiments;

fig. 11 is an exemplary flowchart outlining an operation for adjusting a duty cycle of an input signal using the duty cycle adjustment system of fig. 1 in accordance with some embodiments.

[ notation ] to show

100 duty cycle adjustment system

105 input signal

110 time-to-digital converter

115 sampling clock signal

120 sampling signal

125 time digital code

130 duty cycle index generator

135 duty cycle index

140 input phase assignment generator

145: output

150 slave delay line

155: output

160 duty cycle generator

165 delaying the select signal

170: output

175 output

205 master delay line

210A-210N sampling unit

215A-215N buffer

220 logic AND gate

225A-225N time digital code

230 sample signal

235 time sequence diagram array

240 timing diagram

245A to 245J timing diagram

250 rising edge

255A-255J time digital code

260 signal

265 duration

270 duration

275 duration

280 first multiplexer

285 second multiplexer

290 reverse input signal

295 inverter

300. 305 select input signal

Set Reset (SR) flip-flop 330

335 timing diagram

340 pulse width

345 time period

350 pulse width

355 timing diagram

360 pulse width

365 time period

370 pulse width

375 diagram

380: Y axis

385X axis

390 first figure

395 second figure

400 arrow head

405 arrow head

410 graph of

415Y-axis

420X axis

425 first graph

430 second graph

435 arrow head

440 Process

445 to 470 operations

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Accurate pulse generation can be critical to proper device operation. For example, for life reliability testing at production level high temperature operation, duty cycle distortion due to device degradation can become a significant problem, especially in clock signals, which will reduce speed and eventually cause device failure. To avoid duty cycle distortion, duty cycle adjustments may be performed. Conventionally, duty cycle adjustment is performed using charge pumping, where the duty cycle of an input signal (e.g., a clock signal) can be adjusted using a feedback control voltage and a ring oscillator. Charge pumps have a narrow frequency range, require large chip area, have increased power consumption and noise generation, and suffer from poor scaling for process migration. Another conventional mechanism for adjusting duty cycle distortion is to use a delay line. However, duty cycle adjustment is limited by the delay line based on the number of delay stages in the delay line. To support a wide range of duty cycle adjustments, delay lines require a large number of delay stages, which increases overall chip area and increases power consumption and noise generation. Accordingly, conventional mechanisms for adjusting the duty cycle of an input signal (e.g., a clock signal) have various disadvantages.

The present disclosure provides duty cycle adjustment systems with a wide range of duty cycle adjustments using a smaller number of delay stages, lower power consumption, improved frequency, reduced chip area, lower noise, and improved technology scaling due to digital design.

Referring to fig. 1, an exemplary block diagram of a duty cycle adjustment system 100 is shown, in accordance with some embodiments of the present disclosure. The duty cycle adjustment system 100 can be used to adjust the duty cycle of a signal. As used herein, a "signal" can be any time-varying voltage, current, or electromagnetic wave that carries information. In some embodiments, the signal may be defined in terms of one or more signal properties such as time period, duty cycle, pulse width, and the like. The time period of the signal may be the amount of time required for the signal to complete a full cycle. For example, in some embodiments, the time period of the signal may be the amount of time between a rising edge of the signal and the next rising edge of the signal. In some embodiments, the time period may be the amount of time between a falling edge of the signal and the next falling edge of the signal. In some embodiments, the pulse width of the signal may be the amount of time between a rising edge and the next falling edge of the signal. In other embodiments, the pulse width of the signal may be the amount of time between the falling edge and the next rising edge of the signal. Further, in some embodiments, the duty cycle of a signal may define a "start-up" time for the signal. In some embodiments, the duty cycle may be calculated by dividing the pulse width by the time period. In some embodiments, the duty cycle may be measured in percent.

The duty cycle adjustment system 100 can be used to adjust the duty cycle or pulse width of the input signal 105. Although the input signal 105 is shown as a clock signal, in other embodiments, the duty cycle adjustment system 100 can be used to adjust the duty cycle of a non-clock signal. In some embodiments, the desired output pulse width or duty cycle of the input signal 105 may be predetermined and programmed within the duty cycle adjustment system 100. In other embodiments, the desired output pulse width or duty cycle of the input signal 105 may be controllable and may be adjusted in real-time (on-the-fly) using the duty cycle adjustment system 100. The duty cycle adjustment system 100 may include a time-to-digital converter 110 to digitally calculate/measure the time period of the input signal 105 and convert the calculated/measured time period into a digital (e.g., binary) output for a wide range of pulse width generation and duty cycle correction. In particular, the time-to-digital converter 110 may be configured to determine a time period of the input signal 105 using the sampling clock signal 115 and another sampling signal 120 to generate a time-to-digital code (TDC) 125. The time-to-digital converter 110 is discussed in more detail in fig. 2-4.

The time-to-digital code 125 is input into a duty cycle index generator 130 that generates a duty cycle index 135 based on the calculated duty cycle of the input signal 105. The duty cycle index generator 130 calculates the duty cycle of the input signal 105 based on the time-to-digital code 125. The duty cycle index generator 130 is discussed in more detail below in FIG. 5. In some embodiments, the duty cycle index 135 may be a binary value that is input into the input phase assignment generator 140. The input phase assignment generator 140 may assign an input clock phase to the input signal 105 based on the duty cycle index 135 and transmit the output 145 to the slave delay line 150 and the output 155 to the duty cycle generator 160. The slave Delay line 150 may Delay the output 145 by a predetermined number of Delay stages determined by a Delay selection signal (Delay _ Sel)165 to transmit the output 170 to the duty cycle generator 160. The duty cycle generator 160 receives the output 155 from the input phase assignment generator 140 and the output 170 from the slave delay line 150 to adjust the duty cycle of the input signal 105. The output 175 from the duty cycle generator 160 corresponds to the input signal 105 but has an adjusted duty cycle. The input phase assignment generator 140, slave delay line 150, and duty cycle generator 160 are discussed in more detail below in fig. 6-8.

Turning to fig. 2, additional details of the time-to-digital converter 110 are shown, according to some embodiments of the present disclosure. The time-to-digital converter 110 can be used to accurately measure the time period and duty cycle of the input signal 105. Although a time-to-digital converter 110 is used herein, in other embodiments, other circuits or components that allow the time period/duty cycle of the input signal 105 to be measured may be used. Time-to-digital converter 110 may be implemented in software, hardware, firmware, or a combination thereof.

The time-to-digital converter 110 includes a master delay line 205 and a plurality of sampling units 210A-210N. Additional details illustrating how the master delay line 205 is connected to the plurality of sampling units 210A-210N are shown in fig. 3. Referring to fig. 2 and 3 together, the master delay line 205 includes a plurality of buffers 215A-215N, each of which forms a delay stage. The number of the plurality of buffers 215A-215N may vary from one embodiment to another depending on the number of delay stages desired. In some embodiments, each buffer of the plurality of buffers 215A-215N may be associated with one sampling unit from the plurality of sampling units 210A-210N. Thus, in some embodiments, the number of buffers in the plurality of buffers 215A-215N may be the same as the number of sampling units in the plurality of sampling units 210A-210N. In other embodiments, the number of buffers in the plurality of buffers 215A-215N may be different from the number of sampling units in the plurality of sampling units 210A-210N.

In operation, a first buffer (e.g., buffer 215A) of the plurality of buffers 215A-215N receives the input signal 105 as an input into the buffer. The output from buffer 215A is delayed by the propagation time required for input signal 105 to pass through the buffer. Thus, each of the plurality of buffers 215A-215N may have a predefined delay time. In some embodiments, each of the plurality of buffers 215A-215N may have the same designed delay time. In other embodiments, one or more of the plurality of buffers 215A-215N may have varying specified delay times. Thus, the output from buffer 215A is delayed by a delay amount (e.g., a delay time associated with buffer 215A). Further, the output from the buffer 215A is input into the buffer 215B. Buffer 215B further delays input signal 105 and sends an output as an input into buffer 215C, and so on. Thus, each of the plurality of buffers 215B-215N receives as input the output from the buffer of the previous delay stage and further delays the input signal.

In addition, an output from each of the plurality of buffers 215A to 215N is input into a corresponding one of the plurality of sampling units 210A to 210B. Each of the plurality of sampling units 210A-210N senses an output from a respective one of the plurality of buffers 215A-215N based on a sampling frequency of the sampling clock signal 115. For example, each of the plurality of sampling units 210A-210N may sample the output of a corresponding buffer of the plurality of buffers 215A-215N on a rising edge (or falling edge) of the sampling clock signal 115. In some embodiments, the sampling clock signal 115 AND the sampling signal 120 may be input to the logic AND gate 220 together to generate another sampling signal 230, AND the sampling signal 230 may be used to sample the plurality of buffers 215A-215N. In some embodiments, each of the plurality of sampling units 210A-210N may be a D flip-flop. In other embodiments, one or more of the plurality of sampling units 210A-210N may be sense amplifier units or another type of electronic circuit for sensing and storing state information.

The output from each of the plurality of sampling units 210A-210N is a time-to-digital code. For example, sampling unit 210A generates a time-to-digital code 225A, sampling unit 210B generates a time-to-digital code 225B, and so on. Thus, for N number of the plurality of sampling units 210A-210N, N time-to-digital codes 225A-225N can be generated by the time-to-digital converter 110. Because each of the N time-to-digital codes 225A-225N is based on an output from one of the plurality of buffers 215A-215N, each of the N time-to-digital codes represents a delay stage. The combination of N time-to-digital codes is denoted herein as time-to-digital code 125. Examples of time-to-digital codes 225A-225N generated by time-to-digital converter 110 are illustrated in FIG. 4. Thus, referring to fig. 4 in conjunction with fig. 2 and 3, a timing diagram array 235 is shown, in accordance with some embodiments of the present disclosure. Timing diagram array 235 shows a timing diagram 240 of sampling clock signal 115 and timing diagrams 245A-245J of some of the plurality of sampling units 210A-210N. For example, timing diagram 245A may correspond to the timing diagram generated by sampling unit 210A, timing diagram 245B may correspond to the timing diagram generated by sampling unit 210B, and so on.

In some embodiments and as shown in FIG. 4, the rising edge 250 of the sampling clock signal 115 may be used as a trigger signal for sampling the state of each delay stage of the master delay line 205 and capturing those states using the plurality of sampling cells 210A-210N. Thus, at the rising edge 250, the states of the plurality of sampling units 210A-210N can be extracted from the timing diagrams 245A-245J, and the extracted states can be input as the time-to-digital codes 255A-255J. For example, at the rising edge 250 of the sampling clock signal 115, the timing diagram 245A of the sampling unit 210A is at a low logic level ("0"). Thus, the time-digital code 255A extracted from the sampling unit 210A at the rising edge 250 is "0". Similarly, at rising edge 250, each of timing diagrams 245B-245E and 245J are at a high logic level ("1"). Thus, each of the time-to-digital codes 255B to 255E and 255J is "1". Similarly, at rising edge 250, each of timing diagrams 245F-245I is at a low level. Thus, each of the time-to-digital codes 255F to 255I is "0". The time-to-digital codes 255A-255J may be output from the time-to-digital converter 110 and input into the duty cycle index generator 130. The time-to-digital codes 255A-255J may represent a signal 260, additional details of which are discussed below in fig. 5.

Turning to FIG. 5, additional details of the duty cycle index generator 130 are shown, according to some embodiments of the present disclosure. The duty cycle index generator 130 receives the time-to-digital codes 225A-225N and generates the duty cycle index from these time-to-digital codes. The duty cycle index represents the calculated duty cycle of the input signal 105. To determine the calculated duty cycle, the duty cycle index generator 130 identifies the falling and rising edges of the input signal 105 from the time-digital codes 225A-225N. To identify falling and rising edges, the duty cycle index generator 130 may count the number of consecutive "0" values and consecutive "1" values in the time-to-digital codes 225A-225N, and count the number of adjacent "0" and "1" values.

In some embodiments, a "1" value of the time-to-digital code 225A-225N may indicate that the input signal is at a logic high level, and a "0" may indicate that the input signal is at a logic low level. Adjacent "0" and "1" values may indicate transitions between rising and falling edges. For example, in some embodiments, a transition from a "0" value to a "1" value may indicate a rising edge, while a transition from a "1" value to a "0" value may indicate a falling edge. For example, in fig. 5, the signal 260 includes a first rising edge tr1 and a second rising edge tr 2. The signal 260 also includes a first falling edge tf1 and a second falling edge tf 2. As shown in fig. 4, the duration between the rising edge tr1 and the falling edge tf1 may be represented by time-to-digital codes 255B-255E having a value of "1", the duration between the falling edge tf1 and the rising edge tr2 may be represented by time-to-digital codes 255F-255I, the rising edge tr1 may be represented by a transition from a "0" value of the time-to-digital code 255A to a "1" value of the time-to-digital code 255B, the falling edge tf1 may be represented by a transition from a "1" value of the time-to-digital code 255E to a "0" value of the time-to-digital code 255F, and so on. Thus, by identifying successive "0" and "1" values, and by identifying transitions between "0" and "1" values, duty cycle index generator 130 may calculate a duty cycle.

In particular, the duty cycle index generator 130 may first calculate the number of delay stages S for a repeating time period using the following equation_period：

S_period＝S[tr2]–S[tr1](first type)

Or

S_period＝S[tf1]–S[tf2](second formula)

Thus, the duty cycle index generator 130 determines the time period of the signal 260 by counting the number of delay stages between two consecutive rising edges or two consecutive falling edges. For example, in fig. 5, duration 265 may be between two consecutive rising edges and duration 270 may be between two consecutive falling edges. S [ tr1]、S[tr2]、S[tf1]And S [ tf2]The number of delay stages of the time-to-digital code 255A-255N may be represented. In addition, the duty cycle index generator 130 may useThe number of delay stages S of the high pulse of signal 260 is calculated by the following equation_{high_pulse}：

S_{high_pulse}＝S[tf1]–S[tr1](third formula)

Thus, S_{high_pulse}Represents the pulse width of the signal 260 and may be determined by counting the number of delay stages between the falling and rising edges of the signal. For example, in fig. 5, the pulse width of signal 260 may be represented by duration 275. The duty cycle of signal 260 may then be calculated using the following equation:

Duty Cycle＝S_{high_pulse}/S_period

in some embodiments, the above duty cycle calculations may be converted to a percentage form. Further, based on the calculated duty cycle, the duty cycle index may be generated using the following table:

duty cycle index of 00	The working period is 50%
		Duty cycle index of 01	Duty cycle<50％
Duty cycle index of 10	Duty cycle>50％
		Duty cycle index of 11	Retention

Therefore, if the calculated duty cycle is 50%, the duty cycle index 135 output from the duty cycle index generator 130 is 00. If the calculated duty cycle is less than 50%, the duty cycle index 135 output from the duty cycle index generator 130 is 01, and if the calculated duty cycle is greater than 50%, the duty cycle index having a value of 10 is output from the duty cycle index calculation block. In some embodiments, the duty cycle index 135 having a value of 11 may not be used for pulse width adjustment and may be reserved for other functions. Thus, in some embodiments, the duty cycle index 135 is a binary value determined based on the time-to-digital codes 225A-225N. The duty cycle index 135 may be input into an input phase assignment generator 140, which is discussed in more detail below in fig. 6. The duty cycle index generator 130 may be formed of software, hardware, firmware, or a combination thereof.

Referring to fig. 6, the duty cycle index 135 is used by the input phase assignment generator 140 to tune the duty cycle of the input signal 105. In some embodiments, input phase assignment generator 140 includes a first multiplexer 280 and a second multiplexer 285, each of which receives two inputs and generates one output. For example, in some embodiments, each of first multiplexer 280 and second multiplexer 285 receive input signal 105 as a first input and inverted input signal 290 as a second input. In some embodiments, the input signal 105 may be inverted using an inverter 295. In other embodiments, other mechanisms to invert the input signal 105 may be used to obtain the inverted input signal 290. In addition, each of first multiplexer 280 and second multiplexer 285 receives a select input signal 300, 305, respectively, based on duty cycle index 135. Each of first multiplexer 280 and second multiplexer 285 may be formed in software, hardware, firmware, or a combination thereof.

When the duty cycle index 135 is 01, indicating a calculated duty cycle less than 50%, in some embodiments the select input signal 300 of the first multiplexer 280 is set to 1 (e.g., the right bit of the duty cycle index 135) and the select input signal 305 of the second multiplexer 285 is set to 0 (e.g., the left bit of the duty cycle index 135). Similarly, when the duty cycle index 135 is 10, indicating a calculated duty cycle greater than 50%, the select input signal 300 of the first multiplexer 280 is set to 0 (e.g., the right bit of the duty cycle index 135) and the select input signal 305 of the second multiplexer 285 is set to 1 (e.g., the left bit of the duty cycle index 135). When set to 1, the first multiplexer 280 selects the inverted input signal 290 as output 145, and when set to 0, the first multiplexer selects the input signal 105 as output. Similarly, the second multiplexer 285 selects the input signal 105 as the output 155 when set to 0 and selects the inverted input signal 290 as the output when set to 1. Thus, input phase assignment generator 140 receives input signal 105 and duty cycle index 135 as inputs and generates outputs 145 and 155.

The output 145 from the first multiplexer 280 is input into the slave delay line 150. The output 155 from the second multiplexer 285 is input to the duty cycle generator 160. In some embodiments, the slave delay line 150 may be similar to the master delay line 205. Thus, the slave delay line 150 may include a plurality of buffers, each providing a specified delay time. The output from the buffer may constitute a delay stage. Thus, the slave delay line 150 includes a plurality of delay stages, and each delay stage includes a buffer. A first buffer in the slave delay line 150 receives the output 145 from the first multiplexer 280. The output from the first buffer is input into a second buffer of the slave delay line 150, the output from the second buffer is input into a third buffer of the slave delay line 150, and so on. Thus, similar to the plurality of buffers 215A-215N of the master delay line 205, the plurality of buffers of the slave delay line 150 are connected in series.

The number of delay stages and the number of buffers in the corresponding slave delay line 150 may vary from one embodiment to another. Further, in some embodiments, the number of delay stages in the slave delay line 150 may be the same as the number of delay stages in the master delay line 205. In other embodiments, the number of delay stages in the slave delay line 150 may be different than the number of delay stages in the master delay line 205. Further, the output from the buffer in each delay stage of the slave delay line 150 may be tapped to achieve different pulse widths of the output 145. In particular, the delay introduced into the output 145 during each delay stage of the slave delay line 150 may be known. Thus, each delay stage can vary the duty cycle of output 145 by a known value, and the number of delay stages required to achieve a desired pulse width can be determined. Thus, based on the number of delay stages needed to obtain the desired pulse width of the input signal 105, the output 145 from the slave delay line 150 may be tapped after the output 145 passes through those number of delay stages. The number of delay stages through which output 145 passes before being tapped may be determined based on delay select signal 165. The tapped output is thus transmitted as output 170 from slave delay line 150.

The output 170 is input to the duty cycle generator 160. In some embodiments, the duty cycle generator 160 includes a set-reset ("SR") flip-flop 330. In some embodiments, SR flip-flop 330 may comprise a cross-coupled NOR gate. In other embodiments, SR flip-flop 330 may comprise cross-coupled NAND gates or other types of logic gates. In some embodiments, other types of flip-flops or other electronic components that achieve the same function as SR flip-flop 330 may be used. In some embodiments, the output 170 from the slave delay line 150 may be provided to a reset input of an SR flip-flop 330, and the output 155 from the second multiplexer 285 may be provided to a set input of the SR flip-flop. Because output 170 is selected from the delay stages of slave delay line 150 to achieve the desired pulse width, output 175 from SR flip-flop 330 has the desired pulse width of input signal 105, as shown in fig. 7 and 8 below.

Referring to fig. 7, an exemplary timing diagram 335 is shown, in accordance with some embodiments of the present disclosure. Timing diagram 335 corresponds to output 175 achieved when the duty cycle index is 01 indicating that the calculated duty cycle of input signal 105 will be less than 50%. Timing diagram 335 includes a timing diagram of output 155, output 155 being the input signal 105 selected from second multiplexer 285 and input into SR flip-flop 330. Timing diagram 335 also includes a timing diagram of output 170, output 170 being an inverted input signal 290 selected as output 145 from first multiplexer 280 and passed through slave delay line 150 before being input into SR flip-flop 330. The output from SR flip-flop 330 is represented by a timing diagram of output 175.

The duty cycle of the input signal 105 may be adjusted between a minimum duty cycle and a maximum duty cycle, as shown in output 175. The minimum duty cycle may be based on the output 145 failing the slave delay line. In other words, the output 145 from the first multiplexer 280 may be directly input into the SR flip-flop 330, similar to the output 155. Thus, the minimum duty cycle may be based on the pulse width 340 and may be given by the following equation:

Duty Cycle_min＝T_{delay_min}/T_period

in the above formula, T_{delay_mi}Is the pulse width 340, and T_periodIs time period 345. Similarly, the maximum duty cycle of output 175 may be based on the output tapped from the last delay stage of subordinate delay line 150. In other words, the maximum duty cycle may be based on the maximum delay that may be achieved by the slave delay line 150. Thus, the maximum duty cycle can be given by the following equation:

Duty Cycle_max＝T_{high_pulse}+T_{delay_max}/T_period

in the above formula, T_{high_pulse}+T_{delay_max}Is the pulse width 350, and T_periodIs time period 345. Thus, depending on the degree to which output 145 is delayed in slave delay line 150, output 175 may be adjusted to any duty cycle between a minimum duty cycle in which output 145 is not delayed at all and a maximum duty cycle in which output 145 is delayed a maximum amount in slave delay line 150. Thus, by using the duty cycle index 135, the input phase assignment generator 140, the slave delay line 150, and the duty cycle generator 160, the duty cycle of the input signal 105 may be adjusted between a minimum duty cycle and a maximum duty cycle, as discussed above.

Turning to fig. 8, an exemplary timing diagram 355 is illustrated, in accordance with some embodiments of the present disclosure. Timing diagram 355 corresponds to output 175 achieved when the duty cycle index is 10 indicating that the calculated duty cycle of input signal 105 will be greater than 50%. Timing diagram 355 includes a timing diagram of output 155, which is the inverted input signal 290 selected from second multiplexer 285 and input into SR flip-flop 330. Timing diagram 355 also includes a timing diagram of output 170, output 170 being the input signal 105 selected as output 145 from first multiplexer 280 and through slave delay line 150 before being input into SR flip-flop 330. The output from SR flip-flop 330 is represented by a timing diagram of output 175, with output 175 reflecting input signal 105 having an adjusted duty cycle.

The duty cycle of output 175 may be adjusted between a minimum duty cycle and a maximum duty cycle. The minimum duty cycle may be based on the output 145 failing the slave delay line. In other words, the output 145 from the first multiplexer 280 may be directly input into the SR flip-flop 330, similar to the output 155. Thus, the minimum duty cycle may be based on the pulse width 360 and may be given by the following equation:

Duty Cycle_min＝T_{delay_min}/T_period

in the above formula, T_{delay_mi}Is the pulse width 360, and T_periodTime period 365. Similarly, the maximum duty cycle of output 175 may be based on the output tapped from the last delay stage of subordinate delay line 150. In other words, the maximum duty cycle may be based on the maximum delay that may be achieved by the slave delay line 150. Thus, the maximum duty cycle can be given by the following equation:

Duty Cycle_max＝T_{low_pulse}+T_{delay_max}/T_period

in the above formula, T_{low_pulse}+T_{delay_max}Is the pulse width 370, and T_periodTime period 365. Thus, depending on the degree to which output 145 is delayed in slave delay line 150, output 175 may be adjusted to any duty cycle between a minimum duty cycle in which output 145 is not delayed at all and a maximum duty cycle in which output 145 is delayed a maximum amount in slave delay line 150. Thus, by using the duty cycle index 135, the input phase assignment generator 140, the slave delay line 150, and the duty cycle generator 160, the input may be adjusted between a minimum duty cycle and a maximum duty cycleThe duty cycle of the signal 105, as discussed above.

Turning to fig. 9, an exemplary graph 375 is illustrated, in accordance with some embodiments of the present disclosure. Graph 375 plots the duty cycle on the Y-axis 380 versus the frequency on the X-axis 385. Graph 375 shows a first graph 390 of duty cycle adjustments made in accordance with the present disclosure and a second graph 395 of duty cycle adjustments made in accordance with the prior art. Graph 375 shows that for the same operating frequency (e.g., at 1.6 GHz), the duty cycle of first graph 390 is greater than the duty cycle of second graph 395 (e.g., the duty cycle rises from about 50% of the second graph to about 75% of the first graph), as shown by arrow 400. Additionally, for the same duty cycle (e.g., 50%), the first graph 390 demonstrates that the lower bound of the operating frequency range may be expanded to about 57% compared to the frequency of the second graph 395 (e.g., the frequency is reduced from about 1.5GHz of the second graph to about 0.6GHz of the first graph), as shown by arrow 405.

Turning to fig. 10, an exemplary graph 410 is illustrated, in accordance with some embodiments of the present disclosure. Graph 410 plots power consumption on Y-axis 415 versus frequency on X-axis 420. Chart 410 shows a first graph 425 of duty cycle adjustments made in accordance with the present disclosure and a second graph 430 of duty cycle adjustments made in accordance with conventional techniques. Graph 410 shows that for the same operating frequency, the power consumption of first graph 425 is reduced by about 50% compared to the power consumption of second graph 430, as shown by arrow 435.

Thus, the present disclosure enables a wide range of operation with low power consumption compared to conventional design approaches. For example, in some embodiments, the present disclosure may maintain the same or substantially similar minimum delay (Tdelay _ min) as the conventional scheme, reduce the maximum delay (Tdelay _ max) of the conventional scheme (e.g., by at least one-half in some embodiments), maintain the same or similar frequencies (e.g., minimum and maximum frequencies) and frequency ranges (e.g., frequency _ range) as the conventional scheme, and reduce power consumption by at least one-half compared to the conventional scheme for the same clock duty cycle.

Referring to fig. 11, an exemplary flowchart outlining the operation of process 440 is shown in accordance with some embodiments of the present disclosure. Process 440 may be used to adjust a duty cycle of an input signal (e.g., input signal 105). Accordingly, at operation 445, the input signal 105 whose duty cycle is to be adjusted is input into the duty cycle adjustment system 100. At operation 450, the input signal 105 is received by the time-to-digital converter 110, and the time-to-digital converter 110 converts the time domain information of the input signal into the digital domain. Specifically, the time-to-digital converter 110 is configured to quantize the time interval of the input signal 105 based on the sampling clock signal 115 to calculate the time period of the input signal, and output the time-to-digital codes 225A-225N. At operation 455, the time-to-digital codes 225A-225N may be used to calculate the duty cycle index 135.

As discussed above, to calculate the duty cycle index, the duty cycle index generator 130 first calculates the duty cycle of the input signal 105 using the time-to-digital codes 225A-225N received from operation 450. To calculate the duty cycle of the input signal 105, the duty cycle index generator 130 counts the number of consecutive "1" and "0" values indicating a high logic level or a low logic level, respectively, and the adjacent "1" and "0" values indicating a rising edge or a falling edge. Based on the calculated duty cycle, the duty cycle index generator 130 assigns a binary duty cycle index to the input signal 105. The duty cycle index 135 is input into the input phase assignment generator 140 at operation 460 to assign an input pulse phase to the input signal 105 for duty cycle adjustment. In particular, the input phase assignment generator 140 includes a first multiplexer 280 and a second multiplexer 285 that are controlled to transmit the outputs 145 and 155 based on the duty cycle index 135.

At operation 465, the output 145 from the input phase assignment generator 140 is input into the slave delay line 150 to delay the output by a predetermined number of stages. The output 170 from the slave delay line 150 is input into an SR flip-flop 330. Output 155 is input directly into SR flip-flop 330. SR flip-flop 330 generates output 175 based on outputs 155 and 170 having the adjusted duty cycle. The process 440 ends at operation 470.

Accordingly, the present disclosure provides a digital-based mechanism to adjust the duty cycle of an input signal over a wide range. The duty cycle adjustment mechanism of the present disclosure achieves a wider adjustment range compared to existing mechanisms with lower power consumption (e.g., high power efficiency), reduced chip size, and low cost.

According to aspects of the present disclosure, a duty cycle adjustment system is disclosed. The duty cycle adjustment system includes: a time-to-digital converter for generating a plurality of time-to-digital codes from an input signal; a duty cycle index generator to calculate a duty cycle of the input signal based on a plurality of time-to-digital codes and to assign a duty cycle index based on the calculated duty cycle; and an input phase assignment generator to generate a first output and a second output based on the duty cycle index. The duty cycle adjustment system also includes: a first delay line for delaying the first output to generate a third output; and a duty cycle generator to adjust a duty cycle of the input signal based on the third output and the second output. In some embodiments, the time-to-digital converter includes a second delay line having a plurality of delay stages, and wherein each of the delay stages generates one of the time-to-digital codes. In some embodiments, each of the delay stages includes a sampling unit to sample a fourth output from the associated one of the delay stages based on a sampling clock signal to generate the time-to-digital code. In some embodiments, the duty cycle index is a binary code. In some embodiments, the duty cycle index generator is configured to count a number of time-digital codes having a plurality of consecutive 1 values and a plurality of consecutive 0 values, and count a number of time-digital codes having adjacent 0 values and 1 values to calculate the duty cycle of the input signal. In some embodiments, if the calculated duty cycle is equal to a first predetermined duty cycle value, the duty cycle index is a first predetermined index value. In some embodiments, if the calculated duty cycle is less than a second predetermined duty cycle value, the duty cycle index is a second predetermined index value. In some embodiments, if the calculated duty cycle is greater than a third predetermined duty cycle value, the duty cycle index is a third predetermined index value. In some embodiments, the input phase assignment generator includes a first multiplexer and a second multiplexer, wherein each of the first multiplexer and the second multiplexer is configured to receive the input signal as a first input and an inverted input signal as a second input, wherein the first multiplexer is configured to receive a first portion of the duty cycle index to select the first input or the second input as the first output, and the second multiplexer is configured to receive a second portion of the duty cycle index to select the first input or the second input as the second output. In some embodiments, the first output is an inverted input signal and the second output is an input signal when the duty cycle index indicates that the duty cycle being calculated is less than 50%. In some embodiments, the first output is an input signal and the second output is an inverted input signal when the duty cycle index indicates that the duty cycle being calculated is greater than 50%. In some embodiments, the duty cycle generator adjusts the duty cycle of the input signal based on a predetermined number of the plurality of delay stages through which the first output passes in the first delay line. In some embodiments, the duty cycle generator includes a set reset flip-flop.

According to some other aspects of the present disclosure, a method is disclosed. The method includes generating a plurality of time-to-digital codes from an input signal by a time-to-digital converter of a duty cycle adjustment system, counting a number of the plurality of time-to-digital codes having a consecutive 1 value, a consecutive 0 value, and adjacent 0 and 1 values by a duty cycle index generator of the duty cycle adjustment system to calculate a duty cycle and assign a duty cycle index based on the calculated duty cycle and generate a first output and a second output based on the duty cycle index by an input phase assignment generator. The method also includes adjusting, by a duty cycle generator of the duty cycle adjustment system, a duty cycle of the input signal based on the first output and the second output. In some embodiments, if the calculated duty cycle is equal to a predetermined duty cycle value, the duty cycle index is a first predetermined index value; if the calculated work period is less than the preset work period value, the work period index is a second preset index value; and if the calculated work period is greater than the predetermined work period value, the work period index is a third predetermined index value. In some embodiments, the input phase assignment generator comprises a first multiplexer and a second multiplexer, and wherein the method further comprises: inputting the input signal as a first input and an inverted input signal as a second input into each of the first multiplexer and the second multiplexer; inputting a first portion of the duty cycle index to a first multiplexer for selecting either the first input or the second input as a first output; and inputting a second portion of the duty cycle index to the second multiplexer for selecting either the first input or the second input as the second output. In some embodiments, the method further comprises: selecting a first output as the inverted input signal and a second output as the input signal at a duty cycle index having a value indicating that the duty cycle being calculated is less than 50%; and selecting the first output as the input signal and the second output as the inverted input signal at a duty cycle index having a value indicating that the duty cycle being calculated is greater than 50%.

According to still other aspects of the present disclosure, a circuit is disclosed. The circuit includes: a first circuit to generate a duty cycle index from an input signal; a first multiplexer for receiving an input signal as a first input, an inverted input signal as a second input, and a first bit of a duty cycle index as a select input to generate a first output. The first output is an inverted input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is less than the predetermined duty cycle value, and the first output is an input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is greater than the predetermined duty cycle value. The circuit also includes a second multiplexer for receiving the input signal as a first input, the inverted input signal as a second input, and the second bit of the duty cycle index as a select input to generate a second output. The second output is the input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is less than the predetermined duty cycle value, and the second output is the inverted input signal if the duty cycle index indicates that the calculated duty cycle of the input signal is greater than the predetermined duty cycle value. The circuit additionally includes a second circuit to adjust a duty cycle of the input signal based on the first output and the second output. In some embodiments, the circuit further includes a master delay line and a slave delay line. The master delay line is used for receiving an input signal and generating a plurality of time digital codes, wherein the work cycle index is generated from the time digital codes. The slave delay line is used for receiving the first output and generating a third output, wherein the third output and the second output are input into the second circuit together. In some embodiments, the second circuit is a set reset flip-flop configured to receive the third output from the slave delay line and the second output from the second multiplexer to adjust the duty cycle of the input signal.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.