阅读说明：本技术 Fpga组件 (FPGA component ) 是由 何允灵 朱怀宇 沙钰杰 王佳承 康治安 姚美荣 朱志新 朱亚军 刘达霖 唐吉亮 于 2018-09-29 设计创作，主要内容包括：本发明公开了一种FPGA组件,所述FPGA组件包括：固态硬盘、DDR和控制单元；所述固态硬盘用于存储界面数据包；所述控制单元用于从所述固态硬盘读取所述界面数据包并写入所述DDR；所述控制单元还用于从所述DDR读取所述界面数据包并组成所述人机界面的显示帧。本发明的FPGA组件可用于实现界面显示,无需任何CPU、操作系统和软件支持,避免了黑客和病毒的入侵,安全性大大提高,且还具有电路简洁、无闲置电路、功耗低等优点。(The invention discloses a kind of FPGA component, the FPGA component includes: solid state hard disk, DDR and control unit；The solid state hard disk is for storing interface data packet；Described control unit is used to read the interface data packet from the solid state hard disk and the DDR is written；Described control unit is also used to read the display frame of man-machine interface described in the interface data packet and composition from the DDR.FPGA component of the invention can be used for realizing interface display, be not necessarily to any CPU, operating system and software support, avoid the invasion of hacker and virus, and safety greatly improves, and also have many advantages, such as simple circuit, without idle circuit, low in energy consumption.)

1. a kind of FPGA component, which is characterized in that the FPGA component includes: solid state hard disk, DDR and control unit；

The solid state hard disk is for storing interface data packet；

Described control unit is used to read the interface data packet from the solid state hard disk and the DDR is written；

Described control unit is also used to read the display frame of the interface data packet and composition man-machine interface from the DDR.

2. FPGA component as described in claim 1, which is characterized in that the solid state hard disk is also used to storage configuration data packet；

The DDR is also used to store the text data of peripheral apparatus transmission；

Described control unit is also used to according to the interface data packet and in conjunction with the text data and/or the configuration data packet Form the display frame of the man-machine interface.

3. FPGA component as claimed in claim 2, which is characterized in that described control unit is also used to judging the textual data When according to change, display frame is reformulated according to the text data after change.

4. FPGA component as described in claim 1, which is characterized in that the DDR is also used to store the behaviour of external equipment transmission It instructs；

Described control unit is also used to update the display frame according to the operational order.

5. FPGA component as claimed in claim 4, which is characterized in that the interface data packet includes: the man-machine interface The pixel data of background data and control；

The pixel data includes at least one of following parameter: the visit of control type, control size, control location, control Ask link；

The access link characterizes the corresponding relationship of the control and the interface data packet.

6. FPGA component as claimed in claim 5, which is characterized in that the interface data packet further include: the icon number of mouse According to；

When the operational order is write command, described control unit is specifically used for basis and writes data reformulation display frame with more The new display frame；The write command includes write data；

When the operational order is jump instruction, described control unit is specifically used for being linked according to the access of target widget from institute It states solid state hard disk part and the DDR is written into corresponding interface data packet, and reformulate display frame to update the display frame；Institute Stating jump instruction includes the target widget；

When the operational order is the change directive of the icon data, described control unit is specifically used for according to location information The display frame is modified to update the display frame；The change directive includes the location information.

7. FPGA component as claimed in claim 2, which is characterized in that the FPGA component further include: group depacketization logic unit；

Described group of depacketization logic unit judges the boundary for unpacking to the received interface data packet of the FPGA component Whether the number of dropped packets of face data packet and/or wrong packet number are in respective threshold range, and when being judged as YES, by the boundary after unpacking Face data packet re-groups package and is sent to the solid state hard disk.

8. FPGA component as claimed in claim 7, which is characterized in that described group of depacketization logic unit is also used to be judged as NO When, it is sent out reissue commands.

9. the FPGA component as described in any one of claim 1-8, which is characterized in that the quantity of described control unit is more A, multiple control units are connected by SerDes interface communication；

And/or the FPGA component further includes power supply unit, the power supply unit successively gives the solid state hard disk, the control Unit and DDR power supply.

10. FPGA component as claimed in claim 9, which is characterized in that the FPGA component further includes metal shell；

The solid state hard disk, the DDR, described control unit and the power supply unit are set in the metal shell.

Technical field

The present invention relates to electronic technology field, in particular to the FPGA (programmable gate array) of a kind of achievable interface display Component.

Background technique

Currently, generalling use CPU processor to realize the design of terminal display system, in addition to main place in whole system design It manages outside device chip, it is also necessary to a plurality of bridge chips are used, to realize data-interface and exchange between various buses.Due to this System architecture is not the special design of display processing, and therefore, many resources therein use less than, and there are many idle electricity Road.And thus bring another problem is that, corresponding software systems, it is still necessary to develop this part leave unused circuit drive software, To guarantee the stable operation of whole system, this results in the power consumption of whole system and volume to accordingly increase.Generally speaking, it uses This design method increases many extra workloads.

In addition, being realized in the design of terminal display system using CPU processor, man-machine interface generally passes through operating system The system realized with application software etc., however have software to participate in just has multi-process, multitask to the shared and competing of system resource It strives, uncertainty will necessarily be brought, and software is easy the invasion by hacker and virus, for nuclear power station security level instrument control system System, bank etc. focus on safe application scenarios, and safety is just difficult to be protected.

Summary of the invention

The technical problem to be solved by the present invention is to realize that terminal is shown using CPU processor in the prior art to overcome In the design of system, on the one hand there is more idle circuit, cause power consumption larger, is on the other hand easy by hacker and virus Invasion, the poor defect of safety provide a kind of FPGA component.

The present invention is to solve above-mentioned technical problem by following technical proposals:

A kind of FPGA component, the FPGA component include: solid state hard disk, DDR (Double Data Rate synchronous dynamic random storage Device) and control unit；

The solid state hard disk is for storing interface data packet；

Described control unit is used to read the interface data packet from the solid state hard disk and the DDR is written；

Described control unit is also used to read the display of man-machine interface described in the interface data packet and composition from the DDR Frame.

Preferably, the solid state hard disk is also used to storage configuration data packet；

The DDR is also used to store the text data of peripheral apparatus transmission；

Described control unit is also used to according to the interface data packet and in conjunction with the text data and/or the configuration number The display frame of the man-machine interface is formed according to packet.

Preferably, described control unit is also used to when judging text data change, according to the textual data after change Frame is shown according to reformulating.

Preferably, the DDR is also used to store the operational order of external equipment transmission；

Described control unit is also used to update the display frame according to the operational order.

Preferably, the interface data packet includes: the background data of the man-machine interface and the pixel data of control；

The pixel data includes at least one of following parameter: control type, control size, control location, control Access link；

The access link characterizes the corresponding relationship of the control and the interface data packet.

Preferably, the interface data packet further include: the icon data of mouse；

When the operational order is write command, described control unit is specifically used for basis and writes data reformulation display frame To update the display frame；The write command includes write data；

When the operational order is jump instruction, described control unit is specifically used for being linked according to the access of target widget The DDR is written from the solid state hard disk part by corresponding interface data packet, and reformulates display frame to update the display Frame；The jump instruction includes the target widget；

When the operational order is the change directive of the icon data, described control unit is specifically used for according to position Information modifies the display frame to update the display frame；The change directive includes the location information.

Preferably, the FPGA component further include: group depacketization logic unit；

Described group of depacketization logic unit judges institute for unpacking to the received interface data packet of the FPGA component Whether the number of dropped packets for stating interface data packet and/or wrong packet number are in respective threshold range, and when being judged as YES, after unpacking Interface data packet re-group package and be sent to the solid state hard disk.

Preferably, described group of depacketization logic unit is also used to be sent out reissue commands when being judged as NO.

Preferably, the quantity of described control unit be it is multiple, multiple control units are connected by SerDes interface communication；

And/or the FPGA component further includes power supply unit, the power supply unit successively gives the solid state hard disk, described Control unit and DDR power supply.

Preferably, the FPGA component further includes metal shell；

The solid state hard disk, the DDR, described control unit and the power supply unit are set in the metal shell.

The positive effect of the present invention is that: FPGA component of the invention can be used for realizing interface display, without any CPU, operating system and software support avoid the invasion of hacker and virus, and safety greatly improves, and also have circuit letter It is clean, without leave unused circuit, it is low in energy consumption the advantages that.

Detailed description of the invention

Fig. 1 is a preferred embodiment of the present invention the structural schematic diagram of FPGA component.

Fig. 2 powers on order schematic diagram for the power supply unit in Fig. 1.

Specific embodiment

The present invention is further illustrated below by the mode of embodiment, but does not therefore limit the present invention to the reality It applies among a range.