阅读说明：本技术 改进的三维纵向存储器 (Improved three-dimensional longitudinal memory ) 是由 张国飙 于 2018-09-20 设计创作，主要内容包括：在共享型三维纵向存储器(3D-M<Sub>V</Sub>)(20)中,每条水平地址线(8a)含有至少第一低掺杂区域(9a)和第二低电阻区域(7a)。低掺杂区域(9a)环绕至少部分存储井(2a,2b…)、并被多个低漏电存储元(1aa,1ab…)共享。低电阻区域(7a)形成一导电网络,以降低水平地址线(8a)的电阻。(In shared three-dimensional longitudinal memory (3D-M V ) in (20), every horizontal address wire (8a) contains at least the first low doped region (9a) and the second low resistance region (7a).Low doped region (9a) is around at least partly storage well (2a, 2b ...) and shared by multiple Low dark curients storage first (1aa, 1ab ...).Low resistance region (7a) forms a conductive network, to reduce the resistance of horizontal address wire (8a).)

1. a kind of three-dimensional longitudinal memory (3D-M_V), it is characterised in that contain:

One contains the semiconductor substrate (0) of a substrate circuitry (0K)；

Multilayer is in the horizontal address wire (8a-8h) on the substrate circuitry (0K)；

Multiple storage wells (2a-2d) for penetrating the multiple-layer horizontal address wire (8a-8h)；

The programming film (6a-6d) of multiple covering storage well (2a-2d) side walls；

The a plurality of vertical address wire (4a-4d) being formed in the storage well (2a-2d)；

Each multiple-layer horizontal address wire (8a) contains at least first area (9a) and second area (7a), the first area The resistivity of (9a) is greater than the second area (7a).

2. memory according to claim 1, it is further characterized in that:

The first area (9a) contains at least one low-doped semiconductor material；

The second area (7a) contains at least a high doping semiconductor material or a metal material.

3. memory according to claim 1, it is further characterized in that: the area of the first area (9a) is greater than described the Two regions (7a).

4. memory according to claim 1, it is further characterized in that: the storage well (2a-2h) penetrates firstth area Domain (9a) and second area (7a).

5. memory according to claim 1, it is further characterized in that containing: multiple to be formed in the horizontal address wire (8a- 8h) and the storage of vertical address wire (4a-4d) infall is first (1aa-1ah), storage member in the first area (9a) Area density is greater than the second area (7a).

6. memory according to claim 1, it is further characterized in that: all storage wells (2a, 2b, 2d, 2e, 2f, 2h) are only Penetrate the first area (9a), without penetrating the second area (7a).

7. a kind of three-dimensional longitudinal memory (3D-M_V), it is characterised in that contain:

One contains the semiconductor substrate (0) of a substrate circuitry (0K)；

Multilayer is in the horizontal address wire (8a-8h) on the substrate circuitry (0K)；

Multiple storage wells (2a-2h) for penetrating the multiple-layer horizontal address wire (8a-8h)；

The programming film (6a-6d) of multiple covering storage well (2a-2h) side walls；

The a plurality of vertical address wire (4a-4d) being formed in the storage well (2a-2d)；

Each multiple-layer horizontal address wire (8a) is containing at least one around the firstth area of at least partly described storage well (2a-2h) Domain (9a*), the first area (9a*) contain at least one low-doped semiconductor material.

8. memory according to claim 7, it is further characterized in that: each multiple-layer horizontal address wire (8a) is containing extremely Few one is located at the second area (7a*) other than the first area (9a*), and the resistivity of the second area (7a*) is greater than institute State first area (9a*).

9. memory according to claim 8, it is further characterized in that: the second area (7a*) is highly doped containing at least one Miscellaneous semiconductor material or a metal material.

10. a kind of semiconductor memory, it is characterised in that contain:

Multiple storage members in first state, including at least first state storage member；

Multiple storage members for being in the second state, including at least Low dark curient storage member and at least one high electric leakage storage member；

At least one address wire, the address wire leak first state storage member, Low dark curient storage member and the height Electricity storage member coupling；

The high electric leakage storage member resistance more first than Low dark curient storage is low, and the Low dark curient storage member is deposited than the first state It is low to store up first resistance.

Technical field

The present invention relates to integrated circuit memory fields, more precisely, being related to three-dimensional storage.

Background technique

Three-dimensional longitudinal direction memory (3D-M_V) it is a kind of monomer (monolithic) semiconductor memory, it contains multiple rows Column on substrate, vertical storage string, each storage string contains the storage member of multiple vertical stackings.Due to 3D-M_VStorage member It is distributed in three dimensions, and the storage member of legacy memory is distributed on two-dimensional surface, 3D-M_VIt is big with storage density, deposit Store up the advantages that at low cost.

Figure 1A-Figure 1B shows a kind of tradition 3D-M_VThe 10(prior art) overall structure.Figure 1A is its sectional view, it contains There are substrate circuitry 0K, horizontal address wire 8a-8h, storage well 2a-2d, programming film 6a-6d, vertical address wire 4a-4d and storage member 1aa-1ha….Substrate circuitry 0K is formed in semi-conductive substrate 0.Horizontal address wire 8a-8h is stacked on substrate circuitry 0K Side, is separated by insulating layer 5a-5g therebetween.Storage well 2a-2d penetrates horizontally location line 8a-8h and insulating layer 5a-5g.Program film The side wall of 6a-6d covering storage well 2a-2d.Conductive material fills the remaining space of storage well 2a-2d, forms vertical address wire 4a-4d.The infall of horizontal address wire 8a-8h and vertical address wire 4a-4d form multiple storage member 1aa-1ha.Wherein, with it is same The storage member 1aa-1ha of one vertical address wire 4a coupling constitutes a storage string 1A.

Figure 1B is the top view of horizontal address wire 8a.Horizontal address wire (also known as horizontal conductor plate) 8a, which is one, to be had The horizontal conductor plate of size is limited, storage well 2a-2h penetrates the horizontal address wire 8a, and the side wall of storage well 2a-2h is programmed film 6a- 6h covering, then forms a plurality of vertical address wire (also known as vertical conductor lines) 4a-4h.In horizontal address wire 8a and vertical address Multiple storage member 1aa-1ah are formed between line 4a-4h.

Fig. 1 C is the symbol of storage member 1.Storage member 1 contains programming film 12 and diode 14.The resistance of programming film 12 can lead to Cross the change of an at least electrical programming signal.There are two ports for diode 14: anode (also known as anode) 1+ and cathode are (also known as negative Pole) 1-.The electric current of diode 14 is easy to flow to cathode 1- from anode 1+, but is not easy to reverse flow.Particularly, diode has There is following generalized character；Alive numerical value is less than read voltage V outside_ROr direction and read voltage V_RWhen opposite, resistance, which is greater than, to be read Resistance (i.e. reading resistance) under voltage.In other patents and technical literature, 3D-M_VIn diode be also referred to as selector (selector), it selects to titles such as device (steering element), quasi- conductive membranes.In the present specification, these titles all have There are identical meanings.

Diode 14 be preferably a self-built diode, i.e., it be naturally formed at horizontal address wire 8a and vertical address wire 4a it Between, without individual diode film.In order to reduce the reverse leakage current of diode 14 and improve its breakdown reverse voltage, P- N junction diode and Schottky diode preferably contain a low doped region.Such as P-N junction diode is using P+/N-/- N+ knot Structure, Schottky diode use metal/N-/N+ structure.In above-mentioned two example, low doped region is a N-type semiconductor Film, thickness is in tens nanometer between some tens of pm.In the present specification, low doped region contains N-type semiconductor material, sheet Levy the combination of (i type) semiconductor material, P-type semiconductor material or above-mentioned material.

Fig. 1 D is the circuit diagram of storage array 10a.Storage array 10a contains wordline 8a-8h, bit line 4a-4h and storage First 1aa-1ah....In storage array 10a, all wordline 8a-8h, bit line 4a-4h are continuous, untotal with adjacent storage array It enjoys.In this embodiment, wordline 8a-8h is coupled with the anode 1+ of diode 14 in storage member 1aa-1ah, bit line 4a-4h with deposit Store up the cathode 1- coupling of diode 14 in member 1aa-1ah.In read procedure, apply read voltage V in a wordline_R, then in phase Electric signal is read on the bit line answered, to obtain the information of respective stored member storage.It is noted that in legacy memory, Suo Youwei Program storage member 1aa-1ah ... has similar physical structure.When the identical digital code information of program storage member storage (is located In identical digital state) when, they have similar electrical characteristic (i.e. I-E characteristic).

Fig. 1 E indicate one storage the member 1aa(prior art) structure.The anode 1+ of diode 14 is horizontal address wire 8a, yin Pole 1- is vertical address wire 4a.It is, in general, that anode 1+ contains P+ type semiconductor material (for P-N junction diode) or metal material Expect (for Schottky diode)；Cathode 1- contains N-type semiconductor film 4a` and N+ type semiconductor film 4a.In the figure, N-type Semiconductor film 4a` and N+ type semiconductor film 4a is both formed in storage well 2a.Due to containing N-type semiconductor film in storage well 2a Diameter d of the diameter D of 4a`, storage well 2a equal to vertical address wire 4a, twice of N-type semiconductor film 4a` thickness T, it is compiled with twice The sum of journey film 6a thickness t, i.e. D=d+2T+2t.Due to T numerical value in tens nanometer between some tens of pm, storage well 2a's is straight Diameter D is excessive, this can reduce storage density and improve carrying cost.

Summary of the invention

The main object of the present invention is to improve three-dimensional longitudinal memory (3D-M_V) storage density.

It is another object of the present invention to reduce 3D-M_VCarrying cost.

It is another object of the present invention to keep the diameter of storage well smaller.

It is another object of the present invention to keep the spacing of storage well closer.

In order to realize that these and other purpose, the present invention propose a variety of improved three-dimensional longitudinal memory (3D-M_V).

In order to keep the diameter of storage well smaller, the present invention proposes a kind of dual area 3D-M_V.Not with the prior art in Fig. 1 E Together, dual area 3D-M_VThe low doped region of middle diode is located at outside storage well.Since storage well contains only vertical address wire and volume Journey film, therefore its diameter D is smaller.Particularly, dual area 3D-M_VHorizontal address wire contain at least two regions: first area And second area.First area be one around storage well low doped region, it contains low-doped semiconductor material.It is low-doped Semiconductor material can reduce the reverse leakage current of diode and improve breakdown reverse voltage.Second area is low resistance region, it Except low doped region.An at least conductive material is contained in low resistance region, and resistivity is lower than low doped region.Low resistance Region can reduce the resistance of horizontal address wire, shorten 3D-M_VAccess time.

In order to keep the spacing of storage well closer, the present invention also proposes a kind of shared 3D-M_V.Shared 3D-M_VIt is dual area 3D-M_VFurther improvement, low doped region is shared by multiple storages member.Particularly, horizontal address wire contains at least Two regions: the first low doped region and the second low resistance region.Each low doped region contains multiple storage members, these storages Member is formed in the infall of low doped region Yu a plurality of vertical address wire.Since the storage member in low doped region is with lower Reverse leakage current, these storage members are referred to as Low dark curient storage member.On the other hand, the conductive material in low resistance region constitutes one Conductive network, it provides a low-resistance current path, to reduce access time and reduce program voltage.

Member is stored relative to Low dark curient, being formed in low resistance region and the storage member of a plurality of vertical address wire infall has Higher reverse leakage current, therefore they are referred to as high electric leakage storage member.Although shared 3D-M_VStorage array in contain simultaneously Low dark curient storage member and high electric leakage storage member, as long as the quantity of high electric leakage storage member stores member, shared 3D- far fewer than Low dark curient M_VReadwrite performance be unaffected.

The present invention discloses a variety of shared 3D-M_VEmbodiment.In the first embodiment, low doped region and low resistance Storage member is contained in region, and (area density refers to horizontal address wire to the storage member area density having the same in the two regions Storage member number on unit area).As long as the area of low doped region is much larger than low resistance region, which can normal work Make.In this embodiment, low doped region has rectangular shape.Second embodiment is similar with first embodiment, only its low-mix Miscellaneous region is hexagonal shape.For man skilled in the art scholar, low doped region can also have other geometries. In the third embodiment, for the area density of high electric leakage storage member lower than Low dark curient storage member, this can improve 3D-M_VRead-write Energy.In the fourth embodiment, low doped region 7a and the infall of vertical address wire do not form storage well or storage member.Due to Only low doped region contains storage member and low resistance region is first without containing storage, therefore storage array only contains Low dark curient storage It is first and first without containing high electric leakage storage.This can be further improved 3D-M_VReadwrite performance.

Notice shared 3D-M_VIt is different from legacy memory.In legacy memory, all unprogrammed storage members are (such as State ' 0 ') there is similar physical structure；Store same digital code information (i.e. in same digital state, such as state ' 1 ') Program storage member has similar electrical characteristic.And in shared 3D-M_VIn, even if Low dark curient storage member and high electric leakage storage member In same digital state (such as state ' 1 '), they still have different electrical characteristics: height electric leakage stores first (such as state ' 1 ') Resistance be less than Low dark curient and store first (such as state ' 1 ')；The resistance that Low dark curient stores first (such as state ' 1 ') is less than unprogrammed storage First (such as state ' 0 ').

Correspondingly, the present invention proposes a kind of three-dimensional longitudinal memory (3D-M_V), it is characterised in that contain: one containing a lining The semiconductor substrate (0) of bottom circuit (0K)；Multilayer is in the horizontal address wire (8a-8h) on the substrate circuitry (0K)；It is multiple Penetrate the storage well (2a-2d) of the multiple-layer horizontal address wire (8a-8h)；Multiple covering storage well (2a-2d) side walls It programs film (6a-6d)；The a plurality of vertical address wire (4a-4d) being formed in the storage well (2a-2d)；Each multilayer Horizontal address wire (8a) is greater than containing at least first area (9a) and second area (7a), the resistivity of the first area (9a) The second area (7a).

The present invention also proposes another three-dimensional longitudinal memory (3D-M_V), it is characterised in that contain: one containing substrate electricity The semiconductor substrate (0) on road (0K)；Multilayer is in the horizontal address wire (8a-8h) on the substrate circuitry (0K)；It is multiple to penetrate The storage well (2a-2h) of the multiple-layer horizontal address wire (8a-8h)；The programming of multiple covering storage well (2a-2h) side walls Film (6a-6d)；The a plurality of vertical address wire (4a-4d) being formed in the storage well (2a-2d)；Each multiple-layer horizontal Location line (8a) is containing at least one around the first area (9a*) of at least partly described storage well (2a-2h), the first area (9a*) contains at least one low-doped semiconductor material.

Present invention further propose that a kind of semiconductor memory, it is characterised in that contain: multiple depositing in first state Chu Yuan, including at least first state storage member；Multiple storage members for being in the second state, including at least Low dark curient storage member At least one high electric leakage storage member；At least one address wire, the address wire first, described Low dark curient by first state storage Storage member and the high electric leakage storage member coupling；The high electric leakage storage member resistance more first than Low dark curient storage is low, described low Electric leakage storage member resistance more first than first state storage is low.

Detailed description of the invention

Figure 1A is a kind of tradition 3D-M_VThe z-x sectional view (prior art) of A-A` along Figure 1B；Figure 1B is its horizontal address The x-y top view (prior art) of line 8a；Fig. 1 C indicates the symbol and its meaning of its storage member；Fig. 1 D is the 3D-M_VStore battle array The circuit diagram (prior art) of column；Fig. 1 E is that a kind of low doped region is located at z-x sectional view (the existing skill that member is stored in storage well Art).

Fig. 2 is a dual area 3D-M_VStore the z-x sectional view of member.

Fig. 3 AA is dual area 3D-M_VStore the z-x sectional view of first first embodiment；Fig. 3 AB indicates the symbol of its storage member Number；Fig. 3 BA is dual area 3D-M_VStore the z-x sectional view of first second embodiment；Fig. 3 BB indicates the symbol of its storage member.

Fig. 4 A is dual area 3D-M_VHorizontal address wire 8a x-y top view；Fig. 4 B is the z- of two adjacent storage member X sectional view.

Fig. 5 A is the first shared 3D-M_VThe z-x sectional view of B-B` along Fig. 5 B；Fig. 5 B is the x- of its horizontal address wire 8a Y top view；Fig. 5 CA is the circuit diagram using the corresponding storage array of storage member in Fig. 3 AA- Fig. 3 AB；Fig. 5 CB is using figure The circuit diagram of the corresponding storage array of member is stored in 3BA- Fig. 3 BB.

Fig. 6 A- Fig. 6 D is the first shared 3D-M_VFour processing steps z-x sectional view.

Fig. 7 A is the second shared 3D-M_VThe z-x sectional view of C-C` along Fig. 7 B；Fig. 7 B is the x- of its horizontal address wire 8a Y top view；Fig. 7 CA is the circuit diagram using the corresponding storage array of storage member in Fig. 3 AA- Fig. 3 AB；Fig. 7 CB is using figure The circuit diagram of the corresponding storage array of member is stored in 3BA- Fig. 3 BB.

Fig. 8 A- Fig. 8 D is four kinds of shared 3D-M_VThe x-y top view of horizontal address wire in embodiment.

It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar Structure.

" in substrate " refers to that function element (active devices) is respectively formed in the substrate (including on substrate surface)； " on substrate " refer to function element be formed in above substrate, not with substrate contact."/" indicates the relationship of "and" or "or".

Specific embodiment

In order to keep the diameter of storage well smaller, the present invention proposes a kind of dual area 3D-M_V.Not with the prior art in Fig. 1 E Together, dual area 3D-M_VThe low doped region of middle diode is located at outside storage well.Since storage well contains only vertical address wire and volume Journey film, therefore its diameter D is smaller.Fig. 2-Fig. 4 B discloses dual area 3D-M_VDetails.

Fig. 2 indicates a kind of dual area 3D-M_VStore member 1aa.It contains a horizontal address wire 8, one and penetrates horizontally location The storage well 2a of line 8a, one layer of programming film 6a for covering storage well 2a side wall and one are formed in storage well 2a vertically Location line 4a.Programming film 6a can be one-time programming (OTP), repeatedly programming (MTP) or overprogram.One-time programming is stored Member, programming film 6a contain an antifuse film.The example of anti-fuse material include silica, silicon nitride, or combinations thereof.For multiple Program storage member or overprogram storage member, programming film 6a contain a writeable film.The example of writable material includes resistive material (RRAM), phase-change material (PCM), connection bridge material (conductive-bridge RAM), magnetoresistance material (MRAM) etc..Programming The thickness of film 6a is between 1 nanometer to 200 nanometers.

Horizontal address wire 8a is containing there are two regions: first area 9a* and second area 7a*.First area 9a* is one circular The low doped region of storage well 2a, it contains at least one low-doped semiconductor material, as N-type semiconductor material, P-type are partly led Body material or intrinsic (i type) semiconductor material.The thickness T of low doped region 9a* is in tens nanometer between some tens of pm.The Two region 7a* are low resistance region, it is located at except low doped region 9a*.Low resistance region 7a* contains an at least conduction material Material, resistivity are lower than low doped region 9a*.The example of conductive material includes that highly doped semiconductor material (partly lead by such as N+ type Body material, P+ type semiconductor material or metal-doped semiconductor material) and metal material (such as metal, metallic compound). The presence of low doped region 9a* can reduce the reverse leakage current of storage member 1aa and improve breakdown reverse voltage；Low resistance region 7a* can reduce horizontal address wire 8a resistance, shorten 3D-M_VAccess time.

Different from the prior art in Fig. 1 E, the low doped region 9a* stored in member 1aa is located at outside storage well 2a.Accordingly Ground, the diameter D of storage well 2a are equal to the sum of the diameter of vertical address wire 4a, twice of thickness t for programming film 6a, i.e. D=d+2t.Cause This, the diameter of the prior art is smaller in diameter D ratio Fig. 1 E of storage well 2a.

Fig. 3 AA- Fig. 3 AB shows dual area 3D-M_VStore the first embodiment of member.In this embodiment, vertical address wire 4a contains P+ type semiconductor material or metal material；The low doped region 9a* of horizontal address wire 8a contains an at least N-type (or i Type) semiconductor material, low resistance region 7a* contains an at least N+ type semiconductor material (Fig. 3 AA).Correspondingly, vertical address wire 4a is coupled with the anode of diode 14, and horizontal address wire 8a couples (Fig. 3 AB) with the cathode of diode 14.

Fig. 3 BA- Fig. 3 BB shows dual area 3D-M_VStore the second embodiment of member.In this embodiment, vertical address wire 4a contains N+ type semiconductor material；The low doped region 9a* of horizontal address wire 8a contains an at least N-type (or i type) semiconductor material Material, low resistance region 7a* contain an at least P+ type semiconductor material or metal material (Fig. 3 BA).Correspondingly, vertical address wire 4a It is coupled with the cathode of diode 14, horizontal address wire 8a couples (Fig. 3 BB) with the anode of diode 14.

Fig. 4 A- Fig. 4 B discloses dual area 3D-M_V30 overall structure.Fig. 4 A shows its horizontal address wire 8a.Storage well 2a-2h penetrates horizontally location line 8a.In storage well 2a-2h, side wall is programmed film 6a-6h covering.Outside storage well 6a-6h Face, low doped region 9a*-9h* is around storage well 2a-2h.Horizontal address wire 8a except low doped region 9a*-9h* is low Resistance region 7a*.

Fig. 4 B shows dual area 3D-M_VAdjacent storage member 1aa, the 1ab of two of 30.Each storage member, which has in Fig. 2, to be shown Structure.There is a low resistance region 7a* between two storage members 1aa, 1ab.Interval S between storage member 1aa, 1ab is equal to The sum of the thickness T`, i.e. S=2T+T` of the thickness T and low resistance region 7a* of twice of low doped region 9a*, 9b*.Due to low-doped For the thickness T of region 9a*, 9b* in tens nanometer between some tens of pm, the interval S of the embodiment is larger.

In order to keep the spacing of storage well closer, the present invention also proposes a kind of shared 3D-M_V.Shared 3D-M_VIt is dual area 3D-M_VFurther improvement, low doped region is shared by multiple storages member.In the following figure, it is total that Fig. 5 A-6D discloses the first Enjoy type 3D-M_V；Fig. 7 A-7CB discloses second of shared 3D-M_V；Fig. 8 A- Fig. 8 D discloses more several embodiments.

Fig. 5 A- Fig. 5 CB indicates the first shared 3D-M_V 20.The shared 3D-M_V 20 contain multiple vertical stackings Horizontal address wire 8a-8h, multiple storage well 2a-2d for penetrating horizontally location line, cover storage well side wall programming film 6a-6d, And a plurality of vertical address wire 4a-4d(Fig. 5 A being formed in storage well 2a-2d).Shared 3D-M_VContain at least two points Area: the first low-doped subregion 9 and the second low resistance subregion 7.All address wire 8a-8h in low-doped subregion 9 contain to A few low-doped semiconductor material, and all address wire 8a-8h being located in low resistance subregion 7 contain an at least low resistance material Material.Correspondingly, address wire 8a-8h is containing there are two regions: the first low doped region 9a-9h and the second low resistance region 7a-7h.

Address wire (such as 8a) horizontal for every, low doped region 9a is by the shared (figure of storage member 1aa, 1ab, 1ae, 1ef 5B).Storage member 1aa, 1ab, 1ae, 1ef are formed in the infall of low doped region 9a Yu vertical address wire 4a, 4b, 4e, 4f, Reverse leakage current is lower, therefore they are referred to as Low dark curient storage member.Storage member 1ac, 1ag be formed in low resistance region 7a with vertically The infall of address wire 1c, 1g, reverse leakage current is higher, therefore they are referred to as high electric leakage storage member.In addition, low resistance region Conductive material in 7a forms a conductive network in horizontal address wire 8a.It provides a low resistance current path, is read with reducing It writes the time and reduces program voltage.

Fig. 5 CA is the circuit diagram using the corresponding storage array 20a of storage member in Fig. 3 AA- Fig. 3 AB.Hollow triangle is (such as Low dark curient storage member 1aa) is represented, black triangle (such as 1ac) represents high electric leakage storage member.As shown in Fig. 3 AB, vertical address wire 4a-4h is coupled with the anode of the storage middle diode 14 of member 1aa-1ah ..., and it acts as wordline；Horizontal address wire 8a-8h and storage The cathode of first middle diode 14 of 1aa-1ah ... couples, and it acts as bit lines.In read procedure, read voltage V_RIt is added in one vertically On location line (wordline, such as 4a), other vertical address wire (wordline) 4b-4h ground connection.Pass through monitoring level address wire (bit line) 8a-8h On voltage change, be stored in storage member 1aa-1ha in information read.In this embodiment, horizontal address wire (bit line) 8a-8h is coupled with sense amplifier (being not drawn into the figure).

Fig. 5 CB is the circuit diagram using the corresponding storage array 20a of storage member in Fig. 3 BA- Fig. 3 BB.As shown in Fig. 3 BB, Vertical address wire 4a-4h is coupled with the cathode of the storage middle diode 14 of member 1aa-1ah ..., and it acts as bit lines；Horizontal address wire 8a-8h is coupled with the anode of the storage middle diode 14 of member 1aa-1ah ..., and it acts as wordline.In read procedure, read voltage V_RAdd On a horizontal address wire (wordline, such as 8a), other horizontal address wire (wordline) 8b-8h ground connection.By monitoring vertical address wire Voltage change on (bit line) 4a-4h, the information being stored in storage member 1aa-1ah are read.In this embodiment, vertically Line (bit line) 4a-4h in location is coupled with sense amplifier (being not drawn into the figure).

Notice shared 3D-M_V20 are different from legacy memory.In legacy memory, all unprogrammed storage members (such as state ' 0 ') has similar physical structure；Store same digital code information (i.e. in same digital state, such as state ' 1 ') The member of program storage have similar electrical characteristic.And in shared 3D-M_VIn 20, even if Low dark curient stores first (such as 1aa) It leaks electricity with height and stores first (such as 1ac) in same digital state (such as state ' 1 '), they still have different electrical characteristics: high The resistance of electric leakage storage member (such as state ' 1 ') 1aa is less than Low dark curient and stores member (such as state ' 1 ') 1ac；Low dark curient storage member is (such as State ' 1 ') resistance of 1aa is less than unprogrammed storage member (such as state ' 0 ').

Fig. 6 A- Fig. 6 D indicates to manufacture the first shared 3D-M_V 20 four processing steps.Manufacture the work of substrate circuitry 0K Skill step is known to professional person, and details are not described herein.After being flattened at the top of substrate circuitry 0K, is deposited on it One layer of low-doped film 12a.The low-doped film 12a thickness is between 5 nanometers to 200 nanometers, it can be N-type doping, P-type is mixed It is miscellaneous or undoped (intrinsic semiconductor).Then, first layer insulating film 5a is deposited on low-doped film 12a.Insulating film 5a thickness Between 5 nanometers to 200 nanometers, it can be silica, silicon nitride, or combinations thereof.It repeats the above steps, it is all until being formed Low-doped film 12a-12h and insulating film 5a-5g(Fig. 6 A).

After foring all low-doped film 12a-12h, the first lithography step is carried out.Photoresist (for simplicity meter, is being schemed Photoresist is not drawn into 6B) block low-doped subregion 9, but exposure low resistance subregion 7.Then ion implanting is carried out.Doping from Attached bag includes N+ ion, P+ ion or metal ion.After ion implantation, region 7a-7h becomes height in low-doped film 12a-12h Doped region, resistivity are lower (Fig. 6 B).

Later, carry out the second lithography step, etch low-doped film 12a-12h with formed a plurality of horizontal address wire 8a-8h and Association structure (Fig. 6 C).Then, third lithography step is carried out, etches low-doped film 12a-12h to be formed and multiple penetrate all water Storage well 2a-2d(Fig. 6 D of flat address wire 8a-8h).Finally, the covering programming film 6a-6d on the side wall of storage well 2a-2d, and Conductor material is filled to form vertical address wire 4a-4d(Fig. 5 A).The processing step phase of above-mentioned processing step and tradition 3D-NAND Seemingly.They are familiar with known to the personage of this profession, and details are not described herein.Entirety is got on very well, shared 3D-M_V 20 have structure letter The advantages that single, it only needs simple process flow.

In shared 3D-M_V In a kind of 20 manufacturing process, low-doped film 12a-12h and insulating film 5a-5g can not be by Interrupt ground, consecutive deposition forms (Fig. 6 A).These films can be formed in a deposition apparatus.Due to not having in deposition process Non- depositing step (such as lithography step), therefore do not need to take out wafer from deposition apparatus.In addition these depositing steps do not influence Planarization can be formed tens of low to hundreds of layers although only depicting eight layers of low-doped film in this figure in practical manufacturing process Doping.In other words, shared 3D-M_V20 can contain tens of to hundreds of layers of horizontal address wire.It was manufactured for above-mentioned Journey, the low resistance region 7a-7h in horizontal address wire 8a-8h are formed by primary ions injection step.

In shared 3D-M_V In 20 another manufacturing process, low resistance region 7a-7h is independently formed (for simplicity meter, In It is not drawn into Fig. 6 A- Fig. 6 D).Such as after forming the first low-doped film 12a, photoetching is carried out and to region 7a ion implanting Or metal silication (silicidation) is carried out to reduce its resistivity.Later, the first insulating layer 5a and the second low-mix are being formed After miscellaneous film 12b, another photoetching is carried out and to region 7b ion implanting or progress metal silication to reduce its resistivity.Above-mentioned step Suddenly other low-doped film 12c-12h can be repeated.The benefit of the way is: different low-doped films (such as 12a, 12b) can be not Low resistance region (such as 7a, 7b) is formed with position, these low resistance regions (such as 7a, 7b) need not be overlapped.

Fig. 7 A- Fig. 7 CB indicates second of shared 3D-M_V20.It is similar to Fig. 5 A- Fig. 5 CB, it is unique unlike Storage member is not formed in low resistance subregion 7.Low resistance region (such as 7a) in horizontal address wire (such as 8a) be it is complete, it does not have It is penetrated by storage well.This is more clearly indicated in Fig. 7 CA and Fig. 7 CB.Storage array 20a contain only Low dark curient storage member 1ac, 1ab, 1ad-1hf, 1ah etc. (are indicated) by hollow triangle, and store first (being indicated by black triangle) without any high electric leakage. Since storage array 20a no longer contains high electric leakage storage member, the shared 3D-M_V20 readwrite performance can be more stable.

Although shared 3D-M_V 20 storage array 20a contains Low dark curient storage member 1aa-1ha ... simultaneously and high electric leakage is deposited Member 1ac-1hc ... is stored up, as long as the quantity of high electric leakage storage member 1ac-1hc ... stores member 1aa-1ha ... far fewer than Low dark curient, is shared Type 3D-M_V20 readwrite performance is unaffected.Correspondingly, the present invention discloses a variety of shared in Fig. 8 A- Fig. 8 D 3D-M_VEmbodiment.In these figures, each stain represents a storage well.For simplicity meter, the specific structure of storage well does not have It draws.

Embodiment in Fig. 8 A corresponds to Fig. 5 A- Fig. 5 CB.Low dark curient storage member 2x is formed in low doped region 9a, height leakage Electricity storage member 2y is formed in low resistance region 7a.Low dark curient stores member 2x and high electric leakage storage member 2y area having the same is close Degree.As long as the area of low doped region 9a is greater than low resistance region 7a, which can be worked normally.In the embodiment of Fig. 8 A In, low doped region 9a is rectangle.In the embodiment of Fig. 8 B, low doped region 9a is hexagon.For being familiar with this profession Personage for, low doped region 9a can also use other geometric figures.In the embodiment of Fig. 8 C, Low dark curient stores member 2x Area density it is identical as Fig. 8 A, but the area density of high electric leakage storage member 2y is less than Fig. 8 A.Compared with Fig. 8 A, less height Shared 3D-M can be improved in electric leakage storage member 2y_V20 readwrite performance.Embodiment in Fig. 8 D corresponds to Fig. 7 A- Fig. 7 CB.In Low doped region 7a and the infall of vertical address wire do not form storage well or storage member.It is deposited since only low doped region contains Chu Yuan and low resistance region without containing storage member, therefore storage array 20a only contain Low dark curient storage member 2x and without containing high Electric leakage storage member.This can be further improved shared 3D-M_V20 readwrite performance.

It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims, The present invention should not be any way limited.