阅读说明：本技术 半导体制程的方法 (Method for semiconductor process ) 是由 刘书豪 陈国儒 吴濬宏 陈佳政 陈亮吟 张惠政 王英郎 于 2019-05-09 设计创作，主要内容包括：本公开涉及一种半导体制程的方法。此处所述的实施例一般关于形成超浅接面于p型源极/漏极区中,且超浅接面具有高掺质浓度与低接点电阻。在一实施例中,方法包括形成源极/漏极区于基板上的主动区中,且源极/漏极区包含锗；进行采用镓的离子布植制程,以形成非晶区于源极/漏极区中；进行采用掺质的离子布植制程至非晶区中；以及对非晶区进行热制程。(The present disclosure relates to a method of semiconductor processing. Embodiments described herein generally relate to forming ultra-shallow junctions in p-type source/drain regions, with high dopant concentrations and low contact resistance. In one embodiment, a method includes forming source/drain regions in an active region on a substrate, the source/drain regions comprising germanium; performing an ion implantation process using gallium to form an amorphous region in the source/drain region; performing an ion implantation process using a dopant into the amorphous region; and performing a thermal process on the amorphous region.)

1. A method of semiconductor processing, comprising:

Forming a source/drain region in an active region on a substrate, the source/drain region comprising germanium;

Performing an ion implantation process using gallium to form an amorphous region in the source/drain region;

Performing an ion implantation process using a dopant into the amorphous region; and

A thermal process is performed on the amorphous region.

Technical Field

Embodiments of the present invention relate to forming an ultra-shallow junction in a p-type source/drain region, where the ultra-shallow junction has a high dopant concentration and low contact resistance.

Background

As the semiconductor industry moves toward the process node of nanotechnology to achieve higher device density, higher performance, and lower cost, three-dimensional designs such as finfet suffer from process and design issues. Finfet transistors typically include high aspect ratio semiconductor fins with channel and source/drain regions formed therein. The gate extends along the sidewalls of the fin structure and onto the fin structure (e.g., wraps around the fin structure), increasing the surface area of the channel to produce a faster, more reliable, and more controllable semiconductor transistor device.

Finfet devices typically include semiconductor regions used to form source and drain regions. Then, a metal silicide is formed on the surface of the semiconductor region to reduce the contact resistance. However, as the size shrinks, new challenges arise with the above-described devices.

Disclosure of Invention

The method for manufacturing a semiconductor provided by an embodiment of the invention comprises the following steps: forming source/drain regions in the active region on the substrate, the source/drain regions comprising germanium; performing an ion implantation process using gallium to form an amorphous region in the source/drain region; performing an ion implantation process using a dopant into the amorphous region; and performing a thermal process on the amorphous region.

Drawings

Fig. 1 is a perspective view of an intermediate structure corresponding to a stage of fabrication in some embodiments.

fig. 2-9 are cross-sectional views of respective intermediate structures at various stages of fabrication in some embodiments.

Figure 10 is a drawing of various dopant profiles, in some embodiments.

FIG. 11 is a partial cross-sectional view of a device structure in some embodiments.

Description of reference numerals:

A-A section

210 metal layer

213 first region

214 silicide layer

215 upper surface of the upper plate

217 second zone

219 amorphous region

220 interface dielectric layer

221 doped region

222 Gate dielectric layer

223 crystalline region

224 compliant layer

226 gate filled with conductive material

228a, 228b replacement gate structure

230 second interlayer dielectric layer

231 pre-amorphous implantation process

232 source/drain contact opening

233 heat treatment

234 conductive structure

251 dummy gate structure

253 groove

270 base plate

274 fins

278 isolation region

280 interfacial dielectric layer

282 dummy gate

284 shade

286 Gate spacer

292 Source/drain regions

296 contact etch stop layer

297 first interlayer dielectric layer

890 insert drawing

892 silicide region

896 first species

898 second species

1012 first contour

1014 second profile

1016 third profile

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, the various embodiments of the present invention may employ repeated reference numbers and/or symbols in order to simplify and clarify the description, but such repetition does not indicate a similar correspondence between similarly numbered elements in the various embodiments.

Furthermore, spatially relative terms such as "below," "lower," "underside," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another element in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

Various embodiments described below generally relate to the use of dopants, such as gallium ions, to form amorphous regions in source/drain regions for p-type field effect transistor devices. For p-type field effect transistors, gallium is a suitable dopant and has a high equilibrium solid solubility. The diffusion of gallium in germanium and silicon germanium containing high concentrations of germanium (e.g., greater than or equal to about 40 atomic%) is slow. Therefore, by disposing Ga in SiGe, an ultra-shallow junction with ultra-high dopant concentration can be formed on the upper surface of the adjacent source/drain region, thereby reducing short channel effect and contact resistance connected to the source/drain region. In some instances, the subsequent dopant implantation process may be omitted.

The foregoing has outlined some of the embodiments of the invention. It is contemplated that planar transistor devices or three-dimensional transistor devices such as finfet devices according to embodiments of the present invention may implement the concepts of the embodiments of the present invention. Some exemplary devices for embodiments described herein may include horizontal full-wrap gate field effect transistors, vertical full-wrap gate field effect transistors, nanowire channel field effect transistors, strained semiconductor devices, silicon-on-insulator devices, fin field effect transistors with fins on crown structures (such as the structure shown in fig. 11) or non-crown structures, or other devices, which may benefit from a pretreatment process to reduce loading effects and/or growth-related issues depending on the substrate.

Fig. 1 is a three-dimensional view of an example of an intermediate structure. Fig. 1 also shows a reference section for the section views of subsequent figures. Fin 274 is formed on substrate 270 of a semiconductor. The semiconductor substrate 270 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator substrate, or the like, which may be doped with p-type or n-type dopants or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 270 may include a semiconductor element such as silicon or germanium, a semiconductor compound, a semiconductor alloy, or a combination thereof. Each fin 274 may provide an active region, where one or more devices are formed. Fin 274 is formed by performing suitable processes on semiconductor substrate 270, including masking, photolithography, and/or etching processes to form trench 253 into substrate 270, while leaving the fin extending upward from substrate 270. The method of patterning fins 274 may be any suitable method. For example, fin 274 may be patterned using one or more photolithography processes, such as a double patterning process or a multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography and self-alignment processes to produce a pattern pitch that is smaller than the pattern pitch produced by a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and uses a photolithography process to pattern the sacrificial layer. Spacers are formed along the sides of the patterned sacrificial layer by a self-aligned process. The sacrificial layer is then removed, fin 274 is patterned with the remaining spacers and trench 253 is formed. The trench 253 can then be filled with an insulating material such as an oxide (e.g., silicon oxide), nitride, the like, or combinations thereof. The insulating material may be recessed to form isolation regions 278 and the recessing process may employ an acceptable etch process. After the insulating material is recessed, fins 274 protrude from between adjacent isolation regions 278 and above isolation regions 278.

Dummy gate structure 251 is formed on fin 274. Dummy gate structure 251 is located on fin 274 and extends in a direction perpendicular to fin 274. Each dummy gate structure 251 includes an interfacial dielectric layer 280, a dummy gate 282 over the interfacial dielectric layer 280, and a mask 284 over the dummy gate 282. The interfacial dielectric layer 280, the dummy gate 282, and the mask 284 for the dummy gate structure 251 are formed by sequentially forming respective layers and then patterning the layers to form the dummy gate structure 251. For example, the layer for the interfacial dielectric layer 280 may comprise or may be silicon oxide, silicon nitride, the like, or multiple layers thereof. The layer used for the dummy gate 282 may comprise or may be silicon (e.g., polysilicon) or another material. The layer used for the mask 284 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The layer formation method or deposition method may be any suitable deposition technique. The layers for the interfacial dielectric layer 280, the dummy gate 282, and the mask 284 are then patterned to form the interfacial dielectric layer 280, the dummy gate 282, and the mask 284 for the dummy gate structure 251. For example, the patterning process may employ photolithography and one or more etching processes.

Fig. 2-9 are cross-sectional views of respective intermediate structures corresponding to various stages of fabrication, which correspond to section a-a in fig. 1. Cross-section a-a in figure 1 is along the plane of the channel in fin 274 between source/drain regions 292 on both sides.

as shown in fig. 2, gate spacers 286 are formed along sidewalls of dummy gate structure 251, such as sidewalls of interfacial dielectric layer 280, dummy gate 282, and mask 284, and on fin 274. For example, the gate spacers 286 may be formed by conformably depositing one or more layers of material for the gate spacers 286 and anisotropically etching the one or more layers of material. The one or more layers of material used for gate spacers 286 may be different than the material used for dummy gate structure 251. In some embodiments, the gate spacers 286 may comprise or may be a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, multiple layers thereof, or combinations thereof, and may be deposited by any suitable deposition technique.

After forming gate spacers 286, source/drain regions 292 may be formed in fins 274 on both sides of dummy gate structure 251, as shown in figure 3. In some examples, the method of etching recesses in fin 274 may use dummy gate structure 251 and gate spacers 286 as a mask. Material may be epitaxially grown in the recesses to form source/drain regions 292. In some embodiments, the epitaxial source/drain structures may be raised structures having an upper surface that is higher than an original upper surface of fin 274. In additional or alternative embodiments, source/drain regions 292 may be formed by masking dummy gate structure 251 and implanting dopants into fin 274 and/or epitaxial source/drain regions 292.

The material used for source/drain regions 292 may comprise or may be silicon germanium (SixGe1-x, where x is between approximately 0 and 1), silicon carbide, silicon phosphide, silicon carbon phosphide, germanium, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like, depending on the conductivity type of the transistor. For example, materials used to form III-V semiconductor compounds may include indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum phosphide, gallium phosphide, or the like. In some examples, silicon germanium or silicon may be included in the source/drain regions 292 of p-type devices, such as p-type field effect transistors, while silicon carbon phosphide or silicon phosphide may be included in the source/drain regions 292 of n-type devices, such as p-type field effect transistors. The source/drain regions 292 are designed to produce a strain effect, thereby enhancing the carrier mobility of the n-type field effect transistor channel and the p-type field effect transistor channel, respectively. Source/drain regions 292 may be raised with respect to fin 274 and have a crystal plane corresponding to a crystallographic plane of substrate 270 of the semiconductor.

Various embodiments described herein provide high dopant concentrations for p-type devices, thereby improving device performance. Although embodiments of the present invention are primarily p-type devices, it should be understood that this concept can also be used for n-type devices. In some embodiments, the source/drain regions 292 for p-type devices are silicon germanium with a germanium concentration between about 0 atomic% and about 100 atomic%, such as between about 20 atomic% and about 60 atomic%, and such as about 40 atomic%. Higher concentrations of ge in sige, such as greater than or equal to 20 at%, may introduce strain into the transistor channel, thereby increasing hole mobility and channel drive current. The concentration of the germanium portion may be a graded concentration along the thickness direction of source/drain region 292. For example, the portion of source/drain region 292 toward upper surface 215 of source/drain region 292 has the greatest germanium concentration in source/drain region 292. While the germanium concentration away from upper surface 215 may decrease as the depth in source/drain region 292 increases. Source/drain region 292 may thus have at least a high germanium concentration region and a low germanium concentration region. In the embodiment shown in fig. 3, the source/drain region 292 for a p-type device has a first region 213 at the upper surface 215 of the source/drain region 292 (or adjacent to the upper surface 215) and a second region 217 radially outward of the first region 213, with the germanium concentration decreasing radially from the first region 213 to the second region 217. In some examples, the germanium concentration of the first region 213 may be between about 20 atomic% and about 100 atomic%, such as between about 40 atomic% and about 80 atomic%, and the other portion is silicon. The germanium concentration of the second region 217 may be between about 0 atomic% and about 20 atomic%, such as between about 5 atomic% and about 15 atomic%, with the remainder being silicon.

Varying the flow of the germanium-containing precursor and fixing the flow of the silicon-containing precursor during the process results in different germanium concentrations. Suitable silicon-containing precursor gases may include or may be silane or higher silanes (SixH (2x +2), such as disilane, trisilane, or tetrasilane), or a combination of any of the above. Suitable germanium-containing precursor gases may include or may be germane, digermane, or a combination of any of the above. The source/drain regions 292 may be epitaxially deposited using cvd, lpcvd, or the like.

As shown in fig. 4, a contact etch stop layer 296 and a first interlayer dielectric 297 are sequentially formed on the surfaces of the source/drain regions 292, the sidewalls and the upper surface of the gate spacers 286, the upper surface of the mask 284, and the upper surface of the isolation regions 278, and may be formed by any suitable deposition technique. The contact etch stop layer 296 may be conformally deposited and may comprise or may be silicon nitride, silicon carbonitride, carbon nitride, the like, or combinations thereof. The first interlayer dielectric 297 may comprise or may be tetraethoxysilane oxide, silicon oxide, a low-k dielectric material (e.g., a material having a lower k than silicon oxide), or the like. A cmp process may then be performed to planarize the first interlayer dielectric 297 and the contact etch stop layer 296, and remove the mask 284 of the dummy gate structure 251 so that the top surfaces of the first interlayer dielectric 297 and the contact etch stop layer 296 are flush with the top surface of the dummy gate 282.

The dummy gate structure 251 is then removed by one or more etching processes. After dummy gate structure 251 is removed, a recess is formed between gate spacers 286 (i.e., where dummy gate structure 251 is removed) and the channel region of fin 274 is exposed through the recess. Replacement gate structures 228a and 228b are then formed in the recesses created by the removal of the dummy gate structure 251, as shown in fig. 4. The replacement gate structures 228a and 228b may each include an interfacial dielectric layer 220, a gate dielectric layer 222, one or more optionally formed conformal layers 224, and a gate fill conductive material 226. Interfacial dielectric layer 220 is formed on the upper surface of fin 274 along the channel region. Interfacial dielectric layer 220 may be an oxide (e.g., silicon oxide) formed by thermally or chemically oxidizing fin 274, and/or an oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), and/or other dielectric layers formed using any suitable deposition technique.

Gate dielectric layer 222 may be conformably deposited in the recess formed by the removal of dummy gate structure 251 (e.g., on the sidewalls of gate spacers 286 and interfacial dielectric layer 220), as well as on the upper surfaces of first interlayer dielectric 297, contact etch stop 296, and gate spacers 286. The gate dielectric layer 222 may be or include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other dielectric materials. The high-k dielectric material may have a dielectric constant greater than about 7.0 and may comprise a metal oxide or metal silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, multiple layers thereof, or combinations thereof.

The one or more optionally formed compliant layers 224 may include one or more barrier and/or cap layers, and one or more work function adjusting layers. The one or more barrier layers and/or cap layers may comprise tantalum nitride, titanium nitride, the like, or combinations thereof. The one or more work function adjusting layers may include or may be titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, the like, or combinations thereof. The choice of materials for the one or more work function adjusting layers, barrier layers, and/or cap layers depends on the desired threshold voltage of the transistor, such as a p-type field effect transistor or an n-type field effect transistor. A gate fill conductive material 226 is formed on one or more of the compliant layers 224 (if compliant layers 224 are formed) and/or on the gate dielectric layer 222. The gate fill conductive material 226 may fill the recess left after the dummy gate structure 251 is removed. The gate fill conductive material 226 may be or include a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multilayers thereof, combinations thereof, or the like.

A planarization process, such as chemical mechanical polishing, may remove portions of gate fill conductive material 226, one or more conformal layers 224, and gate dielectric layer 222 above the upper surfaces of first interlayer dielectric 297, contact etch stop layer 296, and gate spacers 286. The replacement gate structures 228a and 228b may each include a gate fill conductive material 226, one or more compliance layers 224, a gate dielectric layer 222, and an interfacial dielectric layer 220, as shown in fig. 4.

Fig. 4 also shows a second ild layer 230 formed over the gate fill conductive material 226, the one or more conformal layers 224, the gate dielectric layer 222, the first ild layer 297, the gate spacers 286, and the contact etch stop layer 296. The second interlayer dielectric 230 may comprise or may be silicon oxide, a low-k dielectric material, silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, silicon carbide material, combinations thereof, composites thereof, the like, or combinations thereof.

After forming the second interlayer dielectric layer 230, source/drain contact openings 232 are formed through the second interlayer dielectric layer 230, the first interlayer dielectric layer 297, and the contact etch stop layer 296 to expose at least a portion of the source/drain regions 292, as in the example of fig. 4. In some embodiments, the source/drain contact opening 232 may extend to the source/drain region 292 to create a metal contact that may extend to the upper surface of the source/drain region 292 or extend below the upper surface of the source/drain region 292. For example, the second interlayer dielectric 230, the first interlayer dielectric 297, and the contact etch stop layer 296 may be patterned to form the source/drain contact openings 232, and the patterning process may employ photolithography and one or more etching processes. The source/drain contact openings 232 may be used to make electrical contact to the source/drain regions 292 of the transistor.

After the formation of the source/drain contact openings 232, a pre-amorphization implant 231 is performed to amorphize portions of the exposed source/drain regions 292, where silicide regions are then formed. As shown in fig. 5, the pre-amorphization implantation process injects impurity species into the source/drain regions 292 to form amorphous regions 219. In some examples, the depth of the amorphous region 219 may be between about 2nm and about 20nm from the upper surface of the source/drain region 292 downward. In one embodiment, the pre-amorphization implantation process is an ion implantation process that introduces a first species into the exposed source/drain region 292, at least at the top of the source/drain region 292, to transform the structure into an amorphous structure. The amorphous regions 219 prevent subsequently implanted dopants/impurities from tunneling through the spaces between the lattice structures, resulting in dopant/impurity depths exceeding the desired depth. Subsequent dopants/impurities may be localized to regions in the amorphous region 219 and/or adjacent to the upper surface of the source/drain regions 292. As a result, the contact resistance between the subsequently formed source/drain region 292 and the conductive structure may be significantly reduced.

In some embodiments, the first species to be doped is a group III element such as gallium, indium, thallium, or combinations thereof. In one embodiment, the first species is Ga 69. A pre-amorphization implant may be performed on the semiconductor substrate 270 while the second ild 230, the first ild 297, and/or the contact etch stop 296 collectively act as an implant mask to form an amorphous region 219 in the source/drain regions 292 exposed by the source/drain contact openings 232. Amorphous region 219 typically has a random distribution of a first species, such as gallium, therein. In some embodiments, the pre-amorphous implantation process may produce a gaussian distribution of the first species in the crystal lattice of the source/drain region 292 with a peak or highest concentration of atoms near the upper surface 215 of the source/drain region 292 and a lower concentration deeper in the source/drain region 292. In some examples, the peak concentration of gallium is about 1 x 1022 atoms/cm 3 or greater, the vertical depth is between about 2nm to about 6nm, and the gradient rate of decline of the gallium concentration may be about ten times less per 2.5 nm. In some examples, the peak concentration of gallium is about 1 x 1022 atoms/cm 3 or greater, the vertical depth is between about 2nm to about 8nm, and the gradient rate of decline of the gallium concentration may be about ten times less per 2.5 nm.

A pre-amorphous implant process using gallium (e.g., Ga69) may have some advantages. In some embodiments, it may be advantageous to use gallium as the first species for the pre-amorphous implantation process because gallium has an atomic radius (e.g., elemental size) that is larger than many dopant atoms (e.g., boron, germanium, or silicon). Gallium is less likely to diffuse deep into the lattice structure of silicon germanium. This allows the dopant profile to remain close to the profile used to implant the dopant after subsequent processing, such as annealing. This allows the process to be more flexible in terms of thermal budget. For example, dopant implantation may be performed prior to various high temperature processes. In addition, gallium generally has a higher solid solubility in the germanium-based source/drain regions than other dopant species (e.g., boron), particularly in regions having a high concentration of germanium (e.g., first region 213). The higher the solubility of the dopant, the greater the amount of dopant activation that can be achieved. Even at higher temperatures, the gallium in the germanium is highly soluble and diffuses slowly, so the pre-amorphous implantation process may produce a high dopant concentration at the upper surface 215 adjacent to the source/drain regions 292. The pre-amorphization implantation process may contribute more holes at the surface of the source/drain region 292 to improve carrier mobility. In addition, since gallium is less diffusive, short channel effects in transistors such as finfet transistors may be mitigated. Therefore, the dopant dragging problem can be reduced to better control the drain induced barrier lowering effect. Some applications may omit the subsequent dopant implantation step because gallium is also a suitable dopant for p-type devices. The dopant profiles after the pre-amorphization implantation process and the thermal treatment are further described below with reference to fig. 10.

Gallium is illustrated herein, but chemical elements having dimensions larger than the host material (e.g., the substrate to be implanted) and having high solid solubility in the host material may also be contemplated for use on the surface of the pre-amorphous source/drain regions 292.

An exemplary pre-amorphization implantation process employs gallium atoms as follows. The pre-amorphization implantation process may include generating gallium ions and implanting the gallium ions into the exposed source/drain regions 292. Gallium ions may be generated from any suitable gallium ion source, such as a solid, liquid, or gas-based ion source. In examples where a solid gallium source is employed, a solid gallium-containing target material, such as gallium nitride, gallium oxide, gallium arsenide, gallium phosphide, or gallium iodide, may be placed in the plasma chamber. An inert gas may be used to generate a plasma in the plasma chamber. The plasma ions are then accelerated to impinge toward a gallium-containing target to form gallium ions. Gallium ions are implanted into the exposed source/drain regions 292. If the dose of gallium is too high, channel and source/drain regions 292 may be damaged and various problems such as threshold voltage shift and drain induced barrier lowering may be exacerbated. If the dopant amount is too low, a shallow junction with the desired dopant concentration cannot be formed to effectively change the contact resistance. The pre-amorphization implant is designed in accordance with the above considerations. In one embodiment, the implantation energy of the gallium ions is between about 0.5keV and about 20keV, such as between about 2keV and about 6keV, and the implantation dose is between about 1 × 1015 atoms/cm 2 and 2 × 1016 atoms/cm 2. In one embodiment, the implantation energy of the gallium ions is between about 0.5keV and about 20keV, such as between about 2keV and about 6keV, and the implantation dose is between about 5x1014 atoms/cm 2 and 2x 1016 atoms/cm 2. The temperature of the semiconductor substrate 270 during the pre-amorphous implantation process may be maintained between about-150 c and about 450 c, such as between about-100 c and about 30 c. In some examples, the temperature of the semiconductor substrate 270 may be maintained at about-60 ℃ during the pre-amorphization implantation process. Gallium ions may be implanted obliquely, and the angle of the oblique angle with respect to the vertical direction may be between about 0 degrees and about 40 degrees, such as between about 10 degrees and about 35 degrees, and such as about 20 degrees.

It should be appreciated that the parameters described herein may be adjusted to effectively convert the implanted region to an amorphous region regardless of the first species employed. Furthermore, although the amorphous region 219 in the figures is limited to within the boundaries of the first region 213, the amorphous region 219 of some embodiments may extend beyond the first region 213. The depth of the amorphous region 219 may vary depending on the application, and the implantation energy, substrate temperature, and/or tilt angle may be varied to control the depth of the amorphous region 219.

After forming the amorphous regions 219 in the exposed source/drain regions 292, a dopant implant may be performed to introduce a second species, such as boron, into the exposed source/drain regions 292. The dopant implantation process is designed to further reduce the contact resistance of the source/drain regions 292. Due to the characteristics of the second species, the contact resistance between the source/drain region 292 and the subsequently formed conductive structure may be effectively reduced. In particular, due to the random distribution of the large atomic size of the first species (e.g., gallium) in the amorphous region 219 and the presence of a large number of dangling bonds, a large portion of the second species will be trapped or localized in the amorphous region 219. As a result, dopant activation at the surface of source/drain region 292 may be greatly improved, thereby further reducing the contact resistance of the device.

For a p-type device, the second species may comprise boron, aluminum, gallium, indium, thallium, or any combination thereof. In one embodiment, the second species is boron. In some examples, the second species may also include n-type dopants such as phosphorus, arsenic, antimony, or the like. If the first species employed in the pre-amorphous implantation process provides the desired and/or appropriate conductivity for the device, a dopant implantation process may optionally be performed.

The second species formed by the ion implantation process is implanted in substantially the same region as the first species, thereby forming doped regions 221 in the exposed source/drain regions 292, as shown in fig. 6. The doped region 221 may overlap the amorphous region 219, i.e. the second species may be randomly distributed in the amorphous region 219 comprising the first species. In some embodiments, the dopant implantation process may distribute the second species in the amorphous region 219 with a peak or highest concentration of the second species near the top surface of the source/drain region 292 and a lower concentration deeper in the amorphous region 219 (or source/drain region 292). In one embodiment, the peak concentration of the second species at the vertical depth of about 2nm to about 4nm is greater than or equal to about 1 × 1021 atoms/cm 3, and the concentration of the second species in the source/drain region 292 decreases from the peak concentration in a direction away from the upper surface 215 of the source/drain region. The depth of the doped region 221 may be controlled by varying the implantation energy, the substrate temperature, and/or the tilt angle. Although the amorphous regions 219 are typically larger and more deeply distributed in the source/drain regions 292 than the doped regions 221, the doped regions 221 in some embodiments may extend beyond the boundaries of the amorphous regions 219 and to regions between the boundaries of the amorphous regions 219 and the boundaries of the first regions 213. In some embodiments, the dopant region 221 may further extend into the second region 217. In most cases, the subsequent annealing process further increases dopant diffusion.

In one embodiment, the second species (e.g., boron) is implanted at an energy between about 0.5keV and about 10keV and at a dose between about 1X 1012 atoms/cm 2 and about 1X 1016 atoms/cm 2 (e.g., about 1X 1015 atoms/cm 2). If desired, the p-type dopant may be implanted obliquely, and may be at an angle of between about 0 degrees and about 30 degrees relative to the vertical.

Following the optional dopant implantation process, a thermal process 233 is performed to activate the dopants in the source/drain regions 292. The heat treatment 233 may further recrystallize any amorphous source/drain regions. For example, the heat treatment 233 may integrate dopant atoms into the crystal lattice of the source/drain regions 292 to rearrange the crystalline structure of the amorphous regions 219 and redistribute dopant molecules (e.g., the first species and the second species). The alignment of the crystal lattice with the activated dopants reduces the resistance of the doped region. Upon completion of the heat treatment 233, the amorphous regions 219 may transition into crystalline regions 223, as shown in FIG. 7. The crystallization zone 223 may have a random distribution of the first species and the second species therein. In some embodiments, the peak or higher concentration of the first and second species of the crystallized region 223 is adjacent to the upper surface 215 of the source/drain region 292, while the lower concentration (one order of magnitude lower than the peak concentration) of the first and second species is deeper (in a direction away from the upper surface 215) in the crystallized region 223. In one example, the crystalline region 223 may be silicon germanium doped with a first species and a second species. In the example where the first species is gallium and the second species is boron, the crystalline region 223 may be gallium-doped and/or boron-doped silicon germanium.

In one embodiment, the annealing process is a millisecond anneal process. In some embodiments, the millisecond anneal process employs a laser anneal process for an anneal time in the millisecond range. Performing the millisecond anneal process may have the advantage that, even at high anneal temperatures (e.g., 850 c or higher), the very short anneal process may activate the dopants (e.g., the first species and the second species) in the source/drain region 292, but minimize the diffusion of the dopants in the source/drain region 292. Short channel effects are avoided because dopant activation in source/drain region 292 has minimal diffusion. The chamber used to perform the laser annealing process may be an Astra chamber available from Applied Materials, Inc. of Santa Clara, Calif. It is contemplated that a flash lamp annealing process or any advanced process using suitable optical radiation may be used to perform the annealing for a very short time (e.g., on the order of milliseconds).

The laser annealing process is performed by scanning a laser beam from an energy source across the exposed surfaces of source/drain regions 292. The laser beam may be sequentially applied to or scan portions of source/drain region 292. For example, the laser beam may anneal a first portion of source/drain region 292, then substrate 270 of the semiconductor and/or the laser beam may be removed, and the laser beam may anneal a second portion of source/drain region 292. The energy source may be any type of laser such as a gas laser, excimer laser, solid state laser, fiber laser, semiconductor laser, or the like. The laser beam may have a fixed energy flux. When a laser beam is applied to the exposed surface of source/drain region 292, substrate 270 of the semiconductor may be transmitted or scanned relative to the energy delivered to the surface of source/drain region 292 (or vice versa). In various examples, the laser scan rate may be between about 15 mm/sec to about 650 mm/sec, which may vary depending on the dwell time required for the application. The laser beam may be operated to have a desired range of wavelengths and intensities. In some embodiments, the laser beam may have a wavelength between about 200nm and about 20 microns, such as between about 700nm and about 1200nm, and such as between about 950nm and about 1000nm, and the intensity of the laser beam may be between about 0.1W/cm2 and about 10W/cm 2. The laser annealing process may be performed such that each portion upon which the laser is irradiated may be instantaneously heated to about 800 c or higher, such as about 850 c or higher, and such as between about 900 c and about 1200 c. The chamber pressure may be maintained at between about 10Torr and about 850Torr during the laser annealing process. The dwell time of the laser beam may be between about 0.01 milliseconds and about 10 milliseconds, such as between about 0.5 milliseconds and about 5 milliseconds, and such as between 0.1 milliseconds and 3 milliseconds.

In another embodiment, the thermal treatment 233 is a rapid thermal anneal process followed by a millisecond anneal (e.g., the millisecond anneal process described above). In this embodiment, the rapid thermal anneal process may recrystallize or repair the crystalline structure of the amorphous region 219 because gallium is implanted in the source/drain regions 292. The subsequent millisecond anneal rearranges or redistributes the dopant atoms (e.g., the first species and the second species) to activate the dopants. Since the millisecond anneal process is performed in a millisecond range, the diffusion of dopants out of source/drain region 292 is minimized. The intermediate structure of fig. 7 may be heated using an array of lamps, such as halogen lamps or flash lamps, to perform a rapid thermal annealing process. Embodiments of annealing processes using halogen lamps may include heating and maintaining the temperature of the intermediate structure of fig. 7 to 200 c or higher, such as between about 250 c and about 350 c. The light from the halogen lamp is irradiated on the exposed surface of the intermediate structure of fig. 7 for a time period of between about 1 second and 600 seconds (e.g., between about 10 seconds and about 180 seconds) to further heat the surface of the intermediate structure of fig. 7 (e.g., the upper surface 215 of the source/drain region 292) to a temperature of between about 400 c and about 800 c (e.g., between about 550 c and about 700 c or between about 200 c and about 800 c). In some embodiments, the rapid thermal annealing process may be performed after the millisecond anneal process.

After heat treatment 233, a silicide layer is formed on source/drain regions 292. The silicide layer can reduce the contact resistance of the device. In some embodiments, the silicide layer may be formed by forming a metal, such as titanium or tantalum, on the exposed surface of the source/drain region 292 and annealing to react the metal with the material of the source/drain region 292 to form the silicide layer.

In one embodiment, a conformal metal layer 210 is formed on the surface of the exposed source/drain regions 292 and on the surfaces of the second ild layer 230, the first ild layer 297 and the contact etch stop layer 296, as shown in fig. 8. The metal layer 210 may be a single layer or a multi-layer stack. In examples where the metal layer 210 is a single layer, the metal layer 210 may be or may include titanium, tantalum, or the like. In examples where a bi-layer stack is employed as the metal layer 210, the first layer may be or may comprise titanium, tantalum, or the like, while the second layer may be or may comprise titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or the like. The first layer may be formed on the second layer and vice versa. The deposition method of the metal layer 210 may be atomic layer deposition, physical vapor deposition, chemical vapor deposition, or any suitable deposition technique. In the example of using the two-layer structure, the first layer may be formed by physical vapor deposition, and the second layer may be formed by atomic layer deposition. In some embodiments, the metal layer 210 is a titanium layer. In another embodiment, the metal layer 210 is a layered stack with a titanium nitride layer formed on the titanium layer.

After the metal deposition, an annealing process is performed to react the upper portions of the source/drain regions 292 with the metal layer 210 to form the silicide layer 214, as shown in fig. 8. Heating the substrate may cause a silicidation reaction to occur regardless of where the metal layer 210 contacts the source/drain regions 292. Silicidation may occur at the interface between source/drain region 292 and metal layer 210, as well as regions outside and/or surrounding the interface between source/drain region 292 and metal layer 210. In some instances where metal layer 210 is a layered stack (e.g., titanium and titanium nitride), the underlying layer (e.g., titanium) may react with source/drain regions 292 and completely transform into first silicide regions. A portion of the first silicide region may overlap the crystallization region 223. An inset 890 in fig. 8 is an enlarged partial view showing an example of the silicide layer 214, and the silicide layer 214 has silicide regions 892 formed at the interface between the source/drain regions 292 and the metal layer 210. Silicide region 892 may be a titanium silicide such as titanium silicon germanium when metal layer 210 is a layered stack of titanium and titanium nitride. The silicide regions 892 may comprise a first species 896, such as gallium, and a second species 898, such as boron, and/or the first species 896, such as gallium and the second species 898, such as boron, surround the silicide regions 892. In inset 890, first species 896 and second species 898 are enlarged to facilitate understanding. In some examples, the second species 898 is distributed in the crystallization zone 223 in a substantial amount because of the random distribution and the presence of a large number of dangling bonds of the first species 896 (e.g., gallium) having a large atomic size in the crystallization zone 223. In some embodiments, the first species 896 and the second species 898 may be randomly distributed along the interface between the silicide layer 214 and the crystallized region 223. In some embodiments, the first species 896 and the second species 898 may be randomly distributed in the silicide regions 892. In some embodiments, the first species 896 and the second species 898 may be gradually distributed in the silicide regions 892 along the thickness direction of the source/drain regions 292, with the peak concentration or higher concentration of the first species 896 and the second species 898 being near the upper surface 215 of the source/drain regions 292 and the lower concentration (e.g., a concentration at least one order of magnitude lower than the peak concentration) being deeper in the source/drain regions 292.

For example, the annealing process used to form the silicide may be a rapid thermal anneal at a temperature between about 400 ℃ and about 650 ℃ (such as about 500 ℃) for a period of about 5 seconds to about 60 seconds. For example, the thickness of the silicide layer 214 may be between 2nm to about 20 nm. In some examples, the unreacted metal layer 210 may be removed by a selective etch process that may attack the unreacted metal layer 210 but not the silicide layer 214. The selective etching process may be any suitable wet or dry etching process. In some examples, the unreacted metal layer 210 may be used to form an adhesion layer and/or a barrier layer.

As shown in fig. 9, conductive structure 234 is formed in source/drain contact opening 232 to source/drain region 292. For example, each conductive structure 234 can include a compliant adhesion layer formed in the exposed surface of the source/drain contact opening 232, a barrier layer formed on the adhesion layer, and a conductive material formed on the barrier layer. In some embodiments, a liner layer, such as a dielectric spacer liner layer, may be located on the exposed surface of the source/drain contact opening 232 and extend into the source/drain region 292. In this case, the barrier layer may be located inside the dielectric spacer liner layer. The dielectric spacer liner layer may define a bottom cavity in the source/drain region 292 for access. In some embodiments, the dielectric spacer liner layer may extend into the source/drain region 292 to a depth different from the depth of the barrier layer. In some embodiments, the dielectric spacer liner layer may extend to the source/drain regions to a depth greater than the depth of the barrier layer. Suitable materials for the dielectric spacer liner layer may include, but are not limited to, silicon oxycarbide, silicon oxynitride, silicon oxide, silicon nitride, or combinations thereof. The adhesion layer may be or may comprise titanium, tantalum, the like, or combinations thereof, and may be deposited by atomic layer deposition, chemical vapor deposition, or another deposition technique. The barrier layer may be or may comprise titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or combinations thereof, and may be deposited by atomic layer deposition, chemical vapor deposition, or another deposition technique. A conductive material may be deposited on the barrier layer and fill the source/drain contact openings. The conductive material may be or may include tungsten, cobalt, ruthenium, aluminum, gold, silver, alloys thereof, the like, or combinations thereof, and the deposition method thereof may be chemical vapor deposition, atomic layer deposition, physical vapor deposition, or another deposition technique. After the conductive material is deposited, a planarization process, such as chemical mechanical polishing, may be used to remove excess conductive material, barrier layer, and adhesion layer. The conductive structure may be coplanar with the top surface of the second interlayer dielectric layer 230. The conductive structures 234 may be referred to as contacts, plugs, or the like.

Fig. 10 is a graph of dopant profiles after a pre-amorphization implantation process and a thermal process, showing dopant concentrations corresponding to depths (e.g., vertical depths) from the top surface of the source/drain region 292 into the source/drain region 292, in some embodiments. The graph shows a first profile 1012 of boron concentration for a pre-implant process that includes boron implantation followed by gallium implantation. The graph shows a second profile 1014 of boron concentration for a pre-amorphous implant process that includes gallium implantation followed by boron implantation. The graph also shows a third profile 1016 of the gallium concentration, where the pre-amorphization implantation process includes gallium implantation, and may be preceded or followed by boron implantation. For illustrative purposes, the intrinsic material of the source/drain regions is silicon germanium. Gallium is implanted at a temperature of about-60 c during the pre-amorphization implant used for second profile 1014 and third profile 1016. The thermal process for first profile 1012, second profile 1014, and third profile 1016 includes a rapid thermal anneal at 700 c for 90 seconds.

As shown in second profile 1014, the boron concentration at a depth of about 2nm to 4nm when gallium is used to amorphize the source/drain regions is greater than the boron concentration at a depth of about 2nm to 4nm in first profile 1012 where boron was previously used to amorphize the source/drain regions. The second profile 1014 indicates that a significant amount of boron dopant is trapped in the amorphous region due to the presence of gallium implanted by the pre-amorphous implantation process. Thus, implanting gallium prior to implanting dopants such as boron may result in a higher dopant concentration near the surface of the source/drain regions. Third profile 1016 shows that the peak concentration of gallium at the surface of (or adjacent to) the source/drain regions (at a depth between about 1nm to about 3 nm) is about 1 x 1022 atoms/cm 3 because of the larger atomic scale size of gallium and the higher solid solubility in germanium.

Although device structures may differ in different embodiments, it is contemplated that various embodiments of the present invention can be used for finfet transistors having fins on crown structures. FIG. 11 is a partial cross-sectional view of a device structure in some embodiments. The structure of fig. 11 may be referred to as a crown structure, while the structure of fig. 1 may be referred to as a non-crown structure. As shown in fig. 11, the various underside surfaces of the isolation regions 278 may have different heights. The semiconductor substrate 270 may be patterned during formation of fins 274, such as by using two or more patterning and etching processes to obtain the structure described above.

Various embodiments described herein may amorphize at least a portion of the source/drain regions with gallium prior to implanting a second dopant, such as boron, to form high dopant concentration source/drain region surfaces for p-type field effect transistor devices. Gallium has a higher solid solubility in germanium than boron, particularly in silicon germanium, which has a high concentration of germanium (about 40 atomic% or higher). Therefore, gallium may have a higher activation level, thereby contributing more holes than other dopants to improve carrier mobility. On the other hand, the amorphous region generated by the gallium implantation is helpful to capture the dopant implanted on the surface of the source/drain region subsequently, so as to reduce the contact resistance between the source/drain region and the subsequently formed conductive structure. In addition, implanting gallium into silicon germanium may result in high dopant concentrations at the upper surface adjacent to the source/drain regions, since gallium is not readily diffused due to the large size at the atomic level. Therefore, the problem of dopant dragging can be reduced, and the drain induced barrier lowering effect can be better controlled. In addition, since gallium is also a suitable dopant for p-type devices, some embodiments may omit subsequent dopant implantation steps.

In one embodiment, a method of semiconductor processing is provided. The method includes forming source/drain regions in an active region on a substrate, the source/drain regions including germanium; performing an ion implantation process using gallium to form an amorphous region in the source/drain region; performing an ion implantation process using a dopant into the amorphous region; and performing a thermal process on the amorphous region.

In some embodiments, the source/drain regions are silicon germanium having a germanium content of between about 20 atomic% and about 80 atomic%.

In some embodiments, the dose of gallium for the ion implantation process using gallium is between about 1 × 1015 atoms/cm 2 and about 2 × 1016 atoms/cm 2.

in some embodiments, the temperature of the ion implantation process is between about-100 ℃ to about 30 ℃.

In some embodiments, the dopant is a p-type dopant.

In some embodiments, the dopant comprises boron.

In some embodiments, the thermal process comprises a laser annealing process with a laser beam dwell time between about 0.5 milliseconds to about 5 milliseconds.

In another embodiment, a method of semiconductor processing is provided. The method includes forming source/drain regions in an active region on a substrate, the source/drain regions having a germanium concentration greater than or equal to about 20 atomic%; forming a dielectric layer on the active region; forming an opening through the dielectric layer to expose at least a portion of an upper surface of the source/drain region; implanting a first species into the exposed source/drain regions, the first species comprising gallium; implanting a second species into the exposed source/drain region after implanting the first species, the second species comprising a p-type dopant; performing a first annealing process on the exposed source/drain region, wherein the first annealing process is performed for a first time within a first temperature interval; after the first annealing process, performing a second annealing process on the exposed source/drain region, wherein the second annealing process is performed at a second temperature interval for a second time, the second temperature interval is higher than the first temperature interval, and the second time is shorter than the first time; forming silicide regions on the exposed upper surfaces of the source/drain regions; and forming a conductive structure in the opening to reach the upper surface of the source/drain region.

in some embodiments, the source/drain regions are silicon germanium with a germanium concentration between about 40 atomic% and about 80 atomic%.

In some embodiments, the dose of the first species implanted into the exposed source/drain region is between about 1 × 1015 atoms/cm 2 and about 2 × 1016 atoms/cm 2.

In some embodiments, the dose of the first species implanted into the exposed source/drain region is between about 5x1014 atoms/cm 2 and about 2x 1016 atoms/cm 2.

In some embodiments, implanting the first species is at a temperature ranging from about-150 ℃ to about 450 ℃.

In some embodiments, implanting the first species is at a temperature ranging from about-100 ℃ to about 30 ℃.

In some embodiments, the first species is implanted at an energy between about 0.5keV and about 20keV and the angle of inclination of the implant is between about 10 degrees and about 35 degrees.

In some embodiments, the first annealing process comprises a rapid thermal annealing process, the first temperature range is between about 400 ℃ and about 800 ℃ and the first time is between about 1 second and about 600 seconds, and the second annealing process comprises a laser annealing process, the second temperature range is between about 900 ℃ and about 1200 ℃ and the second time is between about 0.5 milliseconds and about 5 milliseconds.

In some embodiments, the first annealing process comprises a rapid thermal annealing process, the first temperature range is between about 200 ℃ and about 800 ℃ and the first time is between about 1 second and about 600 seconds, and the second annealing process comprises a laser annealing process, the second temperature range is between about 900 ℃ and about 1200 ℃ and the second time is between about 0.5 milliseconds and about 5 milliseconds.

In yet another embodiment, a structure is provided. The structure comprises an active region located on a substrate, the active region comprising a source/drain region having a silicide layer located thereon; a dielectric layer located on the active region; and a conductive structure passing through the dielectric layer to the active region and contacting the silicide layer of the source/drain region. The source/drain region includes: a first region adjacent an upper surface of the source/drain region, the first region overlapping at least a portion of the silicide layer, the first region having a first concentration of germanium, the first region comprising gallium, a peak concentration of the gallium adjacent the upper surface of the source/drain region, and a concentration of the gallium in the source/drain region decreasing from the peak concentration in a direction away from the upper surface of the source/drain region; and a second region between the first region and the substrate, the second region having a second concentration of germanium that is lower than the first concentration of germanium.

In some embodiments, the first concentration of germanium is between about 20 atomic% and about 100 atomic%, and the second concentration of germanium is between about 0 atomic% and about 20 atomic%.

In some embodiments, gallium has a peak concentration at a vertical depth of between about 2nm to about 6nm that is greater than or equal to about 1 x 1022 atoms/cm 3.

In some embodiments, gallium has a peak concentration at a vertical depth of between about 2nm to about 8nm that is greater than or equal to about 1 x 1022 atoms/cm 3.

In some embodiments, the silicide layer is titanium silicon germanium.

In some embodiments, the first region further comprises a p-type dopant.

In some embodiments, the p-type dopant has a peak concentration at a vertical depth of between about 2nm and about 4nm that is greater than or equal to about 1 x 1021 atoms/cm 3, and the concentration of the p-type dopant in the source/drain region decreases from the peak concentration in a direction away from the upper surface of the source/drain region.

The features of the above-described embodiments will facilitate understanding of the present disclosure by those skilled in the art. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that these equivalent substitutions and alterations can be made without departing from the spirit and scope of the present disclosure, and that these changes, substitutions, and alterations should also be seen as illustrative embodiments of the present disclosure.