阅读说明：本技术 一种占空比调整电路及其抗噪方法 (duty ratio adjusting circuit and anti-noise method thereof ) 是由 孙欣茁 林长龙 于 2018-05-29 设计创作，主要内容包括：本发明实施例提供了一种占空比调整电路及其抗噪方法,涉及电子技术领域。该占空比调整电路,包括：噪声引入支路和控制支路,所述噪声引入支路与所述控制支路相连接；其中,所述噪声引入支路,用于引入所述占空比调整电路的电压噪声信号,并将所述电压噪声信号与所述占空比调整电路的控制信号进行合成,形成新的控制信号,以及,将所述新的控制信号传输给所述控制支路；所述控制支路,用于根据所述新的控制信号对所述占空比调整电路的输出时钟信号的占空比进行调整。本发明实施例通过引入电压信号中的噪声来抵消电源信号和地信号的噪声,减轻噪声的影响。(The embodiment of the invention provides a duty ratio adjusting circuit and an anti-noise method thereof, relating to the technical field of electronics. The duty ratio adjusting circuit comprises: the noise introducing branch circuit is connected with the control branch circuit; the noise introducing branch is used for introducing a voltage noise signal of the duty ratio adjusting circuit, synthesizing the voltage noise signal and a control signal of the duty ratio adjusting circuit to form a new control signal, and transmitting the new control signal to the control branch; and the control branch circuit is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal. The embodiment of the invention cancels the noise of the power supply signal and the ground signal by introducing the noise in the voltage signal, thereby reducing the influence of the noise.)

1. A duty cycle adjustment circuit, comprising: the noise introducing branch circuit is connected with the control branch circuit;

The noise introducing branch is used for introducing a voltage noise signal of the duty ratio adjusting circuit, synthesizing the voltage noise signal and a control signal of the duty ratio adjusting circuit to form a new control signal, and transmitting the new control signal to the control branch;

And the control branch circuit is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal.

2. The circuit of claim 1, wherein the noise introducing branch comprises at least one noise introducing sub-branch comprising a first transistor and a second transistor;

The first transistor is connected with a first end of the second transistor, and the first end of the second transistor is connected with the control branch circuit;

The first transistor is used for introducing a voltage noise signal of the duty ratio adjusting circuit into the second transistor through a first end of the second transistor;

The second transistor is configured to receive a control signal of the duty ratio adjustment circuit, synthesize the control signal and the voltage noise signal into a new control signal, and provide the new control signal to the control branch.

3. The circuit of claim 2, wherein the control branch comprises a third transistor for connecting a ground signal of the duty cycle adjusting circuit;

The noise introducing sub-branch comprises a ground noise introducing sub-branch which comprises a first transistor and a second transistor;

The first transistor in the ground noise introducing sub-branch is used for connecting the ground signal and introducing the ground noise signal in the ground signal to the first end of the second transistor in the ground noise introducing sub-branch;

The first end of the second transistor in the ground noise introducing sub-branch is connected with the third transistor, so that the ground noise signal carried in the new control signal and the ground noise signal in the ground signal are mutually offset to stabilize the working state of the third transistor.

4. The circuit according to claim 2 or 3, wherein the control branch comprises a fourth transistor for connecting a power supply signal of the duty cycle adjusting circuit;

The noise introducing sub-branch further comprises a power supply noise introducing sub-branch, and the power supply noise introducing sub-branch comprises a first transistor and a second transistor;

the first transistor in the power supply noise introducing sub-branch is used for connecting the power supply signal and introducing a source noise signal in the power supply signal to a first end of a second transistor in the power supply noise introducing sub-branch;

and the first end of the second transistor in the power supply noise introducing sub-branch is connected with the fourth transistor, so that a source noise signal carried in the new control signal and a source noise signal in the power supply signal are mutually offset, and the working state of the fourth transistor is stabilized.

5. The circuit of claim 2, wherein the first transistor is a fet or a transistor and the second transistor is a fet or a transistor.

6. The circuit of claim 1 or 2, further comprising: the device comprises a buffer module and a detection module;

One end of the buffer module is connected with the control branch circuit, and the other end of the buffer module is connected with the detection module, so that the detection module generates a control signal of the duty ratio adjusting circuit according to an output clock signal of the control branch circuit.

7. an anti-noise method of a duty cycle adjustment circuit, comprising:

Introducing a voltage noise signal of the duty ratio adjusting circuit through a noise introducing branch of the duty ratio adjusting circuit;

synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit;

And providing the new control signal to a control branch of the duty ratio adjusting circuit, wherein the control branch is used for adjusting the duty ratio of an output clock signal of the duty ratio adjusting circuit according to the new control signal.

8. The method of claim 7,

The voltage noise signal introduced into the duty ratio adjusting circuit through the noise introducing branch of the duty ratio adjusting circuit comprises: introducing a ground noise signal in a ground signal of the duty ratio adjusting circuit through a ground noise introducing sub-branch;

the synthesizing of the new control signal by using the voltage noise signal and the control signal of the duty ratio adjusting circuit includes: and synthesizing a new control ground signal by adopting a ground noise signal in the ground signal and the control signal of the duty ratio adjusting circuit.

9. the method of claim 7,

The voltage noise signal introduced into the duty ratio adjusting circuit through the noise introducing branch of the duty ratio adjusting circuit comprises: introducing a source noise signal in a power supply signal of the duty ratio adjusting circuit through a power supply noise introducing sub-branch;

the synthesizing of the new control signal by using the voltage noise signal and the control signal of the duty ratio adjusting circuit includes: and synthesizing a new control source signal by adopting a source noise signal in the power supply signal and the control signal of the duty ratio adjusting circuit.

10. The method of any of claims 7 to 9, further comprising:

and adjusting the duty ratio of the output clock signal according to the new control signal through the control branch circuit to obtain an adjusted output clock signal.

Technical Field

The invention relates to the technical field of electronics, in particular to a duty ratio adjusting circuit and an anti-noise method of the duty ratio adjusting circuit.

Background

With the rapid development of computer technology, Duty Cycle (DCC) circuits are increasingly widely used.

For example, in the case of high-speed systems using Double-edge sampling (DDR) techniques, these systems require the duty cycle of the clock signal to be maintained at 50% accurately, so that the rising and falling edges have equal symmetrical phase margins to sample the Data. However, due to Process, Voltage and Temperature (PVT) effects, the input clock signal is distorted after transmission and may deviate significantly from the 50% duty ratio value. Therefore, these systems require a dedicated duty cycle adjustment circuit to correct the duty cycle of the clock signal, ensuring a 50% duty cycle.

At present, the duty ratio adjusting circuit can adopt a full digital mode to realize duty ratio adjustment. Specifically, the duty ratio adjusting circuit in the all-digital mode generally adopts waveform generation (PG), Half-Cycle Delay Line (HCDL), and Phase Frequency Detector (PFD) to realize the function of adjusting the duty ratio, so as to effectively influence the anti-noise fluctuation on the circuit. However, the duty ratio adjusting circuit needs to reconstruct the waveform by using HCDL, which results in a relatively large circuit area and is difficult to integrate into a System with strict area requirements, such as a System On Chip (SOC) System with a tight area.

Disclosure of Invention

In view of the above problems, embodiments of the present invention are proposed to provide a duty cycle adjustment circuit and a corresponding noise-resistant method of a duty cycle adjustment circuit that overcome or at least partially solve the above problems.

In order to solve the above problem, an embodiment of the present invention discloses a duty ratio adjusting circuit, including: the noise introducing branch circuit is connected with the control branch circuit; the noise introducing branch is used for introducing a voltage noise signal of the duty ratio adjusting circuit, synthesizing the voltage noise signal and a control signal of the duty ratio adjusting circuit to form a new control signal, and transmitting the new control signal to the control branch; and the control branch circuit is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal.

Optionally, the noise introducing branch comprises at least one noise introducing sub-branch comprising a first transistor and a second transistor; the first transistor is connected with a first end of the second transistor, and the first end of the second transistor is connected with the control branch circuit; the first transistor is used for introducing a voltage noise signal of the duty ratio adjusting circuit into the second transistor through a first end of the second transistor; the second transistor is configured to receive a control signal of the duty ratio adjustment circuit, synthesize the control signal and the voltage noise signal into a new control signal, and provide the new control signal to the control branch.

Optionally, the control branch includes a third transistor, and the third transistor is used for connecting a ground signal of the duty ratio adjusting circuit; the noise introducing sub-branch comprises a ground noise introducing sub-branch which comprises a first transistor and a second transistor; the first transistor in the ground noise introducing sub-branch is used for connecting the ground signal and introducing the ground noise signal in the ground signal to the first end of the second transistor in the ground noise introducing sub-branch; the first end of the second transistor in the ground noise introducing sub-branch is connected with the third transistor, so that the ground noise signal carried in the new control signal and the ground noise signal in the ground signal are mutually offset to stabilize the working state of the third transistor.

Optionally, the control branch comprises a fourth transistor, and the fourth transistor is used for connecting a power supply signal of the duty ratio adjusting circuit; the noise introducing sub-branch further comprises a power supply noise introducing sub-branch, and the power supply noise introducing sub-branch comprises a first transistor and a second transistor; the first transistor in the power supply noise introducing sub-branch is used for connecting the power supply signal and introducing a source noise signal in the power supply signal to a first end of a second transistor in the power supply noise introducing sub-branch; and the first end of the second transistor in the power supply noise introducing sub-branch is connected with the fourth transistor, so that a source noise signal carried in the new control signal and a source noise signal in the power supply signal are mutually offset, and the working state of the fourth transistor is stabilized.

Optionally, the first transistor is a field effect transistor or a triode, and the second transistor is a field effect transistor or a triode.

Optionally, the duty cycle adjusting circuit further includes: the device comprises a buffer module and a detection module; one end of the buffer module is connected with the control branch circuit, and the other end of the buffer module is connected with the detection module, so that the detection module generates a control signal of the duty ratio adjusting circuit according to an output clock signal of the control branch circuit.

the embodiment of the invention also discloses an anti-noise method of the duty ratio adjusting circuit, which comprises the following steps:

Introducing a voltage noise signal of the duty ratio adjusting circuit through a noise introducing branch of the duty ratio adjusting circuit;

Synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit;

And providing the new control signal to a control branch of the duty ratio adjusting circuit, wherein the control branch is used for adjusting the duty ratio of an output clock signal of the duty ratio adjusting circuit according to the new control signal.

Optionally, the introducing, by the noise introducing branch of the duty ratio adjusting circuit, the voltage noise signal of the duty ratio adjusting circuit includes: introducing a ground noise signal in a ground signal of the duty ratio adjusting circuit through a ground noise introducing sub-branch;

the synthesizing of the new control signal by using the voltage noise signal and the control signal of the duty ratio adjusting circuit includes: and synthesizing a new control ground signal by adopting a ground noise signal in the ground signal and the control signal of the duty ratio adjusting circuit.

Optionally, the introducing, by the noise introducing branch of the duty ratio adjusting circuit, the voltage noise signal of the duty ratio adjusting circuit includes: introducing a source noise signal in a power supply signal of the duty ratio adjusting circuit through a power supply noise introducing sub-branch;

The synthesizing of the new control signal by using the voltage noise signal and the control signal of the duty ratio adjusting circuit includes: and synthesizing a new control source signal by adopting a source noise signal in the power supply signal and the control signal of the duty ratio adjusting circuit.

Optionally, the method further comprises: and adjusting the duty ratio of the output clock signal according to the new control signal through the control branch circuit to obtain an adjusted output clock signal.

The embodiment of the invention has the following advantages:

the duty ratio adjusting circuit in the embodiment of the invention has the advantages of small area, low power consumption, high noise resistance and the like, and can give consideration to the performance indexes of high performance, low area, low power consumption and high noise resistance, thereby overcoming the defect that the existing analog DCC and digital DCC can not give consideration to both the area and the noise resistance.

Drawings

FIG. 1 is a schematic diagram of a duty cycle adjusting circuit according to the present invention;

FIG. 2 is a schematic diagram of a noise introducing sub-branch in connection with a control branch in accordance with an alternative embodiment of the present invention;

FIG. 3 is a flowchart illustrating the steps of one embodiment of a noise immunity method for a duty cycle adjustment circuit of the present invention;

FIG. 4 is a schematic diagram of a ground noise introducing sub-branch in connection with a control branch in accordance with an example of the present invention;

FIG. 5 is a schematic diagram of a power supply noise injection sub-branch and control branch connection in accordance with an exemplary embodiment of the present invention;

fig. 6 is a schematic diagram of a duty cycle adjusting circuit according to an example of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

With the continuous enhancement of data processing capacity of an electronic system, in order to transmit data efficiently, the duty ratio of a clock signal needs to be strictly controlled to be about 50%, so that a rising edge and a falling edge have equal and symmetrical phase margins to sample data, and the accuracy of the data is ensured. However, even if the clock signal is input to the electronic system at a duty ratio of 50%, the transmitted clock signal is distorted by mismatch, signal coupling, and process drift, and is severely deviated from the duty ratio of 50%. Therefore, the electronic system needs a special circuit, namely a duty ratio adjusting circuit, to adjust the duty ratio of the clock signal and ensure that the clock signal is in a 50% duty ratio state. In addition, as the area of electronic systems is continuously reduced, stringent requirements are placed on the area of the duty cycle adjusting circuit.

At present, although a digital duty ratio adjusting circuit realized by a digital method can keep the performance and simultaneously has the function of resisting power supply and ground noise, the digital duty ratio adjusting circuit needs to occupy a larger area and is difficult to integrate in a system with strict area requirements. The existing analog duty ratio adjusting circuit realized by adopting an analog method can keep the performance and simultaneously consider a smaller area, but the application of the analog duty ratio adjusting circuit is severely limited by the high sensitivity to the noise of a power supply signal and a ground signal. For example, in a system with a complex circuit environment and mixed signals, that is, in a situation where it is not guaranteed that the power signal and the ground signal are very clean, the conventional analog duty ratio adjusting circuit cannot be applied. Therefore, in the case of ensuring that the DCC area is small, how to overcome the noise of the power signal and the ground signal in the system becomes a particularly critical issue.

One of the core ideas of the embodiments of the present invention is to provide a new duty ratio adjusting circuit, which can reduce the influence of noise by introducing the noise in the voltage signal to cancel the noise of the power signal and the ground signal.

Referring to fig. 1, a schematic diagram of a duty cycle adjusting circuit according to the present invention is shown.

in an embodiment of the present invention, the duty ratio adjusting circuit may include: a noise introducing branch 110 and a control branch 120, and the noise introducing branch 110 is connected with the control branch 120. The noise introducing branch circuit 110 is configured to introduce a voltage noise signal of the duty ratio adjusting circuit, synthesize the voltage noise signal and a control signal Vctrl of the duty ratio adjusting circuit to form a new control signal, and transmit the new control signal to the control branch circuit 120. The control branch circuit 120 is configured to adjust the duty ratio of the output clock signal of the duty ratio adjustment circuit according to the new control signal.

It should be noted that the voltage noise signal may be used to characterize noise in the voltage signal of the duty ratio adjustment circuit, and may include a source noise signal in the power supply signal, a ground noise signal in the ground signal, and the like. The source noise signal may be used to characterize the source noise in the power signal and the ground noise signal may be used to characterize the ground noise in the ground signal. The control signal Vctrl of the duty ratio adjusting circuit may be used to control the duty ratio state of the clock signal, so as to ensure that the clock signal is in a preset duty ratio state.

In the embodiment of the present invention, the new control signal carries the voltage noise signal introduced through the noise introducing branch 110. In the process that the control branch 120 controls the input clock signal according to the new control signal, the voltage noise signal carried in the new control signal can be cancelled out with the voltage noise signal in the voltage signal connected to the control branch 120, so as to achieve the purpose of canceling out noise, so that the control branch is not affected by the voltage noise signal, and the working state of the control stage is stabilized.

In an alternative embodiment of the present invention, the noise introducing branch 110 may include at least one noise introducing sub-branch, that is, may include one or more noise introducing sub-branch noises, and the number of the noise introducing sub-branches is not particularly limited by the embodiment of the present invention.

referring to fig. 2, a schematic diagram of a connection between a noise introducing sub-branch and a control branch according to an alternative embodiment of the present invention is shown.

In an embodiment of the present invention, the noise introducing sub-branch 210 may include a first transistor 211 and a second transistor 212. The first transistor 211 is connected to a first terminal of the second transistor 212, and the first terminal of the second transistor 212 may be connected to the control branch 220. The first transistor 211 may be configured to introduce a voltage noise signal of the duty ratio adjustment circuit into the second transistor 212 through a first terminal of the second transistor 212; the second transistor 212 may be configured to receive the control signal Vctrl of the duty ratio adjustment circuit, synthesize a new control signal from the control signal and the voltage noise signal, and provide the new control signal to the control branch 220, so that the control branch 220 may control the input clock signal of the duty ratio adjustment circuit according to the new control signal, so as to ensure that the clock signal is in a preset duty ratio state, for example, ensure that the clock signal is in a 50% duty ratio state.

In a specific implementation, the first transistor may be a field effect transistor or a triode; the second transistor may also be a field effect transistor or a triode, which is not particularly limited in the embodiments of the present invention. For example, when the second transistor is a field effect transistor, the first terminal of the second transistor may be a source terminal of the field effect transistor. For another example, when the second transistor is a triode, the first terminal of the second transistor may be an emitter of the triode, and so on.

As an example of the present invention, when the first transistor and the second transistor are field effect transistors, a source terminal of the first transistor may be connected to a source terminal of the second transistor, and the second transistor may be connected to a control branch of the duty ratio adjustment circuit. The first transistor may be configured to introduce the voltage noise signal of the duty ratio adjustment circuit to a source terminal of the second transistor, that is, the first transistor may be connected to the voltage signal of the duty ratio adjustment circuit to introduce the voltage noise signal in the voltage signal to the source terminal of the second transistor. The second transistor may be configured to transmit a control signal Vctrl of the duty ratio adjustment circuit to a source end of the second transistor, so that the control signal and the voltage noise signal are synthesized into a new control signal, and the new control signal may be provided to the control branch. Specifically, the gate terminal of the second transistor may be connected to a control signal of the duty ratio adjustment circuit, so that the control signal may be introduced to the source terminal of the second transistor, and the control signal may be superimposed with the voltage noise signal to synthesize a new control signal, and then the new control signal may be provided to the control branch for use, so that the control branch may control the input clock signal of the duty ratio adjustment circuit according to the new control signal, and ensure that the duty ratio of the clock signal is 50%.

Referring to fig. 3, a flowchart illustrating steps of an embodiment of an anti-noise method for a duty ratio adjustment circuit according to the present invention is shown, which may specifically include the following steps:

step 301, introducing a voltage noise signal of a duty ratio adjusting circuit through a noise introducing branch of the duty ratio adjusting circuit.

and step 302, synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit.

Step 303, providing the new control signal to the control branch of the duty ratio adjusting circuit.

And the control branch circuit is used for adjusting the duty ratio of an output clock signal of the duty ratio adjusting circuit according to the new control signal.

In summary, the duty ratio adjusting circuit in the embodiment of the present invention may introduce the voltage signal noise through the noise introducing branch, so that the introduced voltage signal noise may be synthesized with the control signal of the duty ratio adjusting circuit to obtain a new control signal, and then the new control signal may be raised and supplied to the control branch, and the new control signal carries the introduced voltage noise signal, and further the voltage noise signal carried in the new control signal may be adopted to cancel the noise signal in the voltage signal connected to the control branch, so as to achieve the purpose of canceling the noise, so that the control branch is not affected by the noise in the voltage signal connected to the control branch, and the problem of poor noise immunity of the duty ratio adjusting circuit in the prior art is solved.

in a specific implementation, the duty ratio adjusting circuit provided by the embodiment of the invention can be implemented by using an analog method to reduce the area of the duty ratio adjusting circuit, so that the duty ratio adjusting circuit can be integrated in a system with strict area requirements, such as an SOC system. Optionally, the noise introducing branch of the duty cycle adjusting circuit may comprise one or more noise introducing sub-branches. The noise introducing sub-branch may be divided into a ground noise introducing sub-branch and a power noise introducing sub-branch. The ground noise introducing sub-branch can be used for introducing ground noise in the ground signal, so that the control branch can cancel the noise in the ground signal connected with the control branch by adopting the introduced ground noise, and the purpose of canceling the ground noise is achieved. The power supply noise introducing sub-branch can be used for introducing source noise in the power supply signal, so that the control branch can adopt the introduced source noise to counteract the source noise in the power supply signal connected with the control branch, and the purpose of counteracting the source noise is achieved.

In an optional embodiment of the present invention, the above-mentioned introducing the voltage noise signal of the duty ratio adjusting circuit through the noise introducing branch of the duty ratio adjusting circuit may include: and introducing a ground noise signal in the ground signal of the duty ratio adjusting circuit through a ground noise introducing sub-branch. The synthesizing a new control signal by using the voltage noise signal and the control signal of the duty ratio adjusting circuit may include: and synthesizing a new control ground signal by adopting a ground noise signal in the ground signal and the control signal of the duty ratio adjusting circuit. Therefore, the control branch can cancel the ground noise signal carried in the new control ground signal and the ground noise signal in the ground signal, so as to realize the cancellation of the ground noise. In the embodiment of the present invention, the new control signal is the above-mentioned new control ground signal.

in a specific implementation, the control branch may include a third transistor, where the third transistor is used to connect a ground signal of the duty ratio adjustment circuit, so that the duty ratio adjustment circuit may connect the ground signal through the third transistor of the control branch, so as to control the input clock signal according to a control voltage generated by the connected ground signal, thereby implementing adjustment of the duty ratio of the clock signal.

In an embodiment of the present invention, the noise introducing sub-branch may include a ground noise introducing sub-branch, and the ground noise introducing sub-branch includes a first transistor and a second transistor. The first transistor in the ground noise introducing sub-branch is used for connecting the ground signal and introducing the ground noise signal in the ground signal to the first end of the second transistor in the ground noise introducing sub-branch; the first end of the second transistor in the ground noise introducing sub-branch is connected with the third transistor, so that the ground noise signal carried in the new control signal and the ground noise signal in the ground signal voltage are mutually offset to stabilize the working state of the third transistor.

for example, when the first transistor, the second transistor and the third transistor in the control branch of the ground noise introducing sub-branch are all field effect transistors, the first transistor and the second transistor of the ground noise introducing sub-branch may be connected as shown in fig. 4, the drain terminal of the first transistor 411 of the ground noise introducing sub-branch 410 may be directly connected to the ground signal Vss of the duty ratio adjusting circuit, and the gate terminal of the first transistor 411 may be connected to the ground signal through a resistor R, so that the ground noise signal in the ground signal Vss may be introduced to the source terminal of the second transistor 412 of the ground noise introducing sub-branch 410. The gate terminal of the second transistor 412 of the ground noise introducing sub-branch 410 may be connected to the control signal Vctrl of the duty ratio adjusting circuit, so that the control signal Vctrl may be introduced to the source terminal of the second transistor 412 of the ground noise introducing sub-branch 410, so that the control signal Vctrl may be synthesized with the ground noise signal introduced by the first transistor 411 to obtain a new control ground signal, and then the new control ground signal is transmitted to the gate terminal of the third transistor 421 of the control branch 420, so as to cancel the noise on the gate-source voltage on the third transistor 421, that is, cancel the ground noise, so that the gate-source voltage Vgs of the third transistor 421 is not affected by the ground noise, and the purpose of stabilizing the operating state of the control stage of the control branch 420 is achieved. It should be noted that the control branch 420 may control the input clock signal Ckin according to a new control ground signal. The drain of the second transistor 412 may be connected to a high level signal, such as a high level signal of a direct current, or may be connected to a power signal of the space ratio adjusting circuit, so that the second transistor 412 may be turned on when the control signal Vctrl is a low level signal, and further the control signal Vctrl may be transmitted to the source of the second transistor 412 to be synthesized with the ground noise signal introduced by the first transistor 411.

The ground noise introducing sub-branch 410 may or may not have a resistor R, and whether the resistor R is set may be determined by the characteristics of the first transistor 411; that is, when the first transistor 411 is a transistor capable of directly connecting a ground signal, a ground signal may be directly connected to the gate terminal of the first transistor 411, and when the first transistor 411 is a transistor incapable of directly connecting a power supply signal, a resistor R needs to be provided between the ground signal and the gate terminal of the first transistor 411.

In an optional implementation manner, the first transistor in the ground noise introducing sub-branch may be a P-Channel Metal Oxide Semiconductor (PMOS) transistor, and the third transistor and the second transistor in the ground noise introducing sub-branch are both N-type Metal-Oxide-Semiconductor (NMOS) transistors. Of course, the first transistor, the second transistor in the ground noise introducing sub-branch or the third transistor in the control branch may also be a triode; besides, the first transistor, the second transistor, or the third transistor in the control branch of the ground noise introducing sub-branch may also be a junction field effect transistor, which is not particularly limited in the embodiment of the present invention.

in the embodiment of the present invention, optionally, the introducing, by the noise introducing branch of the duty ratio adjusting circuit, the voltage noise signal of the duty ratio adjusting circuit may include: and introducing a source noise signal in the power supply signal of the duty ratio adjusting circuit through the power supply noise introducing sub-branch. The synthesizing a new control signal by using the voltage noise signal and the control signal of the duty ratio adjusting circuit may include: and synthesizing a new control source signal by adopting a source noise signal in the power supply signal and the control signal of the duty ratio adjusting circuit. Therefore, the control instruction can offset the source noise signal carried in the new control source signal and the source noise signal in the power supply signal, so as to offset the source noise. In the embodiment of the present invention, the new control signal is the new control source signal.

In a specific implementation, the control branch may include a fourth transistor, and the fourth transistor is configured to be connected to the power supply signal of the duty ratio adjustment circuit, so that the duty ratio adjustment circuit may connect the power supply signal through the fourth transistor of the control branch, so as to control the input clock signal according to a control voltage generated by the connected power supply signal, and implement adjustment of the duty ratio of the clock signal.

The noise introducing branch comprises a power supply noise introducing sub-branch, and the power supply noise introducing sub-branch comprises a first transistor and a second transistor; and the first transistor in the power supply noise introducing sub-branch is used for connecting the power supply signal and introducing the source noise signal in the power supply signal to the first end of the second transistor in the power supply noise introducing sub-branch. The first end of the second transistor in the power supply noise introducing sub-branch is connected with the fourth transistor, so that a source noise signal carried in a new control source signal and a source noise signal in the power supply signal are mutually offset, and the working state of the fourth transistor is stabilized.

For example, when the fourth transistor, the first transistor and the second transistor of the power noise introducing sub-branch are both triodes, the first transistor and the second transistor of the power noise introducing sub-branch may be connected as shown in fig. 5, the collector of the first transistor 511 of the power noise introducing sub-branch 510 may be directly connected to the power signal Vdd of the duty ratio adjusting circuit, and the base of the first transistor 511 may be connected to the power signal Vdd through a resistor R1, so that the source noise signal in the power signal Vdd may be introduced to the emitter of the second transistor 512 of the power noise introducing sub-branch 510. The base of the second transistor 512 of the power noise introducing sub-branch 510 may be connected to the control signal Vctrl of the duty ratio adjusting circuit, so that the control signal Vctrl may be introduced to the emitter of the second transistor 512 of the power noise introducing sub-branch 510, so that the control signal Vctrl may be synthesized with the source noise signal introduced by the first transistor 512 to obtain a new control source signal, and then the new control source signal may be transmitted to the base of the fourth transistor 521 of the control branch 520 to cancel the source noise on the fourth transistor 521, so that the fourth transistor 521 is not affected by the source noise, and the purpose of stabilizing the working state of the control stage of the control branch 520 is achieved. It should be noted that the control branch 520 may control the input clock signal Ckin according to a new control source signal. The collector of the second transistor 512 may be connected to a low level signal, such as a low level signal of a direct current, or may be connected to a ground signal of the duty ratio adjusting circuit, so that the second transistor 512 may be turned on when the control signal Vctrl is a high level signal, and further the control signal Vctrl may be transmitted to the emitter of the second transistor 512 to be synthesized with the source noise signal introduced by the first transistor 511.

The power noise introducing sub-branch 510 may be provided with the resistor R1, or may not be provided with the resistor R1, and whether the resistor R1 is provided is determined by the characteristics of the first transistor 511; that is, when the first transistor 511 is a transistor capable of directly connecting a power supply signal, the power supply can be directly connected to the base of the first transistor 511, and when the first transistor 511 is a transistor incapable of directly connecting a power supply signal, the resistor R1 needs to be provided between the power supply and the base of the first transistor 511.

In an optional embodiment of the present invention, the fourth transistor, the first transistor in the power supply noise introducing sub-branch, and the second transistor may all be field effect transistors, for example, the first transistor in the power supply noise introducing sub-branch may be an NMOS transistor, and the third transistor and the second transistor in the ground noise introducing sub-branch may all be PMOS transistors; besides, the first transistor, the second transistor, or the third transistor in the control branch of the ground noise introducing sub-branch may also be a junction field effect transistor, which is not particularly limited in the embodiment of the present invention.

In the embodiment of the present invention, optionally, the duty ratio adjusting circuit may further include: the device comprises a buffer module and a detection module. One end of the buffer module is connected with the control branch circuit, and the other end of the buffer module is connected with the detection module, so that the detection module generates a control signal of the duty ratio adjusting circuit according to an output clock signal of the control branch circuit.

In order that those skilled in the art will better understand the embodiments of the present invention, the following description is given by way of example:

as an example of the present invention, the duty cycle adjusting circuit may include a power supply noise introducing sub-branch 610, a ground noise introducing sub-branch 620, a control branch 630, a buffer module 640, and a detection module 650, as shown in fig. 6. The Buffer module 640 may include one or more buffers, such as a Buffer Chain (Buffer Chain) composed of three buffers connected in sequence.

in this example, the first transistor M1 and the second transistor M2 of the power noise introducing sub-branch 610 may be used to introduce noise of the power signal, and the first transistor M7 and the second transistor M8 of the ground noise introducing sub-branch 620 may be used to introduce noise of the ground signal, so as to cancel the noise.

specifically, the drain terminal of the first transistor M1 in the power noise introducing sub-branch 610 may be connected to the power signal Vdd, and the gate terminal of the first transistor M1 may be connected to the power signal Vdd through the resistor R1, so that the first transistor M1 may introduce the source noise signal to the source terminal of the second transistor M2 in the power noise introducing sub-branch 610. The second transistor M2 may introduce the control signal Vctrl output by the detection module 650 into the source end of the second transistor M2, so that the control signal Vctrl and the introduced source noise signal may be synthesized into a new control source signal, and the new control source signal is transmitted to the gate end of the fourth transistor M4 of the control branch 630, so as to achieve noise cancellation on the source noise signal and the gate-source voltage on the fourth transistor M4, that is, cancel the source noise, so that the gate-source voltage Vgs of the fourth transistor M4 is not affected by the source noise, and the purpose of stabilizing the working state is achieved.

Likewise, the drain terminal of the first transistor M7 in the ground noise introducing sub-branch 620 may be connected to the ground signal Vss, and the gate terminal of the first transistor M7 may be connected to the ground signal Vss through the resistor R2, so that the first transistor M7 may introduce the ground noise signal to the source terminal of the second transistor M8 in the ground noise introducing sub-branch 620. The second transistor M8 may introduce the control signal Vctrl output by the detection module 650 into the source end of the second transistor M8, so that the control signal Vctrl and the introduced ground noise signal are synthesized into a new control ground signal, and the new control ground signal is transmitted to the gate end of the third transistor M3 of the control branch 630, so as to cancel the ground noise signal and the noise on the gate-source voltage on the third transistor M3, that is, cancel the ground noise, so that the gate-source voltage Vgs of the third transistor M3 is not affected by the ground noise, and the purpose of stabilizing the working state is achieved.

therefore, in the example, the control voltage Vctrl can be introduced and the source noise and/or the ground noise can be introduced at the same time by adding the noise introducing branch composed of the field effect transistor, so that the purpose of offsetting the source noise and/or the ground noise is achieved, and the problem that the existing analog DCC is small in area but poor in noise resistance is solved.

In a particular implementation, the duty cycle adjustment circuit may be configured to process the interface clock signal such that the interface clock signal maintains a 50% duty cycle. Of course, the duty ratio adjusting circuit may also be used to generate an interface clock signal, and the like, which is not limited in this embodiment of the present invention.

for example, in the case that the duty ratio adjusting circuit is used for processing the interface clock signal, the duty ratio adjusting circuit may control the input clock signal according to the control voltage, that is, adjust the duty ratio of the output clock signal of the duty ratio adjusting circuit to correct the duty ratio of the output clock signal to be 50%.

In an optional embodiment of the present invention, the noise immunity method of the duty ratio adjustment circuit may further include: and adjusting the duty ratio of the output clock signal according to the new control signal through the control branch circuit to obtain an adjusted output clock signal. For example, in combination with the above example, as shown in fig. 6, the control branch 630 may control the input clock signal Ckin according to a new control voltage to control the charging and discharging rates of the fifth transistor M5 and the sixth transistor M6, that is, adjust the duty ratio of the output clock signal according to the new control voltage, so that the rising/falling time of the output waveform relative to the input waveform changes, thereby achieving the purpose of adjusting the duty ratio of the output clock signal. The output waveform may be a waveform of the output clock signal, and the input waveform may be a waveform of the input clock signal. Alternatively, the fifth transistor M5 may be a PMOS transistor, and the sixth transistor M6 may be an NMOS transistor.

In the embodiment of the present invention, the duty ratio adjusting circuit may adjust the duty ratio according to a ratio of 1: the ratio of 1 is to introduce the source noise and the ground noise into the gate end of the device directly contacting the source noise and the ground noise, namely to introduce the ground noise signal into the gate end of the third transistor under the condition of keeping the ground noise original value, and to introduce the source noise signal into the gate end of the fourth transistor under the condition of keeping the source noise original value, so as to realize the noise cancellation at the two ends of the gate source of the device contacting the noise, so that the noise does not influence the gate-source voltage Vgs of the device, and the purpose of stabilizing the working state of the device is achieved. In addition, the duty ratio adjusting circuit can simultaneously complete the reasonable superposition of the source noise signal to be offset and the ground noise signal and the control signal, generate a new control signal, enable the new control signal to carry the noise control device to be offset, and simultaneously complete the noise offset on the device, thereby enabling the device to work in a stable working state and simultaneously keeping the original control capability of the control signal. Therefore, the embodiment of the invention solves the problem that the existing high-performance analog DCC is sensitive to power supply and ground noise, and achieves the purpose of inhibiting the influence of the power supply and ground noise on the duty ratio adjustment result.

In summary, the duty ratio adjusting circuit of the embodiment of the invention has the advantages of small area, low power consumption and high noise immunity, i.e. the performance indexes of high performance, low area, low power consumption and high noise immunity can be considered, and the defect that the existing analog DCC and digital DCC can not consider both area and noise immunity is overcome.

it should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

the embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a predictive manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

while preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The duty ratio adjusting circuit and the noise-proof method of the duty ratio adjusting circuit provided by the invention are introduced in detail, and a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the above embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.