阅读说明：本技术 一种结合子图同构的量子线路程序通用变换方法 (Quantum line program universal conversion method combined with subgraph isomorphism ) 是由 张昱 陈铭瑜 李永尚 于 2021-07-29 设计创作，主要内容包括：本发明提出一种结合子图同构的量子线路程序通用变换方法,将量子线路表示成顶点为单量子门或双量子门、边为弧尾结点依赖的量子比特信息的DAG；并在这种DAG上提出子图同构的QVF算法解决线路的模式匹配问题,并基于线路匹配信息设计子图替换算法。本发明还引入量子线路等价关系的模式描述格式,并定义通用模式和合并模式两种具体模式类别及其描述格式,使得重写方法能够处理诸如线路优化、线路转换等重写问题。在IBM和ScaffCC提供的量子测试程序集上的实验表明,本发明的方法实现的连续单量子门优化能够对量子程序规模提供10％的优化率。(The invention provides a quantum circuit program general transformation method combined with subgraph isomorphism, which expresses a quantum circuit as DAG with the vertex of single quantum gate or double quantum gate and the edge of quantum bit information depending on an arc tail node; and a QVF algorithm of sub-graph isomorphism is provided on the DAG to solve the problem of pattern matching of the lines, and a sub-graph replacement algorithm is designed based on the line matching information. The invention also introduces a mode description format of quantum line equivalence relation, and defines two specific mode categories of a general mode and a merging mode and description formats thereof, so that the rewriting method can process rewriting problems such as line optimization, line conversion and the like. Experiments on the quantum test suite provided by IBM and ScaffCC show that the continuous single quantum gate optimization achieved by the method of the present invention can provide 10% optimization rate on quantum program scale.)

1. A method for program universal transformation of quantum wires combining subgraph isomorphism, comprising the steps of:

step 1, inputting a quantum program, and converting quantum circuits into directed acyclic graph DAG representation based on a circuit model;

step 2, the mode scheduler judges, if the user does not assign a scheduling rule to the mode scheduler, the mode is selected randomly from the mode library directly; if the mode scheduler has a rule specified by a user, selecting a mode according to the specified rule; if the pattern library is empty, the algorithm terminates;

step 3, the mode scheduler selects proper routines to execute processing according to the type of the mode; specifically, if the mode is the general mode, step 4 is executed; if the mode is the merging mode, executing the step 5;

step 4, executing a general mode which comprises a sub-circuit to be searched and a sub-circuit for replacement, wherein the sub-circuit and the sub-circuit have fixed structures; after the completion, returning to the step 2;

and 5, executing the merging mode, finding out the single quantum gate specified by the continuous merging mode, processing by the processing function specified by the merging mode, and returning to the step 2 after the processing is finished.

2. The method for procedural universal transformation of quantum wires with subgraph isomorphism according to claim 1, wherein in step 1, the conversion of quantum wires into DAG representation means that quantum wires are represented as DAG with single-quantum gate or double-quantum gate vertex and arc tail node dependent quantum bit information on edge; the DAG representation of the quantum wire is defined as follows:

define a DAG representation of 1 quantum wire: the DAG representation of a quantum line is defined as a triplet G ═<q，V，E>Where Q ═ {0, 1, 2. } contains the qubit index value on which the quantum wire acts, V and E represent the vertex set and the edge set in the DAG, respectively; each vertex V ═ V (op, qlist, angle) e V in the DAG corresponds to a gate in the quantum line, where op represents the gate operation type, qlist and angle storing the quantum bit parameters and the rotation angles that may exist; each side e ═ e: (<v_i，v_j>Q) E E represents the gate v_iTo v_jQubit dependency relationship between, i.e. gate v_jDependent on door v_iThe acted qubit q ∈ q state and q satisfies q ∈ v_iQlist and q ∈ v_j.qlist。

3. The method of claim 1, wherein the quantum wire program general transformation method is combined with sub-graph isomorphism,

in step 4, a general pattern is executed, where the general pattern includes a sub-line to be searched and a sub-line for replacement, and both have a fixed structure, and the general pattern specifically includes:

step 4.1, giving DAG representation of the original line and the mode line, and executing a QVF quantum line mode matching algorithm;

step 4.2, outputting an isomorphic mapping list as a matching line context after matching;

step 4.3, given the DAG representation of the original line and the replacement sub-line, a sub-graph replacement algorithm is performed in conjunction with the match line context in step 4.2.

4. The method as claimed in claim 1, wherein in step 3, the basis is used in the procedure of transforming quantum wires with subgraph isomorphismDefining description formats of a general mode and a merging mode in a JSON file, wherein the general mode comprises a mode line and a substitute line which are respectively marked as C_pAnd C_s(ii) a The mode wire describes what wire is replaced, and the alternate wire describes what wire should be used to replace the mode wire.

5. A method of generic transformation of quantum wire programs in conjunction with subgraph isomorphism according to claim 1, characterized in that the description format of the generic model comprises three parts: "qubits", "src", and "dst", where the term "qubits" describes the mode line C_PThe maximum qubit number used in "src" and "dst" terms are used to describe the source, i.e., mode, and destination, i.e., alternate, lines of the conversion relationship.

6. A method of program generic transformation of quantum wires in conjunction with subgraph isomorphism, as per claim 3, characterized in that said step 4.1, given the DAG representation of the original wires and pattern wires, performs a QVF quantum wire pattern matching algorithm, comprising in particular the steps of:

1) initializing isomorphic mapping listsIs empty, state queueWhereinIt is referred to as an empty set,for only one isomorphic mapping M stored in the initial state queue<M₁，M₂>Its structure maps M₁And semantic mapping M₂All are empty sets; and initializing a structure map for temporary storage of the current stateM of (A)_strAnd semantically mapped M_sem；

2) If Q is_sIf the program is empty, the program is terminated, otherwise the program continues to be executed;

3) from Q_sGet out of isomorphic mapping of queue head M ═<M₁，M₂>And perform value assignment<M_str，M_sem>M, which is then queued from state queue Q_sDeleting;

4) if the current structure maps M_strCovered the mode line G_pAll vertices in (D), in other words dom (M)_str)＝G_pV, then add the current isomorphic mapping to the listMedium, and return to 2);

5) mapping M according to the current structure_strOriginal line G_oAnd mode line G_pCalculating a current candidate ordered point pair set P;

6) traversing each point pair P in the set P, and executing:

6.1) execution of FeasibilityRules (M)_str，M_semP) function, judging the structure mapping M after adding the point pair p_strWhether vertex isomorphic conditions are satisfied and modify semantic mapping M_semIs M'_semTo make it conform to the new vertex mapping relation; if such M 'is present'_sem6.2) is executed, otherwise, the next point pair p is taken out, and 6.1) is executed again;

6.2) new isomorphic mapping M ═<M_str∪p，M′_sem>Add to queue Q_sTaking out the next point pair p, and returning to 6.1);

7) return 2).

7. The method of claim 3, wherein the step 4.3 of performing the subgraph replacement algorithm comprises the following steps:

1) initializing a line sub-graph representation G_r＝G_o；

2) Traversing a mapping listFrom which an isomorphic mapping M is taken<M_str，M_sem>If the mapping list is presentNull, return the final DAG graph G_rAnd ending the algorithm;

3) using M_strDetermining a matching sub-graph g in the original graph by using the vertex information contained in the graph, and utilizing M_semInclusion mapping instantiation schema wire G_s；

4) Determining a mode line G_sSet S consisting of the first and last corresponding vertices of the quantum gate acting on a qubit_inAnd S_out；

5) Determining a set T of vertices into and out of a matching subgraph g_inAnd T_out；

6) Matching sub graph G and the edge connecting the top point and the rest part are driven from G_rDeleting and removing G_sIs added to G_rIn this case G_rFrom the excised remainder and instantiated G_sThe two are not connected with each other;

7) for each qubit q e g.Q contained in the matching subgraph g, the following steps are performed:

7.1) by using M_semFind each qubit at G_pCorresponding qubit index

7.2) depending on whether q' is at G_sThe method is divided into two cases:

i. if q'. epsilon.G_sQ, description of S_in[q′]And S_out[q′](ii) present; if T is_in[q]If present, go to G_rAdding a new edge (T)_in[q]，S_in[q′]) (ii) a If T is_out[q]Exist to G_rAdding a new edge (S)_out[q′]，T_out[q])；

ii ifIf T is_in[q]And T_out[q]At the same time, to G_rAdding a new edge (T)_in[q]，T_out[q])；

7.3) if existing, taking out the next qubit q in g, returning to 7.1), otherwise, executing 8);

8) back to 2).

8. The method of claim 6, wherein the original graph, the pattern graph, and the substitution graph are used to refer to DAG representations of the original line, the pattern line, and the substitution line, respectively, and are denoted as G_o，G_pAnd G_s(ii) a The isomorphic conditions are defined as follows 2:

the sub-graph isomorphism condition for a 2-quantum wire is defined as: representing G for two given quantum-line DAGs_p、G_sFrom G_pTo mapping M ═ M<M_str，M_sem>Represents a possible isomorphic relationship when M is mapped to a structure_str，(n，m)∈M_str，n∈G_p.V，m∈G_sV satisfies the following vertex isomorphism condition:

i.n.op＝m.op；

ii.|n.qlist|＝|m.qlist|；

iii.|n.angle|＝|m.angle|；

n.angle [ i ] is the same complex constant as m.angle [ i ] for each i, or at most one is a variable;

at the same time, M is mapped to semantics_semEach side pair (e)_s，e_d)∈M_semThe following edge isomorphism conditions are satisfied:

i.e_s＝(<n₁，n₂>，q₁)∈G_p.E；

ii.e_d＝(<m₁，m₂>，q₂)∈G_o.E；

iii.(n₁，m₁)∈M_str，(n₂，m₂)∈M_str；

further, for each qubit pair (q)₁，q₂)∈M_sem，q₁，q₂Should have the same qubit type.

Technical Field

The invention relates to the field of quantum computation, line optimization and mode matching, in particular to a quantum line program universal transformation method combining subgraph isomorphism.

Background

The quantum computation is a novel computation mode for regulating quantum equipment to perform computation according to the law of quantum mechanics. Quantum computing exhibits different possibilities compared to classical computing. For example, the Shor algorithm in the quantum algorithm has exponential acceleration compared with the classical large number decomposition algorithm, and the Grover algorithm provides square acceleration for the classical database lookup algorithm.

In quantum computing, the basic unit of storage and operation is a qubit. Similar to the classical bit, a qubit has two ground states, |0> and |1 >; however, the qubits can also be in a superposition state, which is any linear combination of the two states:

wherein each of α and β is |0>Sum of states |1>Complex amplitude corresponding to state satisfying | alpha uti²+|β|²＝1。

The basic operations that act on qubits are called quantum gates, and fig. 1 shows symbolic representations and matrix representations of some basic single quantum gates (acting on single-quantum bits, such as H, X, Y, Z, P) and one commonly used double quantum gate (acting on double-quantum bits, such as CNOT gates). All these gates can describe their mathematical semantics with a unitary matrix U and satisfy(whereinIs the conjugate transpose of U and I is the identity matrix). Quantum gate g_AAnd g_BSatisfy the relationship of the pairs and only if their matrix represents M_AAnd M_BReciprocal, i.e. M_AM_B＝M_BM_A。

Quantum wires are a common abstract model for quantum programs. It consists of a series of quantum gates acting on a set of qubits, as in fig. 2 (a). In this model, each qubit is represented by a horizontal line, and the quantum gates are represented by the box symbols shown in FIG. 1; the flow direction of time is from left to right, so the qubits are acted upon sequentially by the qubits from left to right. Another common abstraction model is the DAG (directed acyclic graph) representation of quantum programs. Compared to quantum wires, it emphasizes the dependence between quantum gates on qubits. The DAG structure used in the quantum mapping algorithm ignores the information of the single quantum gates, as shown in fig. 2(b), because the execution of the single quantum gates does not introduce dependencies between the qubits. However, in the present invention, as shown in fig. 2(c), the information of the single quantum gate is retained in the DAG to perform the quantum circuit subgraph matching process (the definition of the DAG of the present invention is detailed in the summary of the invention).

Although quantum computing has been developed in recent years to be new, the difference between software and hardware in quantum computing is exposed in the process;

1) logic and physical gates: the quantum gates used in quantum programs are commonly referred to as logic gates. Unlike physical gates supported by quantum hardware, logic gates are often richer and often expanded in pursuit of program expressive power and good readability. Similar to the Instruction Set (ISA) in classical computing, the class of physical gates is limited by the physical nature of the device, often hardware-dependent, fixed, and limited. For example, for the two major classes of programmable quantum physical systems today, the dual quantum gates supported on superconducting systems are often CNOT gates, while the XX gates supported on ion trap systems.

2) Influence of noise on the quantum program: noise is one of the key factors that affect the quantum circuit execution. The interaction of the qubit with the surrounding environment inevitably introduces noise such as decoherence, which causes the quantum states (especially |1> states) to be distorted exponentially over time, with a consequent reduction in the fidelity of the quantum program execution. The coherence duration of each qubit is very short, e.g. up to 100 mus in superconducting systems. Therefore, most of the quantum algorithms which can be realized by the quantum device at present are shallow layer algorithms (the depth of a quantum line is smaller so as to reduce the time requirement for maintaining quantum states of quantum bits), and the larger-scale quantum algorithms need to be realized through quantum-classical mixing.

The above problems are the problems that the quantum program compiling needs to solve urgently. The differences between program execution abstraction layers and between different physical architectures result in quantum programs that must undergo appropriate transformations before execution. The presence of noise enables line optimization to improve the fidelity of program execution by reducing the line size, while reducing the line run time. The transformation and optimization behavior for quantum wires is collectively referred to as the rewriting operation of the quantum wires.

Disclosure of Invention

In the quantum program compiling process, in order to solve the problems of the difference between a quantum computing platform and a quantum program execution abstraction layer, the reduction of the quantum program execution fidelity caused by noise and the like, the quantum program must be properly converted. Aiming at quantum circuit equivalent transformation, the invention provides a quantum circuit program general transformation method combined with subgraph isomorphism, which is a rewriting method in essence, and expresses a quantum circuit as DAG with vertex being single quantum gate or double quantum gate and edge being quantum bit information dependent on arc tail node; and a QVF algorithm of sub-graph isomorphism is provided on the DAG to solve the problem of pattern matching of the lines, and a sub-graph replacement algorithm is designed based on the line matching information. In order to expand the processing range of the rewriting method, the invention also introduces a mode description format of quantum line equivalence relation, and defines JSON description formats of two specific mode categories of a general mode and a merging mode, so that the rewriting method can process the rewriting problems such as line optimization, line conversion and the like. Experimental results on the quantum test suite provided by IBM and ScaffCC show that the framework enables continuous single quantum gate optimization (in merge mode) that can provide 10% optimization rate on quantum program scale.

The technical scheme of the invention is as follows: a general transformation method for quantum wire program combined with subgraph isomorphism comprises the following steps:

step 1, inputting a quantum program, and converting quantum circuits into Directed Acyclic Graphs (DAG) representation based on a circuit model;

step 2, the mode scheduler judges, if the user does not assign a scheduling rule to the mode scheduler, the mode is selected randomly from the mode library directly; if the mode scheduler has a rule specified by a user, selecting a mode according to the specified rule; if the pattern library is empty, the algorithm terminates;

step 3, the mode scheduler selects proper routines to execute processing according to the type of the mode; specifically, if the mode is the general mode, step 4 is executed; if the mode is the merging mode, executing the step 5;

step 4, executing a general mode which comprises a sub-circuit to be searched and a sub-circuit for replacement, wherein the sub-circuit and the sub-circuit have fixed structures; after the completion, returning to the step 2;

and 5, executing the merging mode, finding out the single quantum gate specified by the continuous merging mode, processing by the processing function specified by the merging mode, and returning to the step 2 after the processing is finished.

Further, the step 1 of converting the quantum wire into the DAG representation means that the quantum wire is represented as a DAG whose vertex is a single-quantum gate or a double-quantum gate and whose edge is the quantum bit information dependent on the arc tail node.

Further, in step 4, a general pattern is executed, which includes the sub-circuit to be searched and the sub-circuit for replacement, both of which have fixed structures, specifically including:

step 4.1, giving DAG representation of the original line and the mode line, and executing a QVF quantum line mode matching algorithm;

step 4.2, outputting an isomorphic mapping list as a matching line context after matching;

step 4.3, giving DAG representation of the original line and the substitute sub-line, and executing a sub-graph replacement algorithm by combining the matching line context in the step 4.2;

furthermore, a description format of a general mode and a description format of a merging mode are defined based on the JSON file, wherein the general mode comprises a mode line and a substitute line which are respectively marked as C_pAnd C_s(ii) a The mode wire describes what wire is replaced, and the alternate wire describes what wire should be used to replace the mode wire.

The description format of each common schema is mainly composed of three parts: "qubits", "src", and "dst", where the term "qubits" describes the mode line C_PThe maximum qubit number used in "src" and "dst" terms are used to describe the source, i.e., mode, and destination, i.e., alternate, lines of the conversion relationship.

The QVF quantum line matching algorithm specifically includes the following steps:

1) initializing isomorphic mapping listsIs empty, state queueWhereinIt is referred to as an empty set,for only one isomorphic mapping M stored in the initial state queue<M₁，M₂>Its structure maps M₁And semantic mapping M₂All are empty sets; and initializing M for temporary storage of current state structure mapping_strAnd semantically mapped M_sem；

2) If Q is_sIf the program is empty, the program is terminated, otherwise the program continues to be executed;

3) from Q_sGet out of isomorphic mapping of queue head M ═<M₁,M₂>And perform value assignment<M_str，M_sem>M, which is then queued from state queue Q_sDeleting;

4) if the current structure maps M_strCovered the mode line G_pAll vertices in (D), in other words dom (M)_str)＝G_pV, then add the current isomorphic mapping to the listMedium, and return to 2);

5) mapping M according to the current structure_strOriginal line G_oAnd mode line G_pCalculating a current candidate ordered point pair set P;

6) traversing each point pair P in the set P, and executing:

6.1) execution of FeasibilityRules (M)_str，M_semP) function, judging the structure mapping M after adding the point pair p_strWhether vertex isomorphic conditions are satisfied and modify semantic mapping M_semIs M'_semTo make it conform to the new vertex mapping relation; if such M 'is present'_sem6.2) is executed, otherwise, the next point pair p is taken out, and 6.1) is executed again;

6.2) new isomorphic mapping M ═<M_str∪p，M′_sem>Add to queue Q_sTaking out the next point pair p, and returning to 6.1);

7) return 2).

Wherein the FeasibilityRules function mentioned in 6.1) is a function embodiment defined in 2. Unlike the original VF2 algorithm, the QVF needs to consider not only the correctness of the structure mapping and further pruning, but also whether the mapping of the parameters of the quantum gate satisfies the requirements, such as the type of quantum gate, especially the qubit parameters and the rotation parameters.

The subgraph replacement algorithm specifically comprises the following steps:

1) initializing a line sub-graph representation G_r＝G_o；

2) Traversing a mapping listFrom which an isomorphic mapping M is taken<M_str，M_sem>If the mapping list is presentNull, return the final DAG graph G_rAnd ending the algorithm;

3) using M_strDetermining a matching sub-graph g in the original graph by using the vertex information contained in the graph, and utilizing M_semInclusion mapping instantiation schema wire G_s；

4) Determining a mode line G_sSet S consisting of the first and last corresponding vertices of the quantum gate acting on a qubit_inAnd S_out；

5) Determining a set T of vertices into and out of a matching subgraph g_inAnd T_out；

6) Matching sub graph G and the edge connecting the top point and the rest part are driven from G_rDeleting and removing G_sIs added to G_rIn this case G_rFrom the excised remainder and instantiated G_sThe two are not connected with each other;

7) for each qubit q e g.Q contained in the matching subgraph g, the following steps are performed:

7.1) by using M_semFind each qubit at G_pCorresponding qubit index

7.2) depending on whether q' is at G_sThe method is divided into two cases:

i. if q'. epsilon.G_sQ, description of S_in[q′]And S_out[q′](ii) present; if T is_in[q]If present, go to G_rAdding a new edge (T)_in[q]，S_in[q′]) (ii) a If T is_out[q]Exist to G_rAdding a new edge (S)_out[q′]，T_out[q])；

ii ifIf T is_in[q]And T_out[q]At the same time, to G_rAdding a new edge (T)_in[q]，T_out[q])；

7.3) if existing, taking out the next qubit q in g, returning to 7.1), otherwise, executing 8);

8) back to 2).

Has the advantages that:

the invention can realize the functions of line conversion and line optimization, provides the QVF algorithm with the isomorphism of the subgraph to solve the problem of pattern matching of the line, and designs the subgraph replacement algorithm based on the line matching information. The invention also introduces a mode description format of quantum line equivalence relation, and defines two specific mode categories of a general mode and a merging mode and description formats thereof, so that the rewriting method can process rewriting problems such as line optimization, line conversion and the like. Experiments on the quantum test suite provided by IBM and ScaffCC show that the continuous single quantum gate optimization achieved by the method of the present invention can provide 10% optimization rate on quantum program scale.

Drawings

FIG. 1 is a symbolic representation of some general quantum gates in a quantum wire and corresponding matrix representation;

FIG. 2 is a circuit model and DAG representation of a quantum program; (a) a line model, (b) a DAG representation without single quantum gates, (c) a DAG representation with single quantum gates;

FIG. 3 is a process flow of a method of quantum wire rewriting;

FIG. 4 is a line model of the Bridge gate and corresponding general schema description format, (a) an example of a line equivalence relation under the line model representation, and (b) a line equivalence relation represented by the schema description format;

FIG. 5 is for a merge mode of the H-gate;

FIG. 6 is a DAG representation of an equivalent pattern for a Bridge gate;

matching subgraph of the exemplary line of FIG. 7 and its T_inAnd T_outStructure;

FIG. 8 matches G after the original position of sub-graph G has been instantiated_sAn alternative schematic diagram;

FIG. 9 illustrates the rules for decomposition between the superconducting stage and the ion trap stage in Qiaskit;

fig. 10U3 matrix representation of the gate.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.

The main technical content of the invention relates to the definition of the DAG representation of quantum wires, the description format of equivalent quantum wires, the design of the subgraph isomorphic algorithm QVF and the subgraph replacement algorithm. Before the details of each part are introduced, the detailed flow of the quantum wire general transformation method proposed by the present invention is briefly summarized, and several definitions related to the introduction process are given.

The specific implementation of the quantum wire model as input and output here is determined by the respective program platform, but before processing it needs to be converted into the DAG intermediate representation as defined by the inventive rewrite method. In the present invention, the DAG representation of a quantum wire is defined as follows:

definition 1 (DAG representation of quantum wires): the DAG representation of a quantum line is defined as a triplet G ═<Q，V，E>Wherein Q ═ {0, 1, 2. } contains the qubit index value on which the quantum wire acts, V and E represent the vertex set and the edge set in the DAG, respectively; each vertex V ═ V (op, qlist, angle) e V in the DAG corresponds to a gate in the quantum line, where op represents the gate operation type, qlist and angle storing the quantum bit parameters and the rotation angles that may exist; each side e ═ e: (<v_i，v_j>Q) E E represents the gate v_iTo v_jQubit dependency relationship between, i.e. gate v_jDependent on door v_iThe acted qubit Q ∈ Q state, and Q satisfies Q ∈ v_iQlist and q ∈ v_j·qlist。

Fig. 3 shows a processing flow chart of a quantum wire method, and in particular, a method for program-generic transformation of a quantum wire in combination with subgraph isomorphism, which includes the following steps:

step 1, inputting a quantum program, and converting quantum circuits into Directed Acyclic Graphs (DAG) representation based on a circuit model;

step 2, the mode scheduler judges, if the user does not assign a scheduling rule to the mode scheduler, the mode is selected randomly from the mode library directly; if the mode scheduler has a rule specified by a user, selecting a mode according to the specified rule;

step 3, the mode scheduler selects proper routines to execute processing according to the type of the mode; specifically, if the mode is the general mode, step 4 is executed; if the mode is the merging mode, executing the step 5;

step 4, executing a general mode which comprises a sub-circuit to be searched and a sub-circuit for replacement, wherein the sub-circuit and the sub-circuit have fixed structures; after the completion, returning to the step 2;

step 5, executing the merging mode, finding out a single quantum gate appointed by the continuous merging mode, processing by a processing function appointed by the merging mode, and returning to the step 2 after the processing is finished;

and 6, sequentially scheduling according to specific requirements, sequentially finishing line optimization, and outputting the converted quantum line model after finishing the line optimization.

If the user does not specify a scheduling rule for the pattern scheduler, the pattern scheduler takes a pattern directly from the pattern library after the quantum wires are converted to the DAG representation. An appropriate routine is selected according to the kind of mode to execute the processing. The present invention has provided for the rewriting of two modes, one referred to as a general mode and the other referred to as a merge mode.

The generic pattern describes the sub-circuit that needs to be searched and the sub-circuit for replacement, both with a fixed structure. The routine for processing the general pattern is composed of a pattern matching algorithm and a subgraph replacement algorithm. To achieve better performance, the pattern matching algorithm transforms the problem of finding pattern lines in the lines into a sub-graph isomorphism problem in graph theory. One of the most common subgraph isomorphic algorithms at present is the VF2 algorithm, and the invention modifies the VF2 algorithm according to the characteristics of quantum line transformation and designs the QVF quantum line pattern matching algorithm. For an incoming quantum wire program (called original wire, denoted C)_o) Matching information obtained via QVF algorithmic pattern matching is referred to as the matching line context, and is passed to the subgraph replacement process. The subgraph replacement process uses the matching line context to determine the position of the pattern line in the line and replace it, represented by the DAG of the original line and the replaced line.

The merge mode describes quantum gates that act on a quantum bit in succession. Unlike the generic model, it does not have a fixed structure, which also means that the above-described routines are not suitable for handling such a model. Thus, the processing idea of the routine corresponding to the merge mode is to find a series of specified single-quantum-bit gates in the line, such as shown in fig. 1, and then process the gate with the processing function specified by the merge mode.

If a specific specified rule exists in the mode scheduler, the execution of the modes is not sequentially executed, but is sequentially scheduled according to specific requirements, so that the circuit optimization with more complex logic, such as easy optimization, continuous single-gate optimization and the like, is completed, and the processing capacity of the framework is expanded.

Pattern description format for equivalent circuit

The re-write method proposed by the present invention is intended to replace unsupported or high overhead sub-lines in a line. In order to make the rewriting method have expansibility on the supported line equivalent transformation mode, the invention designs a mode description format, and a user can describe a line needing to be replaced and a line to be replaced according to the format. In addition, in order to ensure the expression capability of the patterns on the equivalence relation, the invention defines the description formats of two patterns, namely a general pattern and a merging pattern, based on the JSON file.

The first mode is as follows: general mode

Each common mode includes two parts, mode line and alternative line, labeled C_pAnd C_s. The mode wire describes what wire is replaced, and the alternate wire describes what wire should be used to replace the mode wire.

Fig. 4(b) illustrates the general line equivalence mode shown in fig. 4(a), i.e., Bridge gates, which are commonly used in quantum hardware devices where the topology of abstract qubits has directions. The "general" entry in the first row of FIG. 4(b) indicates that a series of common patterns are contained in the following brackets. Lines 2-21 describe a generic schema called "bridge," the name of which is customizable by the user.

The description format of each common schema is mainly composed of three parts: "qubits", "src" and "dst". Wherein the term "qubits" describes the mode line C_PThe maximum number of qubits used. The terms "src" and "dst" are used to describe the source line (i.e., the mode line) and the destination line (i.e., the alternate line) of the conversion relationship)。

The description format of quantum wires consists of two parts, a "cost" and a "circuit". The "cost" entry is used to account for the overhead of the line. There are two possible general modes in the current framework: if C is present_PAnd C_SThe costs of (a) are equal, then the pattern describes the decomposition rule; if C is present_SAt a cost lower than C_PThen the schema describes the optimization rules. The cost calculation is based on the simple assumption that the cost of the implementation of a two-quantum bit gate is 2 and the cost of the implementation of a single-quantum bit gate is 1, and the specific numerical value can be changed by the user according to the situation. For a quantum gate to act on more than two qubits, the cost calculation should be based on decomposing it into lines after a double quantum gate and a single quantum gate.

The "circuit" term consists of a series of gates in a quantum program-like manner. Each row describes a quantum gate operation, including the kind of gate and its parameters, which relate to the qubit acted on and the rotation angle. In addition, the angle parameter in a quantum wire may be constant or variable.

Note that in the general pattern description, the defined pattern line and the alternative line are both line templates, and the parameters involved in the pattern line and the alternative line are all reset in the matching or replacing process, and both share a set of virtual parameters. In the pattern matching process, it is necessary to distinguish which subgraph in the original line is isomorphic with the pattern line, or can be matched, and the specific isomorphic condition is defined in definition 2. The DAG representations of the original lines, the pattern lines, and the substitute lines are referred to herein as G, using the original graph, the pattern graph, and the substitute graph, respectively_o,G_pAnd G_s。

Define 2 (sub-graph isomorphic condition of a quantum wire) for two given quantum wire DAG representations G_p、G_sFrom G_pTo mapping M ═ M<M_str，M_sem>Represents a possible isomorphic relationship when M is mapped to a structure_str，(n，m)∈M_str，n∈G_p.V,m∈G_sV satisfies the following vertex isomorphism condition:

i.n.op＝m.op；

ii.|n.qlist|＝|m.qlist|；

iii.|n.angle|＝|m.angle|；

n.angle [ i ] is the same complex constant as m.angle [ i ] for each i, or at most one is a variable;

at the same time, m is mapped to the semantics_semEach side pair (e)_s，e_d)∈M_semThe following edge isomorphism conditions are satisfied:

i.e_s＝(<n₁，n₂>，q₁)∈Gp.E；

ii.e_d＝(<m₁，m₂>，q₂)∈G_o.E；

iii.(n₁，m₁)∈M_str，(n₂，m₂)∈M_str；

further, for each qubit pair (q)₁，q₂)∈m_sem，q₁，q₂Should have the same qubit type (e.g. both control bits or both steered bits)

Isomorphic conditions describe the matching relationship between the matched subgraph in the original graph, denoted as g, and the pattern graph. Since there are matching lines of a plurality of pattern lines in the original line, the present invention defines a listAs match line context, it is passed by the pattern matching algorithm to the sub-graph replacement portion. In the subgraph replacement algorithm, each M_iIs used to instantiate and replace alternate lines (particularly qubit parameters and rotation angles)A determined subgraph.

And a second mode: merge mode

Since the quantum gates are reversibly operated, the effect of the same type of quantum gate acting successively on the same qubit is equivalent to that of an identity transformation or of a quantum gate, e.g. an even number of successive operationsWith H gates directly removable from the circuit, with a plurality of successively acting R_zThe gate may be replaced with a single R_zAnd a door. Obviously, this model does not have a fixed structure, and the general model can complete this function by processing several doors at once, but is inefficient and has poor expandability. Thus, the present invention designs a merge pattern to extend the expressive power of the present schema description format, as shown in FIG. 5, lines 2-8 define a merge pattern named "accH".

The merge mode is much simpler than the general mode, since the responsibility for specifying processing functions is handed over to the user as well as to the interpreter. Defined in parenthesis following the first row of the "merge" description is a series of merge patterns. From the "type" entry, the interpreter in the schema scheduler needs to tell the merge processing module which contiguous sequence of gates needs to be found. The processing module does not retain match line context, but instead calls the function specified by the "function" entry to process the matched sub-graph when a continuous sequence is found.

According to the embodiment of the present invention, since the execution flows of the merge mode and the mode scheduler depend on the selection of the user, the entire rewrite method mainly considers the implementation details of the general mode processing routine.

The QVF pattern matching algorithm of the present invention specifically includes the following:

DAG representation G given original and pattern lines_oAnd G_pThe QVF pattern matching algorithm should output an isomorphic mapping listAs the match line context and passed to the sub-graph matching process.

The general idea of the QVF algorithm according to the embodiment of the present invention is as follows:

1) initializing isomorphic mapping listsIs empty, state queueWhereinIt is referred to as an empty set,for only one isomorphic mapping M stored in the initial state queue<M₁，M₂>Its structure maps M₁And semantic mapping M₂All are empty sets; and initializing M for temporary storage of current state structure mapping_strAnd semantically mapped M_sem；

2) If Q is_sIf the program is empty, the program is terminated, otherwise the program continues to be executed;

3) from Q_sGet out of isomorphic mapping of queue head M ═<M₁，M₂>And perform value assignment<M_str，M_sen>M, which is then queued from state queue Q_sDeleting;

4) if the current structure maps M_strCovered the mode line G_pAll vertices in (D), in other words dom (M)_str)＝G_pV, then add the current isomorphic mapping to the listMedium, and return to 2);

5) mapping M according to the current structure_strOriginal line G_oAnd mode line G_pCalculating a current candidate ordered point pair set P;

6) traversing each point pair P in the set P, and executing:

6.1) execution of FeasibilityRules (M)_str，M_semP) function, judging the structure mapping M after adding the point pair p_strWhether vertex isomorphic conditions are satisfied and modify semantic mapping M_semIs M'_semTo make it conform to the new vertex mapping relation; if such M 'is present'_sem6.2) is executed, otherwise, the next point pair p is taken out, and 6.1) is executed again;

6.2) new isomorphic mapping M' ═ M_str∪p，M′_semAdd to queue Q_sTaking out the next point pair p, and returning to 6.1);

7) return 2).

Wherein the FeasibilityRules function mentioned in 6.1) is a function embodiment defined in 2. Unlike the original VF2 algorithm, the QVF needs to consider not only the correctness of the structure mapping and further pruning, but also whether the mapping of the parameters of the quantum gate satisfies the requirements, such as the type of quantum gate, especially the qubit parameters and the rotation parameters.

The subgraph replacement algorithm of the invention is specifically as follows:

context information of the matched line generated by QVF pattern matching, i.e. isomorphic mapping listsIs passed to the subgraph replacement algorithm. For theEach isomorphic mapping in (1), structure mapping M_strFor determining the position of the matching subgraph g, while the semantic map M_semFor instantiating a surrogate graph G as a template_sTo ensure the reasonableness of DAG as a representation of quantum wires. Thus the input to the algorithm comprises a list of mappingsOriginal graph G_oAnd alternative graph G_sThe output is the DAG representation G after replacement_r。

The most important link in subgraph replacement is to determine DAG after deleting matching subgraph G and substitute graph G after instantiation_sThe connection point between them. To this end, a new structure is introduced to illustrate this operation. Note T_inSet of arc-tail vertices for those edges whose arc-head is in g and whose arc-tail is not, T_outA set of arc head vertices for those edges whose arc tail is in g and arc head is not in g; note S_inContains the vertex whose first in the topological order contains a certain qubit q, and S_outThe last one of the inclusion topological order contains a certainThe vertex of qubit q'. The former corresponds to the qubit q in the quantum wire corresponding to the first quantum gate on the horizontal line, and the latter corresponds to the qubit q' corresponding to the last quantum gate on the horizontal line. Both are ubiquitous in DAG representation of quantum wires, and for the avoidance of ambiguity, T will be used here_inAnd T_outIs limited in the range of use of G_oIn, i.e.v∈G_oAnd then S is_inAnd S_outIs limited in the range of use of G_pAnd G_sAnd (the two lines share a set of dummy qubit sets as the template lines).

Note that vertices within these sets all have a mapping relationship with the qubits. S_inAnd S_outObviously. T because each edge e has a qubit label e.q_in(T_out) The inner node has an association with the label e.q corresponding to the edge e when defined. Therefore, the present invention adds a corresponding qubit q index to the original set to facilitate the following description.

For ease of understanding, FIG. 6 is a DAG representation of FIG. 4 (a). The DAG nodes in the graph only contain their sequence numbers in the DAG graph and the corresponding quantum operations. Shown on the right side of fig. 6 is an alternative to this mode. Since node 0 corresponds to both the first contribution to qubit q [0 ]]And q [1 ]]Is the last one, so S in the figure is replaced at this time_in＝S_out0. Consider the application of the pattern matching algorithm to the DAG representation of a quantum wire shown in fig. 7 using the equivalent pattern of fig. 6, finding sub-graph g corresponding to nodes 6-10 in fig. 7. For matching subgraph g, its corresponding T_inAnd T_outStructures are also labeled in the figures. Wherein node 4 belongs to T because it has an edge pointing to node 6_in. For convenience of later use, the node is denoted as T according to the label of this edge_in[q[2]]. Node 13 and node 14 are labeled q [2 ]]And q [3 ]]Of (a) thus belongs to T_outLet two nodes be T_out[q[2]]，T_out[q[3]]. In the process of replacing the algorithm, because each edge represents the dependency between nodes on the quantum bit, the connection point is established by connecting T_inAnd S_in，T_outAnd S_outThe nodes that operate on the same qubit are connected.

The subgraph replacement algorithm operates as follows:

1) initializing a line sub-graph representation G_r＝G_o；

2) Traversing a mapping listExtracting isomorphic mapping M ═ M from the map_str，M_semIf the mapping list at this timeNull, return the final DAG graph G_rAnd ending the algorithm;

3) using M_strDetermining a matching sub-graph g in the original graph by using the vertex information contained in the graph, and utilizing M_semInclusion mapping instantiation schema wire G_s；

4) Determining a mode line G_sSet S consisting of the first and last corresponding vertices of the quantum gate acting on a qubit_inAnd S_out；

5) Determining a set T of vertices into and out of a matching subgraph g_inAnd T_out；

6) Matching sub graph G and the edge connecting the top point and the rest part are driven from G_rDeleting and removing G_sIs added to G_rIn this case G_rFrom the excised remainder and instantiated G_sThe two are not connected with each other;

7) for each qubit q e g.Q contained in the matching subgraph g, the following steps are performed:

7.1) by using M_semFind each qubit at G_pCorresponding qubit index

7.2) depending on whether q' is at G_sThe method is divided into two cases:

i. if q'. epsilon.G_sQ, description of S_in[q′]And S_out[q′](ii) present; if T is_in[q]If present, go to G_rAdding a new edge (T)_in[q]，S_in[ q'); if T is_out[q]Exist to G_rAdding a new edge (S)_out[q′]，T_out[q])；

ii ifIf T is_in[q]And T_out[q]At the same time, to G_rAdding a new edge (T)_in[q]，T_out[q])；

7.3) if existing, taking out the next qubit q in g, returning to 7.1), otherwise, executing 8);

8) back to 2).

The graph replacement algorithm is run, as shown in FIG. 8, at this time at G_rIn, G after the original position of the matching sub-graph G has been instantiated_sAnd (4) replacing. But the rest remains unchanged compared to the original graph, and the edges between the newly added and replacement subgraphs meet the requirements of defining a DAG representation of the quantum wire in one.

The invention can realize the functions of line conversion and line optimization. The implementation of both is discussed below.

The application one is as follows: line switching

Line translation addresses implementation differences between the physical and logical layers and between different physical platforms. For example, a similar approach is taken by the quantum programming framework for switching between platforms, as shown in fig. 9, which introduces the ion trap platform by way of decomposition rules. The first rule shows the decomposition rule from the CNOT gate in superconductivity to the quantum gate supported by the ion trap, the last two show the XX-rotation (rxx) gate sum from the ion trapDecomposition rules for gate-to-CNOT operations. Obviously, these rules can be expressed by the general mode designed by the present invention, and naturally, the conversion between platforms can also be accomplished by the rewriting method of the present invention.

The application II comprises the following steps: line optimization

Line optimization by replacing a high overhead sub-line in the line with another equivalent implementation with low overhead can be accomplished by the universal pattern expressive power rewrite methodology of the present invention. For a more complex line optimization method, a mode scheduling module is needed. Such as optimization of a continuous single quantum gate. The basis for this operation is that all single quantum gates can be represented as U3 gates (the expression for U3 gates is shown in fig. 10), and several successive U3 gates can be combined into one U3 gate, thereby reducing the number of operations to reduce the line size. The invention can add the conversion rule from the single quantum gate to the U3 gate and the combination rule of the continuous U3 gate in the mode library, and make the mode dispatcher complete the conversion of the single quantum gate first and then call the combination of the U3 gate, thereby completing the combination of the continuous single gates.

The framework of the method is called pattern-matching-based unknown quantity Rewriting frame (QCiR). With the present invention, one of the above described sequential single quantum bit gate optimizations is achieved and the performance of the QCiR framework is tested using a test program selected from the group provided by IBM and ScaffCC. The invention adopts the optimized quantum gate number and the optimized rateThe method is used as an evaluation index of the optimization algorithm to measure the efficiency of the method. From the experimental results shown in table 1, it can be seen that the continuous single gate optimization achieved by the QCiR framework has an average optimization rate of 10%, thus proving the effectiveness of the framework.

TABLE 1 continuous Single Gate optimization of results of execution of test programs provided by IBM and ScaffCC

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but various changes may be apparent to those skilled in the art, and it is intended that all inventive concepts utilizing the inventive concepts set forth herein be protected without departing from the spirit and scope of the present invention as defined and limited by the appended claims.