阅读说明：本技术 双通道ddr动态随机存取存储器的减少的纠错码 (Reduced error correction code for dual channel DDR DRAM ) 是由 纳尔辛·克里希纳·维贾伊拉奥 克里斯蒂安·马库斯·彼得森 于 2021-05-06 设计创作，主要内容包括：本申请涉及双通道DDR动态随机存取存储器的减少的纠错码。接收第一组64字节数据和第二组64字节数据。为第一组64字节数据计算第一组八个纠错码(ECC)字节,并为第二组64字节数据计算第二组八个ECC字节。在单个突发中通过第5代双数据速率(DDR5)双通道,第一组64字节数据、第二组64字节数据、第一组八个ECC字节和第二组八个ECC字节被发送到一个或更多个DDR5同步动态随机存取存储器(SDRAM)模块,其中DDR5双通道包括第一数据通道和第二数据通道,并且其中第一数据通道和第二数据通道由相同的时钟信号驱动。(The application relates to reduced error correction codes for dual channel DDR dynamic random access memories. A first set of 64 bytes of data and a second set of 64 bytes of data are received. A first set of eight Error Correction Code (ECC) bytes is calculated for the first set of 64 bytes of data and a second set of eight ECC bytes is calculated for the second set of 64 bytes of data. The first set of 64 bytes of data, the second set of 64 bytes of data, the first set of eight ECC bytes, and the second set of eight ECC bytes are sent to one or more DDR5 Synchronous Dynamic Random Access Memory (SDRAM) modules over a double 5-generation double data rate (DDR5) lane in a single burst, wherein the DDR5 lane includes a first data channel and a second data channel, and wherein the first data channel and the second data channel are driven by the same clock signal.)