阅读说明：本技术 显示装置 (Display device ) 是由 朱成培 于 2021-04-29 设计创作，主要内容包括：本公开涉及一种显示装置,显示装置包括：基板,其包括显示区域、非显示区域和导电材料；显示层,其位于基板的顶表面上,并且包括发光元件；信号线,其从显示层延伸并进入到非显示区域中；导电粘合剂构件,其位于基板的底表面上；以及电路板,其通过电路板与导电粘合剂构件的接触以及基板中的导电材料与信号线和导电粘合剂构件二者的接触而电连接到信号线。(The present disclosure relates to a display device including: a substrate including a display region, a non-display region, and a conductive material; a display layer on a top surface of the substrate and including a light emitting element; a signal line extending from the display layer and into the non-display region; a conductive adhesive member on a bottom surface of the substrate; and a circuit board electrically connected to the signal line by contact of the circuit board with the conductive adhesive member and contact of the conductive material in the substrate with both the signal line and the conductive adhesive member.)

1. A display device, comprising:

a substrate, comprising:

the display area is a display area in which,

a non-display area adjacent to the display area,

a top surface and a bottom surface, the bottom surface being opposite the top surface, an

A conductive material;

a display layer in the display area including light emitting elements, the display layer on the top surface of the substrate;

a signal line connected to the light emitting element, the signal line extending from the display layer and into the non-display region; and

in the non-display region, the display device includes:

a conductive adhesive member on the bottom surface of the substrate; and

a circuit board facing the signal line, the substrate and the conductive adhesive member both being between the circuit board and the signal line;

wherein, in the non-display area, the circuit board is electrically connected to the signal line by a contact of the circuit board with the conductive adhesive member and a contact of the conductive material in the substrate with both the signal line and the conductive adhesive member.

2. The display device of claim 1, wherein the substrate further comprises:

a polymer resin, and

the conductive material including a plurality of first conductive balls located within the polymer resin,

wherein, in the non-display area, the circuit board is electrically connected to the signal line by contact of the plurality of first conductive balls in the substrate with both the signal line and the conductive adhesive member.

3. The display device according to claim 2, wherein the conductive adhesive member comprises:

a binder resin, and

a plurality of second conductive balls located within the binder resin,

wherein, in the non-display area, the circuit board is electrically connected to the signal lines by contact of the circuit board with the plurality of second conductive balls in the conductive adhesive member and contact of the plurality of first conductive balls in the substrate with the signal lines and the plurality of second conductive balls in the conductive adhesive member.

4. A display device according to claim 3, wherein

The substrate further comprises a thickness direction defined between the top surface and the bottom surface of the substrate, an

The conductive adhesive member is aligned with the signal line and the non-display area of the substrate along the thickness direction of the substrate.

5. Display device according to claim 4, wherein

The signal lines extending from the display layer and into the non-display area define conductive pads in the non-display area, an

In the non-display area:

the display layer defining a pad hole exposing the top surface of the substrate,

at the bond pad hole, the conductive bond pad extends through the display layer to contact a top surface of the substrate exposed at the bond pad hole, an

The circuit board is electrically connected to the signal lines by the contact of the plurality of first conductive balls in the substrate with the signal lines contacting the conductive pads of the top surface of the substrate at the pad holes.

6. The display device according to claim 5, wherein in the non-display region, the conductive pads, the first conductive balls of the substrate, and the second conductive balls of the conductive adhesive member are aligned with and respectively in contact with each other along the thickness direction of the substrate.

7. The display device according to claim 6, wherein

The circuit board includes bump electrodes, and

in the non-display area:

the bump electrodes of the circuit board are aligned with the first conductive balls of the substrate and the second conductive balls of the conductive adhesive member along the thickness direction of the substrate, an

The circuit board is electrically connected to the signal lines by the contact of the bump electrodes of the circuit board with the plurality of second conductive balls in the conductive adhesive member.

8. The display device according to claim 1, wherein

Each of the substrate, the conductive adhesive member, and the circuit board includes an outer side surface farthest from the display area, an

The outer side surface of the substrate, the outer side surface of the conductive adhesive member, and the outer side surface of the circuit board are aligned with each other.

9. The display device of claim 1, wherein the substrate further comprises the conductive material dispersed along both the non-display area and the display area of the substrate.

10. A display device comprising

A substrate, comprising:

the display area is a display area in which,

a non-display area adjacent to the display area,

a top surface and a bottom surface, the bottom surface being opposite the top surface,

a conductive material, and a conductive material,

a first substrate area not including the conductive material, the first substrate area corresponding to the display area, an

A second substrate region including the conductive material, the second substrate region corresponding to the non-display region;

a display layer in the display area including light emitting elements, the display layer on the top surface of the substrate;

a signal line connected to the light emitting element, the signal line extending from the display layer and into the non-display region; and

in the non-display region, the display device includes:

a conductive adhesive member on the bottom surface of the substrate; and

a circuit board facing the signal line, the second substrate region and the conductive adhesive member both being between the circuit board and the signal line;

wherein, in the non-display area, the circuit board is electrically connected to the signal line by a contact of the circuit board with the conductive adhesive member and a contact of the conductive material in the second substrate area with both the signal line and the conductive adhesive member.

Technical Field

The present disclosure relates to a display device.

Background

With the development of multimedia, display devices have become more and more important. Various types of display devices have been used, such as liquid crystal display ("LCD") devices, organic light emitting diode ("OLED") display devices, and the like.

Foldable display devices are receiving increasing attention. The foldable display device has advantages of a smart phone and a tablet personal computer ("PC") because the foldable display device is portable and has a wide display screen. In the foldable display device, a pad portion provided with a driving integrated circuit ("IC") or other printed circuit board may be provided at an edge portion of an outer portion of a substrate forming the foldable display device. The pad part may correspond to a bezel of the foldable display device, which is a non-display area where an image is not displayed.

Disclosure of Invention

Embodiments provide a display device that includes a pad portion and minimizes the size of a bezel.

However, the embodiments are not limited to those described herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present invention pertains by referencing the detailed description given below.

According to an embodiment, a display device includes: a substrate including a display region, a non-display region, and a conductive material; a display layer on a top surface of the substrate and including a light emitting element; a signal line extending from the display layer and into the non-display region; a conductive adhesive member on a bottom surface of the substrate; and a circuit board electrically connected to the signal line by contact of the circuit board with the conductive adhesive member and contact of the conductive material in the substrate with both the signal line and the conductive adhesive member.

In an embodiment, the conductive material may include a plurality of first conductive balls, and the substrate may further include a polymer resin in which the first conductive balls are dispersed.

In an embodiment, the conductive adhesive member may include a plurality of second conductive balls and an adhesive resin.

In an embodiment, the conductive adhesive member may overlap the non-display area and the signal line.

In an embodiment, the signal line may define a conductive pad, and the conductive pad may be electrically connected to the substrate at a pad hole defined in the display layer.

In an embodiment, the conductive pad, the first conductive ball, and the second conductive ball may overlap and contact each other in the non-display area.

In an embodiment, the circuit board may include a bump electrode, the bump electrode may overlap the first conductive ball and the second conductive ball contacting each other, and the bump electrode may contact the second conductive ball.

In an embodiment, the outer side surfaces of the substrate, the conductive adhesive member, and the circuit board may be aligned with and contact each other.

In an embodiment, the conductive material may be in the entirety of the substrate.

According to an embodiment, the display device includes a substrate including a display region, a non-display region, a first substrate region and a second substrate region, a display layer located on an upper surface of the substrate and including a light emitting element, a signal line extending from the display layer into the second substrate region of the non-display region, a conductive adhesive member located on a bottom surface of the second substrate region of the substrate, and a circuit board electrically connected to the signal line by a contact of the circuit board with the conductive adhesive member and a contact of a conductive material in the second substrate region with both the signal line and the conductive adhesive member.

Other features and aspects will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

Drawings

The above and other embodiments and features will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings, in which:

FIG. 1 is a perspective view illustrating an embodiment of a front side of a display device;

FIG. 2 is a perspective view illustrating an embodiment of a back side of the display device of FIG. 1;

FIG. 3 is a cross-sectional view of an embodiment of the display device of FIG. 1;

FIG. 4 is a plan view illustrating an embodiment of a sensor electrode layer of the display device of FIG. 1;

FIG. 5 is a plan view illustrating an embodiment of the driving electrodes, the sensing electrodes, and the first connection parts of FIG. 4;

FIG. 6 is a cross-sectional view taken along line I-I' of FIG. 5;

FIG. 7 is a plan view illustrating an embodiment of a display pad area of the display device of FIG. 1;

FIG. 8 is a sectional view taken along line II-II' of FIG. 7;

FIG. 9 is an enlarged cross-sectional view illustrating an embodiment of region B of FIG. 8;

FIG. 10 is a cross-sectional view taken along line III-III' of FIG. 7;

FIG. 11 is a cross-sectional view of an embodiment of a display device;

FIG. 12 is a plan view of an embodiment of a substrate of the display device of FIG. 11;

FIG. 13 is a cross-sectional view of an embodiment of the display device of FIG. 11;

FIG. 14 is an enlarged cross-sectional view of an embodiment of a portion of the display device of FIG. 13;

FIG. 15 is a plan view of an embodiment of a substrate of a display device;

FIG. 16 is a cross-sectional view of an embodiment of the display device of FIG. 15;

FIG. 17 is a cross-sectional view of an embodiment of a portion of the display device of FIG. 15; and

fig. 18 to 20 are plan views illustrating a structure in an embodiment of a method of providing a substrate of a display device.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will also be understood that when a layer is referred to as being "associated with" (such as being "on") another layer, it can be directly on the other layer or the substrate, or intervening layers may also be present. In contrast, when a layer is referred to as being associated with another layer (e.g., "directly on" another layer or substrate), there are no other layers or substrates or intervening layers present. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "a", "an", "the" and "at least one" do not denote a limitation of quantity, and are intended to include both the singular and the plural. For example, "an element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "at least one" should not be construed as limiting "one" or "an". "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "including," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Further, relative terms (such as "lower" or "bottom" and "upper" or "top") may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below" or "beneath" may encompass both an orientation of below and above.

As used herein, "about" and "approximately" include the average of the stated value and the specified value within an acceptable range of deviation as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations or within ± 30%, ± 20%, ± 10% or ± 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, deviations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Furthermore, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Embodiments will be described hereinafter with reference to the accompanying drawings.

Fig. 1 is a perspective view illustrating an embodiment of a front surface of a display device 10, and fig. 2 is a perspective view illustrating an embodiment of a rear surface of the display device 10 of fig. 1.

Referring to fig. 1 and 2, the display device 10, which is an electronic device displaying moving images or still images, may be used not only in a portable electronic device, such as a mobile phone, a smart phone, a tablet personal computer ("PC"), a smart watch, a watch phone, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player ("PMP"), a navigation device, or an ultra mobile PC ("UMPC"), but also in various other electronic display products, such as a television ("TV"), a notebook computer, a display screen, a billboard, or an internet of things ("IoT") device.

The display device 10 may include a display panel 100, a display driving circuit 200, and a circuit board 300.

The first direction (or X-axis direction), i.e., the direction of the short side of the display device 10, may be, for example, the horizontal direction of the display device 10. The second direction (or Y-axis direction), i.e., the direction of the long side of the display device 10, may be the vertical direction of the display device 10. The third direction (or Z-axis direction) may be a thickness direction of the display device 10.

In a plan view (e.g., along the third direction), the display panel 100 may have a planar shape, such as a rectangular shape having a short side extending along the first direction (or the X-axis direction) and a long side extending along the second direction (or the Y-axis direction). Corners where the short sides and the long sides of the display panel 100 respectively meet each other may be rounded to have a predetermined curvature in a plan view, or may be right-angled in a plan view. The planar shape of the display panel 100 is not particularly limited, and the display panel 100 may have various other shapes in a plan view, such as a polygonal shape, a circular shape, or an elliptical shape.

The display panel 100 may be flat, such as disposed in a plane defined by a first direction and a second direction crossing each other, but is not limited thereto. In an embodiment, for example, the display panel 100 may include arc-shaped portions at left and right ends of the display panel 100 in the first direction and/or the second direction, and have a uniform or varying curvature. The display panel 100 may be flexible, such as foldable, bendable, and/or rollable.

The display panel 100 may be a light emitting display panel including light emitting elements. In an embodiment, for example, the display panel 100 may be an organic light emitting diode ("OLED") display panel using an OLED having an organic light emitting layer, a micro light emitting diode ("micro LED") display panel using a micro LED, a quantum dot light emitting diode ("QLED") display panel including a quantum dot light emitting layer, or an inorganic light emitting diode ("ILED") display panel using an ILED including an inorganic semiconductor.

The display panel 100 may be a foldable, bendable, or rollable flexible display panel. In an embodiment, for example, the display panel 100 may be a foldable display panel that can be folded or unfolded, an arc-shaped display panel having an arc-shaped display surface, a curved display panel that is curved in all regions thereof except the display surface, a rollable display panel that can be rolled or unrolled, or a stretchable display panel. Alternatively, the display panel 100 may be a transparent display panel that is transparent so that a background or an object outside the display panel 100 at the rear surface of the display panel 100 can be seen from the front surface of the display panel 100. Still alternatively, the display panel 100 may be a reflective display panel, and the display panel 100 may reflect an object or a background on its front surface.

The display panel 100 may include a display area DA displaying an image and a non-display area NDA not displaying an image. The non-display area NDA may be adjacent to the display area DA, such as extending around the display area DA in a plan view. The display area DA may include pixels (e.g., display pixels or display elements) that display an image. The non-display area NDA may be defined as a planar area extending between a side of the display area DA and an outer side surface or an outer edge of the display panel 100. Various components or elements of the display panel 100 and/or the display device 10 may include a display area and a non-display area corresponding to the display area DA and the non-display area NDA described above.

Referring to fig. 2, the display driving circuit 200 may be disposed on a circuit board 300.

The display driving circuit 200 may generate voltages and electrical signals for driving and/or controlling the display panel 100. The display driving circuit 200 may be an integrated circuit ("IC") such as one attached to the circuit board 300 in a chip on film ("COF"). Alternatively, the display driving circuit 200 may be attached to the circuit board 300, such as in a chip on glass ("COG") or chip on plastic ("COP") manner or by ultrasonic bonding, to be attached to the display panel 100, thereby reducing the size of the non-display area NDA.

The circuit board 300 may be attached to the display panel 100 at its back surface and at a first end by means of a conductive adhesive member CAM. Accordingly, the circuit board 300 may be electrically connected to both the display panel 100 and the display driving circuit 200. The display panel 100 and the display driving circuit 200 may receive electrical signals such as digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board ("FPCB"), a printed circuit board ("PCB"), or a flexible film such as a COF.

The conductive adhesive member CAM may be an anisotropic conductive film ("ACF") including a plurality of conductive members, such as a plurality of conductive balls. The conductive adhesive member CAM may include a plurality of conductive balls dispersed in an adhesive resin ADR.

Since the circuit board 300 is attached to the rear surface of the display panel 100 and is located within a planar area of the display panel 100 in a plan view, the bezel size of the display device 10 is reduced by omitting the planar area occupied by the circuit board 300 bent along the outer side surface of the display device 10.

Fig. 3 is a cross-sectional view of an embodiment of the display device 10 of fig. 1.

Referring to fig. 3, the display panel 100 may include a substrate SUB, a display layer DISL (e.g., an image display layer), a sensor electrode layer SENL (e.g., an input sensing layer), and a polarizing film PF (e.g., a polarizing layer).

The substrate SUB may include or be formed of an insulating material such as a polymer resin PSM. The substrate SUB may be a flexible substrate that is foldable, bendable and/or rollable.

The substrate SUB may comprise a conductive material. Specifically, the substrate SUB may include a conductive material dispersed in a polymer resin PSM. The conductive material may be a first conductive ball CM1 (e.g., a first conductive member) disposed in a plural number including a plurality of first conductive balls CM 1. The first conductive balls CM1 may be discrete members within the polymer resin PSM and electrically conductive. Since the substrate SUB includes the first conductive balls CM1, the substrate SUB may function as a conductor under certain conditions. The substrate SUB will be described in detail later.

The display layer dil may be disposed on the substrate SUB. The display layer dil may be a layer including a light emitting region displaying an image. The display layer dil may include a thin film transistor ("TFT") layer in which TFTs ST including a plurality of TFTs ST are disposed in a plural manner, a light emitting element layer EML in which a light emitting element 170 generating and/or emitting light is disposed in a light emitting region, and an encapsulation layer TFEL encapsulating the light emitting element layer EML on a substrate SUB.

At the display area DA, the display layer dil may include not only light emitting areas but also conductive lines for driving and/or controlling the light emitting elements 170, such as a gate signal line GLS, a data signal line DLS, and a power supply line VDS. In the non-display area NDA, the display layer dil may include a scan driving unit outputting a scan signal to the gate signal line GLS and a fan-out line connecting the data signal line DLS and the display driving circuit 200 to each other.

The sensor electrode layer SENL may be disposed on the display layer DISL. The sensor electrode layer sens may include a sensor electrode SE. The sensor electrode layer sens may be a layer that detects a touch input using the sensor electrodes SE.

The polarizing film PF may be additionally disposed on the sensor electrode layer SENL. The polarizing film PF may include a first base member, a linear polarizing film, a phase retardation film (such as a quarter wavelength (λ/4) plate), and a second base member. The first base member, the phase retardation film, the linear polarization film, and the second base member may be sequentially stacked on the sensor electrode layer SENL.

A cover window (not shown) may be additionally disposed on the polarizing film PF. The cover window may be attached to the polarizing film PF by an optically clear adhesive ("OCA") film.

A panel bottom cover (not shown) may be additionally disposed under the display panel 100. The panel bottom cover may be attached to the bottom surface of the display panel 100 by an adhesive member. The adhesive member may be a pressure sensitive adhesive ("PSA"). The panel bottom cover may include at least one of a light blocking member for absorbing incident light from the outside of the display device 10, a buffer member for absorbing shock from the outside, and a heat dissipation member for effectively releasing heat from the display panel 100.

The circuit board 300 to which the display driving circuit 200 is attached may be disposed under the display panel 100. The circuit board 300 may be attached to the bottom surface of the substrate SUB via a conductive adhesive member CAM.

Attaching the circuit board 300 to the substrate SUB may include thermocompression such that the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be pressed to be in contact with each other, and thus may be electrically connected to the plurality of lines disposed on the substrate SUB. As used herein, elements that are in contact with each other may form an interface therebetween, without limitation. This will be described in detail later.

Fig. 4 is a plan view illustrating an embodiment of a sensor electrode layer SENL of the display device 10 of fig. 1.

Referring to fig. 4, the sensor electrodes SE may be arranged in a plural number, including a plurality of sensor electrodes SE in the sensor electrode layer sens. The sensor electrodes SE may comprise two types of electrodes, e.g. drive electrodes TE and sense electrodes RE. Within the sensor electrode layer SENL, the driving electrodes TE and the sensing electrodes RE may be disposed in a plural manner, including a plurality of driving electrodes TE and a plurality of sensing electrodes RE. The sensor electrodes SE may be driven in a mutual capacitance manner, but not limited thereto, by applying a driving signal to the driving electrodes TE and detecting a voltage charging the mutual capacitance from the sensing electrodes RE.

For convenience, fig. 4 shows only the driving electrode TE, the sensing electrode RE, the dummy pattern DE including a plurality of dummy patterns DE disposed in a plural manner, a plurality of sensor lines SL, the first sensor pad TP1 including a plurality of first sensor pads TP1 disposed in a plural manner, and the second sensor pad TP2 including a plurality of second sensor pads TP2 disposed in a plural manner. A touch driving circuit (not shown) may be connected to the sensor electrode layer sensl at the first and second sensor pads TP1 and TP 2. The display pad PD, the first sensor pad TP1, and the second sensor pad TP2 may each be conductive pads.

Referring to fig. 4, the sensor electrode layer sen includes a touch sensing region TSA that detects an external input, and a touch peripheral region TPA (e.g., a non-sensing region) that does not detect an external input and is adjacent to the touch sensing region TSA. In an embodiment, the touch peripheral area TPA may surround the touch sensing area TSA. The touch sensing area TSA may overlap the display area DA of the display layer DISL, and the touch peripheral area TPA may overlap the non-display area NDA of the display layer DISL.

The touch sensing region TSA may include sensor electrodes SE and dummy patterns DE. The sensor electrode SE may be an electrode provided with a mutual capacitance to detect an external input, such as an external input from an object or a user (e.g., an input tool) outside the display apparatus 10 and/or the display panel 100.

The sensor electrodes SE may include drive electrodes TE and sense electrodes RE. In the touch peripheral area TPA, the sensing line RL may be disposed in a plural number, including a plurality of sensing lines RL, the first driving line TL1 may be disposed in a plural number, including a plurality of first driving lines TL1, and the second driving line TL2 may be disposed in a plural number, including a plurality of second driving lines TL 2. In an embodiment, the sensing electrode RE may be defined as a first sensing electrode, and the driving electrode TE may be defined as a second sensing electrode, in which case the sensing line RL may be defined as a first sensor line, and the first and second driving lines TL1 and TL2 may be defined as a second sensor line. Alternatively, the driving electrode TE may be defined as a first sensor electrode, and the sensing electrode RE may be defined as a second sensor electrode, in which case the first and second driving lines TL1 and TL2 may be defined as first sensor lines, and the sensing line RL may be defined as a second sensor line.

The sensing electrodes RE may be arranged in parallel along a first direction (or X-axis direction) and along a second direction (or Y-axis direction). The sensing electrodes RE may be electrically connected to each other along the first direction (or the X-axis direction). Pairs of the sensing electrodes RE adjacent to each other along the first direction (or the X-axis direction) may be connected to each other. Pairs of the sensing electrodes RE adjacent to each other along the second direction (or the Y-axis direction) may be electrically insulated from each other.

The driving electrodes TE may be arranged in parallel along the first direction (or X-axis direction) and along the second direction (or Y-axis direction). The driving electrodes TE may be electrically connected to each other along the second direction (or the Y-axis direction). The pairs of driving electrodes TE adjacent to each other along the second direction (or the Y-axis direction) may be connected to each other. The pairs of driving electrodes TE adjacent to each other along the second direction (or the Y-axis direction) may be connected to each other by the first connection portion CE 1. The first connection part CE1 may be provided in plural, including a plurality of first connection parts CE 1.

The first connection portion CE1 may have a planar shape bent at least once in a plan view. Fig. 4 shows that each of the first connection parts CE1 has the shape of an angular bracket (such as "<" or ">), but the planar shape of the first connection part CE1 is not particularly limited. Since the pairs of driving electrodes TE adjacent to each other in the second direction (or the Y-axis direction) are connected by the plurality of first connection portions CE1, the driving electrodes TE can be stably connected to each other in the second direction (or the Y-axis direction) even if one of the first connection portions CE1 is disconnected. Fig. 4 shows that two driving electrodes TE adjacent to each other along the second direction are connected to each other through one of the first connection portions CE1 including two angled supports, but the number of the first connection portions CE1 is not particularly limited.

Due to the presence of the first connection portion CE1, the driving electrode TE and the sensing electrode RE may be electrically insulated at the intersection therebetween. Thus, a mutual capacitance may be provided or formed between the drive electrode TE and the sense electrode RE.

Referring to fig. 4, the planar shape of the dummy pattern DE may be surrounded by the planar shape of the driving electrode TE or the sensing electrode RE. The dummy pattern DE may be electrically isolated from the driving electrode TE or the sensing electrode RE. The dummy pattern DE may be spaced apart from the driving electrode TE or the sensing electrode RE. The dummy pattern DE may be electrically floated.

Fig. 4 shows that the driving electrodes TE, the sensing electrodes RE, and the dummy patterns DE each have a diamond shape in a plan view, but are not limited thereto. Alternatively, the driving electrodes TE, the sensing electrodes RE, and/or the dummy patterns DE may have various other planar shapes other than the diamond shape in plan view, such as a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape.

A plurality of sensor lines SL may be disposed in the touch peripheral area TPA. The plurality of sensor lines SL may include: a sensing line RL connected to the sensing electrode RE, and a first driving line TL1 and a second driving line TL2 connected to the driving electrode TE. The sensing line RL may be defined as a first sensor line, and the first and second driving lines TL1 and TL2 may be defined as a second sensor line.

The sensing electrodes RE disposed on one side of the touch sensing region TSA may be connected to the sensing lines RL one to one. In an embodiment, for example, referring to fig. 4, a group of sensing electrodes RE electrically connected to each other along the first direction (or X-axis direction) may be connected to the sensing line RL at the right end of the touch sensing area TSA. The second sensor pads TP2 may be disposed in a plural manner in the touch peripheral area TPA, including a plurality of second sensor pads TP 2. The sensing lines RL may be connected to the second sensor pads TP2 one to one. Accordingly, the touch driving circuit may be electrically connected to the sensing electrode RE at the second sensor pad TP 2.

A group of driving electrodes TE electrically connected to each other along the second direction (or Y-axis direction) may be connected to the first driving line TL1 at a first side of the touch sensing area TSA and may be connected to the second driving line TL2 at a second side of the touch sensing area TSA opposite to the first side thereof. Referring to fig. 4, for example, a set of drive electrodes TE may be connected to a first drive line TL1 at a lower end (e.g., a first side) of the touch sensing area TSA and to a second drive line TL2 at an upper end (e.g., a second side) of the touch sensing area TSA. The second driving line TL2 may be connected to the driving electrode TE on an upper side of the touch sensing area TSA via an outer left side of the touch sensing area TSA.

The first and second driving lines TL1 and TL2 may be respectively connected to the first sensor pad TP1 one-to-one. Accordingly, the touch driving circuit may be electrically connected to the driving electrode TE at the first sensor pad TP 1. Since the driving electrodes TE are connected to the first and second driving lines TL1 and TL2 at the corresponding sides of the touch sensing area TSA and each of the driving electrodes TE receives the touch driving signal, an electrical difference between the touch driving signal applied to the driving electrodes TE disposed on the lower side of the touch sensing area TSA and the touch driving signal applied to the driving electrodes TE disposed on the upper side of the touch sensing area TSA due to resistance-capacitance ("RC") delay in the touch driving signal may be reduced or effectively prevented.

The touch peripheral area TPA further includes a display pad area DPA in which display pads DP including a plurality of display pads DP arranged in a plural number are disposed. The display pad DP may be connected to the data signal line DLS in the display area DA of the display panel 100.

The first sensor pad region TPA1 may be disposed at a first end of the display pad region DPA including the display pad DP, and include the first sensor pad TP 1. The second sensor pad region TPA2 may be disposed at a second end of the display pad region DPA opposite to the first end of the display pad region DPA, and include second sensor pads TP 2. The first sensor pad area TPA1, the display pad area DPA, and the second sensor pad area TPA2 may together form a pad area of the display panel 100.

The display pad region DPA, the first sensor pad region TPA1, and the second sensor pad region TPA2 and their components may be disposed on the first surface of the substrate SUB at a lower side of the display panel 100 along the second direction in a plan view. The circuit board 300 may be disposed on a second surface (e.g., a rear surface) of the substrate SUB opposite to the first surface in a thickness direction of the display device 10 to correspond to each of the display pad DP, the first sensor pad TP1, and the second sensor pad TP 2. The display pad DP, the first sensor pad TP1, and the second sensor pad TP2 may face the circuit board 300 with the substrate SUB and the conductive adhesive member CAM therebetween. The display pad DP, the first sensor pad TP1, and the second sensor pad TP2 may be electrically connected to the circuit board 300 through the substrate SUB and the conductive adhesive member CAM.

As shown in fig. 4, the touch sensing region TSA may include driving electrodes TE and sensing electrodes RE. Accordingly, the mutual capacitance between the driving electrode TE and the sensing electrode RE may be used to detect the presence of a touch input or an object from outside the display device 10 and/or the display panel 100.

Fig. 5 is an enlarged plan view illustrating an embodiment of the driving electrode TE, the sensing electrode RE, and the first connection portion CE1 of fig. 4. Specifically, fig. 5 is an enlarged plan view of the region a of fig. 4.

Referring to fig. 5, the driving electrode TE, the sensing electrode RE, and the dummy pattern DE may be disposed in the same layer as each other and spaced apart from each other in a direction along the substrate SUB. That is, a gap may be provided or formed between the driving electrode TE and the sensing electrode RE spaced apart from each other. Further, gaps may be disposed or formed between the driving electrodes TE and the dummy patterns DE and between the sensing electrodes RE and the dummy patterns DE in a direction along the substrate SUB. The elements in the same layer may be respective portions or respective patterns of the same material layer.

The first connection portion CE1 may be disposed in a different layer from the driving electrode TE and the sensing electrode RE. The first connection portion CE1 may overlap, along the third direction (or Z-axis direction), a corresponding pair of driving electrodes TE, which are adjacent to each other along the second direction (or Y-axis direction) and connected to each other through the first connection portion CE 1. The first connection portion CE1 may not overlap the sensing electrode RE in the third direction (or the Z-axis direction). A first end of each of the first connection portions CE1 may be connected to one of a pair of driving electrodes TE adjacent to each other along the second direction (or Y-axis direction) via a first touch contact hole TCNT1 (e.g., a contact hole), and a second end of each of the first connection portions CE1 may be connected to the other of the pair of driving electrodes TE via the other of the first touch contact hole TCNT 1.

In a plan view, the driving electrode TE, the sensing electrode RE, and the first connection portion CE1 may each be disposed or formed in a mesh or fish net structure. Further, the dummy patterns DE may be disposed or formed in a net or fish net structure in a plan view. The mesh or fishnet structure may be defined by solid portions defining openings therebetween.

Accordingly, the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the dummy pattern DE may not overlap with an emission area (e.g., a light emission area) where light is emitted from the display panel 100. In detail, the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the solid portion of the dummy pattern DE may not overlap with the emission area. Accordingly, since the emission area is not blocked by the solid portions of the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the dummy pattern DE, a decrease in luminance of light emitted from the emission area may be reduced or effectively prevented.

Alternatively, the driving electrodes TE, the sensing electrodes RE, the first connection portions CE1, and the dummy patterns DE may be disposed or formed as a surface (e.g., a single solid portion) in plan view, instead of being disposed or formed in a mesh or fish-net structure. In order to prevent a reduction in the brightness of light emitted from the emission region due to the solid portions of the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the dummy pattern DE, the materials of the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the dummy pattern DE may include a transparent conductive material, such as indium tin oxide ("ITO") or indium zinc oxide ("IZO").

The emission area may include: a first emission region E1 disposed in a plural manner, including a plurality of first emission regions E1 that emit light of a first color; a second emission region E2 disposed in a plural manner, including a plurality of second emission regions E2 that emit light of a second color different from the first color; and a third emission region E3 disposed in a plural number, including a plurality of third emission regions E3 that emit light of a third color different from the first color and the second color. In an embodiment, for example, the first color may be red, the second color may be green, and the third color may be blue. The emission regions may respectively correspond to the display pixels in the display region DA, without being limited thereto.

The first emission region E1, the second emission region E2, and the third emission region E3 may each have a diamond or rectangular shape in a plan view, but are not limited thereto. Alternatively, the first emission region E1, the second emission region E2, and the third emission region E3 may have various other planar shapes other than a rectangular shape in plan view, such as a polygonal shape, a circular shape, or an elliptical shape.

Each of the first emission region E1, the second emission region E2, and the third emission region E3 has a size (e.g., a planar size) in a plan view. Among the sizes of the first, second, and third emission regions E1, E2, and E3, fig. 5 illustrates that the size of the third emission region E3 is the largest size and the size of the second emission region E2 is the smallest size, but is not limited thereto.

One of the first emission regions E1, two of the second emission regions E2, and one of the third emission regions E3 may be defined as a pixel emission group PXG that emits light to represent white gray. That is, the white gray may be represented by light emitted from one of the first emission regions E1, light emitted from two of the second emission regions E2, and light emitted from one of the third emission regions E3.

The emission regions may be arranged in rows extending along the first direction (or X-axis direction) and columns extending along the second direction (or Y-axis direction). Each emission area may have a side defining an outer edge of the emission area. The side may extend obliquely with respect to the first direction (or X-axis direction) and/or the second direction (or Y-axis direction).

The second emission regions E2 may be arranged in odd-numbered rows. The second emission regions E2 may be arranged side by side along the first direction (or X-axis direction) in odd-numbered rows. The second emission regions E2 arranged side by side along the first direction may form a group of emission regions. In each of the odd-numbered rows, one of each pair of second emission regions E2 adjacent to each other along the first direction (or the X-axis direction) may have a long side extending along the first inclination direction DR1 and a short side extending along the second inclination direction DR 2. However, the other of each pair of second emission regions E2 may have a long side extending along the second inclination direction DR2 and a short side extending along the first inclination direction DR 1. The first inclined direction DR1 may be a direction between the first direction (or X-axis direction) and the second direction (or Y-axis direction), and the second inclined direction DR2 may be a direction intersecting the first inclined direction DR 1.

The first and third emission regions E1 and E3 may be arranged in even rows. The first and third emission regions E1 and E3 may be arranged side by side in the first direction (or X-axis direction) in even-numbered rows. The first emission regions E1 arranged side by side along the first direction may form a group of emission regions, and the third emission regions E3 arranged side by side along the first direction may form a group of emission regions. The first and third emission regions E1 and E3 may be alternately arranged in even-numbered rows.

The second emission regions E2 may be arranged in odd columns. The second emission regions E2 may be arranged side by side along the second direction (or Y-axis direction) within the odd-numbered columns. In each of the odd columns, one of each pair of second emission regions E2 adjacent to each other along the second direction (or Y-axis direction) may have a long side extending along the first inclination direction DR1 and a short side extending along the second inclination direction DR 2. However, the other of each pair of second emission regions E2 may have a long side extending along the second inclination direction DR2 and a short side extending along the first inclination direction DR 1.

The first and third emission regions E1 and E3 may be arranged in even columns. The first emission regions E1 and the third emission regions E3 may be arranged side by side in even-numbered columns. The first emission regions E1 and the third emission regions E3 may be alternately arranged along even columns.

Fig. 6 is a sectional view taken along line I-I' of fig. 5.

Referring to fig. 6, a display layer DISL including a TFT layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL may be sequentially disposed on a substrate SUB. A sensor electrode layer sensl including the sensor electrode SE may be disposed on the display layer DISL. That is, the sensor electrode layer SENL faces the substrate SUB, and the display layer DISL is provided between the sensor electrode layer SENL and the substrate SUB.

The first buffer layer BF1 may be disposed on the first surface of the substrate SUB, and the second buffer layer BF2 may be disposed on the first buffer layer BF 1. The first buffer layer BF1 and the second buffer layer BF2 may be sequentially disposed on the first surface of the substrate SUB to protect the TFT ST of the TFT layer TFTL, which is susceptible to moisture, and the light emitting layer 172 (e.g., light emitting pattern) of the light emitting element layer EML from moisture that may penetrate the substrate SUB.

Each of the first buffer layer BF1 and the second buffer layer BF2 may include a plurality of inorganic material layers stacked along a thickness direction of the display panel 100 (e.g., in a direction away from the substrate SUB). In an embodiment, for example, each of the first buffer layer BF1 and the second buffer layer BF2 may be formed in a multilayer structure in which one or more inorganic material layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked. In embodiments, one of the first buffer layer BF1 and the second buffer layer BF2 may be omitted.

The first light blocking layer BML (e.g., a first light blocking pattern) may be disposed in plural along the substrate SUB, including a plurality of first light blocking layers BML disposed on the first buffer layer BF 1. The first light blocking layer BML may include or be formed in a single-layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. Alternatively, the first light blocking layer BML may be an organic material layer including a black pigment.

The active layer ACT (e.g., active layer pattern) may be disposed in plural along the substrate SUB, including the active layer ACT of the plurality of TFTs ST disposed on the second buffer layer BF 2. The active layer ACT may include polysilicon, single crystal silicon, low temperature polysilicon ("LTPS"), amorphous silicon, or an oxide semiconductor material. In the active layer ACT including polysilicon or an oxide semiconductor material, the ion-doped region of the active layer ACT may be a conductive region having conductivity.

The active layer ACT may overlap or correspond to the first light blocking layer BML along the third direction (or Z-axis direction). Since light incident through the substrate SUB may be blocked by the first light blocking layer BML, a leakage current flowing into the active layer ACT due to the incident light may be reduced or effectively prevented.

A gate insulating layer 130 may be disposed or formed on the active layer ACT. The gate insulating layer 130 may include an inorganic material layer such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, or an inorganic material layer formed such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The gate electrodes G may be disposed in a plural number, including the gate electrodes G of the plurality of TFTs ST disposed on the gate insulating layer 130. The gate electrode G of the TFT ST may overlap with or correspond to the active layer ACT along the third direction (or the Z-axis direction), respectively. The gate electrode G may be disposed or formed in a single layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

The portion of the active layer ACT overlapping the gate electrode G in the third direction (or the Z-axis direction) may be a plurality of channel regions CHA including channel regions CHA arranged in a plural number. The active layer ACT may include first and second conductive regions COA1 and COA2 each disposed in a plural number, including a plurality of first and second conductive regions COA1 and COA2, respectively, extending from opposite sides of the channel region CHA.

The first interlayer insulating layer 141 may be disposed on the gate electrode G. The first interlayer insulating layer 141 may be disposed or formed as an inorganic material layer such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating layer 141 may include a plurality of inorganic material layers.

The capacitance electrode CAE may be disposed in a plural manner, including a plurality of capacitance electrodes CAE that may be disposed on the first interlayer insulating layer 141. The capacitor electrode CAE may overlap or respectively correspond to the gate electrode G along the third direction (or Z-axis direction). The capacitor electrode CAE may be disposed or formed in a single layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

The second interlayer insulating layer 142 may be disposed on the capacitor electrode CAE. The second interlayer insulating layer 142 may be disposed or formed as an inorganic material layer such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 142 may include a plurality of inorganic material layers.

The first electrodes S and the second electrodes D may each be disposed in a plural number, including a plurality of first electrodes S and a plurality of second electrodes D of the TFT ST disposed on the second interlayer insulating layer 142. The first and second electrodes S and D may be formed in a single layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

The first electrode S of the TFT ST may be respectively connected to the first conductive region COA1 through contact holes penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142, and the first conductive region COA1 is disposed to extend from a first side of the channel region CHA of the active layer ACT. The second electrode D of the TFT ST may be connected to a second conductive region COA2 through contact holes penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142, respectively, and the second conductive region COA2 is disposed to extend from a second side of the channel region CHA of the active layer ACT.

The first organic layer 150 for planarizing a height difference formed by the TFT ST may be disposed on the first electrode S and the second electrode D. The first organic layer 150 may be disposed or formed as an organic material layer including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The first connection electrode ANDE1 (e.g., connection electrode) may be disposed in a plural manner, including a plurality of first connection electrodes ANDE1 disposed on the first organic layer 150. The first connection electrodes ANDE1 may be respectively connected to the second electrodes D of the TFTs ST through contact holes penetrating the first organic layer 150. The first connection electrode ANDE1 may be provided or formed in a single layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

The second organic layer 160 may be disposed on the first connection electrode ANDE 1. The second organic layer 160 may be disposed or formed as an organic material layer including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

Fig. 6 shows that the TFT ST is disposed or formed as a top gate TFT in which the gate electrode G is disposed above the active layer ACT (for example, the gate electrode G is disposed farther from the substrate SUB than the active layer ACT), but is not limited thereto. Alternatively, the TFT ST may be formed as a bottom gate TFT in which the gate electrode G is disposed below the active layer ACT (for example, the gate electrode G is disposed closer to the substrate SUB than the active layer ACT), or as a dual gate TFT in which the gate electrode G is disposed both above and below the active layer ACT.

The light emitting element layer EML is disposed on the TFT layer TFTL. The light emitting element layer EML may include a light emitting element 170 and a third organic layer 180 sequentially disposed from the substrate SUB, wherein the light emitting element 170 is disposed in a plural manner, including a plurality of light emitting elements 170.

Each of the light emitting elements 170 may include a first light emitting electrode 171, a light emitting layer 172, and a second light emitting electrode 173. The first light emitting electrode 171 faces the second light emitting electrode 173, and a light emitting layer 172 is provided between the first light emitting electrode 171 and the second light emitting electrode 173. Each of the second and third emission regions E2 and E3 may be a region in which the first light emitting electrode 171, the light emitting layer 172, and the second light emitting electrode 173 are sequentially stacked in a thickness direction of the display panel 100, so that holes from the first light emitting electrode 171 and electrons from the second light emitting electrode 173 may combine in the light emitting layer 172 to generate and emit light. In this case, the first light emitting electrode 171 may be an anode electrode, and the second light emitting electrode 173 may be a cathode electrode.

The first light emitting electrodes 171 may be disposed in a plurality along the substrate SUB, including a plurality of first light emitting electrodes 171 disposed or formed on the second organic layer 160. The first light emitting electrodes 171 may be respectively connected to the first connection electrodes ANDE1 through contact holes penetrating the second organic layer 160.

In the top emission structure in which the light emitting element 170 emits light in a direction from the light emitting layer 172 of the light emitting element 170 to the second light emitting electrode 173, the first light emitting electrode 171 may be disposed or formed as a single material layer of Mo, Ti, Cu, or Al, or may be disposed or formed as a stacked material layer of Al and Ti (e.g., Ti/Al/Ti), Al and ITO (e.g., ITO/Al/ITO), silver (Ag) -palladium (Pd) -copper (Cu) (APC) alloy, or APC alloy and ITO (e.g., ITO/APC/ITO).

The third organic layer 180 defines a second emission region E2 and a third emission region E3. For this, a third organic layer 180 may be disposed or formed on the second organic layer 160 to expose a portion of the first light emitting electrode 171 of the light emitting element 170 at each emission region. The third organic layer 180 may cover an edge of each of the first light emitting electrodes 171. The third organic layer 180 may be disposed or formed as an organic material layer including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The light emitting layers 172 are respectively disposed or formed on the first light emitting electrodes 171. The light emitting layer 172 may include an organic material to emit light of a predetermined color. In an embodiment, for example, the light emitting layers 172 may each include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a matrix and a dopant. The organic material layer may include a material capable of emitting light of a predetermined color, and may include or be formed of a phosphorescent material or a fluorescent material.

In an embodiment, for example, the organic material layer of the emission layer 172 emitting light of the first color disposed or formed in the first emission region E1 (of fig. 5) may include or be formed of a phosphorescent material, wherein the phosphorescent material includes a matrix material including carbazole biphenyl ("CBP") or 1, 3-bis (carbazol-9-yl) benzene ("mCP") and at least one dopant material selected from bis (1-phenylisoquinoline) iridium acetylacetonate (piqir (acac)), bis (1-phenylquinoline) iridium acetylacetonate (pqicac), tris (1-phenylquinoline) iridium (PQIr), and platinum octaethylporphyrin (PtOEP). In an embodiment, the organic material layer of the emission layer 172 disposed or formed in the first emission region E1 (of fig. 5) may include or be formed of a fluorescent material including PBD: eu (DBM)₃(Phen) or perylene. However, the embodiments are not limited to these examples.

In an embodiment, for example, the organic material layer of the light emitting layer 172 emitting light of the second color disposed or formed in the second emission region E2 may include or be formed of a phosphorescent material including a host material including CBP or mCP and a dopant material including planar tris (2-phenylpyridine) iridium (ir (ppy)₃). In embodiments, the organic material layer of the light emitting layer 172 disposed or formed in the second emission region E2 may include or be formed of a fluorescent material including tris (8-hydroxyquinoline) aluminum (Alq)₃). However, the embodiments are not limited to these examples.

In an embodiment, for example, the organic material layer of the light emitting layer 172 emitting light of the third color disposed or formed in the third emission region E3 may include or be formed of a phosphorescent material including a host material including CBP or mCP and a dopant material including (4, 6-F)₂ppy)₂Irpic or L2BD 111. However, the embodiments are not limited to this example.

The second light emitting electrode 173 may be disposed or formed on the light emitting layer 172. The second light emitting electrode 173 may be disposed or formed to cover the light emitting layer 172. The second light emitting electrode 173 may be a common layer corresponding to all display pixels. A capping layer (not shown) may be disposed or formed on the second light emitting electrode 173.

In the top emission structure, the second light emitting electrode 173 may include or be formed of a transparent conductive oxide ("TCO") material such as ITO or IZO or a semi-transparent metal material such as magnesium (Mg), Ag or an alloy thereof. The second light emitting electrode 173 including or formed of a semitransparent metal material provides improved emission efficiency of the light emitting element 170 due to the microcavity.

The light emitting layer 172 may be disposed on the top surface of the first light emitting electrode 171 and on the inclined surface of the third organic layer 180. The second light emitting electrode 173 may be disposed on the top surface of the light emitting layer 172 and on the inclined surface of the third organic layer 180. The top surface may be the surface furthest from the substrate SUB.

The encapsulation layer TFEL may be disposed or formed on the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic material layer to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The encapsulation layer TFEL may further include at least one organic material layer to protect the light emitting element layer EML from foreign substances such as dust. The inorganic material layer may be disposed or formed in a multi-layered structure in which one or more inorganic material layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked. The organic material layer may include or be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The sensor electrode layer SENL is disposed on the encapsulation layer TFEL. The sensor electrode layer sens may include a sensor electrode SE.

A third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may be a layer having insulating and optical functions. The third buffer layer BF3 may include at least one inorganic material layer. In an embodiment, for example, the third buffer layer BF3 may be disposed or formed in a multilayer structure in which one or more inorganic material layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked. The third buffer layer BF3 may be disposed or formed by a lamination process using a flexible material, a spin coating process using a solution type material, a slit die coating process, or a deposition process. In an embodiment, the third buffer layer BF3 may be omitted.

The first connection portion CE1 may be disposed on the third buffer layer BF 3. The first connection portion CE1 may be provided or formed as a single material layer of Mo, Ti, Cu, or Al, or may be formed as a stacked material layer of Al and Ti (e.g., Ti/Al/Ti), Al and ITO (e.g., ITO/Al/ITO), APC alloy, or APC alloy and ITO (e.g., ITO/APC/ITO).

The first sensor insulating layer TINS1 may be disposed on the first connection portion CE 1. The first sensor insulating layer TINS1 may be a layer having insulating and optical functions. The first sensor insulating layer TINS1 may be disposed or formed as an inorganic material layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first sensor insulating layer TINS1 may be disposed or formed by a lamination process using a flexible material, a spin coating process using a solution type material, a slot die coating process, or a deposition process.

The driving electrode TE and the sensing electrode RE may be disposed on the first sensor insulation layer TINS1, i.e., in the same layer on the first sensor insulation layer TINS 1. The driving electrode TE and the sensing electrode RE may not overlap the second emission region E2 and the third emission region E3. The driving electrode TE and the sensing electrode RE may be disposed or formed as a single layer of Mo, Ti, Cu, or Al, or may be disposed or formed as stacked material layers of Al and Ti (e.g., Ti/Al/Ti), Al and ITO (e.g., ITO/Al/ITO), APC alloy, or APC alloy and ITO (e.g., ITO/APC/ITO).

A second sensor insulating layer TINS2 may be disposed on the driving electrode TE and the sensing electrode RE. The second sensor insulating layer TINS2 may face the first sensor insulating layer TINS1 with the drive electrode TE and the sense electrode RE between the second sensor insulating layer TINS2 and the first sensor insulating layer TINS 1. The second sensor insulating layer TINS2 may be a layer having insulating and optical functions. The second sensor insulating layer TINS2 may include at least one of an inorganic material layer and an organic material layer. The inorganic material layer may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic material layer may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second sensor insulating layer TINS2 may be disposed or formed by a lamination process using a flexible material, a spin coating process using a solution type material, a slot die coating process, or a deposition process. Referring to fig. 6, the driving electrode TE and the sensing electrode RE may be disposed in the same layer as each other, and may simultaneously include or be formed of the same material so as to be respective portions of the same material layer.

How to connect the conductive lines via the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 within the display device 10 will be described below.

Fig. 7 is a plan view illustrating an embodiment of a pad region of the display device 10 of fig. 1. Fig. 8 is a sectional view taken along line II-II' of fig. 7. Fig. 9 is an enlarged sectional view illustrating a region B of fig. 8. Fig. 10 is a sectional view taken along line III-III' of fig. 7.

Referring to fig. 7, the pad region may be disposed in the non-display region NDA of the substrate SUB. The signal lines disposed in a plural manner including a plurality of lines disposed in the display area DA may extend from the display area DA to the non-display area NDA to dispose distal ends of the plurality of lines in the display pad area DPA. The distal ends of the plurality of lines may define conductive pads in the non-display area NDA, respectively. The plurality of lines may include gate signal lines GLS arranged in a complex number including a plurality of gate signal lines GLS and data signal lines DLS arranged in a complex number including a plurality of data signal lines DLS.

The non-display area NDA may further include a plurality of lines including a power line VDS and a sensing line RL. The plurality of lines may extend from a portion of the non-display area NDA not including the pad area into the pad area. In an embodiment, the sensing line RL may extend into the second sensor pad area TPA 2. The power supply line VDS may extend into the display pad area DPA or the second sensor pad area TPA 2. Fig. 7 shows only a part of the pad region, and various lines other than those shown in fig. 7 may be provided in the pad region.

The gate signal line GLS may extend from the gate signal line GLS in the display area DA, and may be a conductive line through which an electric signal such as a gate signal is applied to the display pixels in the display area DA. The data signal lines DLS may extend from the data signal lines DLS in the display area DA, and may be conductive lines through which an electric signal such as a data signal is applied to the display pixels in the display area DA.

The power supply line VDS may extend from a first power supply line (e.g., a power supply line) in the display area DA, and may be a conductive line through which an electric signal such as a power supply voltage is applied to the display area DA. The sensing line RL may extend from the sensing electrode RE in the display area DA and may be a conductive line through which an electrical signal such as a touch sensing signal is applied to and/or output from the display area DA.

The pad region includes: gate line pads GP arranged in plural, including a plurality of gate line pads GP connected to the gate signal lines GLS; a data line pad DLP provided in a plural form including a plurality of data line pads DLP connected to the data signal line DLS; a power supply pad VDP connected to the power supply line VDS; and a second sensor pad TP2 connected to the sensing line RL. The gate line pad GP may be an extension of the gate signal line GLS and may include the same material as the gate signal line GLS, the data line pad DLP may be an extension of the data signal line DLS and may include the same material as the data signal line DLS, the power supply pad VDP may be an extension of the power supply line VDS and may include the same material as the power supply line VDS, and the second sensor pad TP2 may be an extension of the sensing line RL and may include the same material as the sensing line RL. Because they comprise the same material, the elements may be in the same layer as each other so as to be a corresponding pattern of the same material layer.

In plan view, the pad region may include a length along a first direction (e.g., an X-axis direction in fig. 4). The length of the pad region may extend along the edge of the display panel 100. The gate signal line GLS, the gate line pad GP, the data signal line DLS, the data line pad DLP, the power line VDS, the power supply pad VDP, the sensing line RL, and the second sensor pad TP2 may each have a width along a length direction of the pad region and/or an edge of the display panel 100. The gate line pad GP may have a width greater than that of the gate signal line GLS, the data line pad DLP may have a width greater than that of the data signal line DLS, the power supply pad VDP may have a width greater than that of the power supply line VDS, and the second sensor pad TP2 may have a width greater than that of the sensing line RL. However, the embodiment is not limited thereto. Alternatively, the widths of the gate line pad GP, the data line pad DLP, the power supply pad VDP, and the second sensor pad TP2 may be the same as or smaller than the widths of the gate signal line GLS, the data signal line DLS, the power supply line VDS, and the sensing line RL, respectively.

The gate line pad GP, the data line pad DLP, the power supply pad VDP, and the second sensor pad TP2 on the first surface of the substrate SUB may be electrically connected to the circuit board 300 disposed under the substrate SUB (e.g., on the second surface of the substrate SUB) through the substrate SUB.

Referring to fig. 8 and 9, the TFT ST, the light emitting element 170, and the sensor electrode layer SENL may be disposed in the display area DA of the substrate SUB. A portion of the gate signal line GLS and the gate line pad GP may be disposed in the non-display area NDA of the substrate SUB.

The substrate SUB may include a base layer such as a polymer resin PSM in which the first conductive balls CM1 are dispersed to provide conductivity within the substrate SUB, and first conductive balls CM 1. The first conductive balls CM1 may be randomly dispersed in the polymer resin PSM.

The polymer resin PSM may include polyimide ("PI"), polyethersulfone ("PES"), polyacrylate ("PA"), polyarylate ("PAR"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyallyl ester, polycarbonate ("PC"), cellulose triacetate ("CAT"), cellulose acetate propionate ("CAP"), or combinations thereof.

Each of the first conductive balls CM1 may include a core and a conductive film surrounding the core. The core of the first conductive ball CM1 may be elastic. Accordingly, the core of the first conductive balls CM1 may remain in contact with the second conductive balls CM2 of the conductive adhesive member CAM, and thus be electrically connected to the second conductive balls CM2 of the conductive adhesive member CAM. The conductive film of first conductive ball CM1 may include or be formed of a conductive material, such as gold (Au), nickel (Ni), or a bi-layer of Au and Ni.

In the non-display region NDA of the substrate SUB, the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 may be sequentially stacked. The gate signal line GLS and the gate line pad GP may be disposed on the gate insulating layer 130. The first pad hole PH1 may extend through the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 to expose the first surface of the substrate SUB. The gate line pad GP may be electrically connected to the substrate SUB through the first pad hole PH 1. That is, the gate line pad GP may fill the first pad hole PH1 to be in contact with the top surface of the substrate SUB at the first pad hole PH 1.

The conductive adhesive member CAM may be disposed at a position of the substrate SUB corresponding to the non-display area NDA. The conductive adhesive member CAM may not overlap the display area DA. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300 to each other.

The conductive adhesive member CAM may include a base layer such as an adhesive resin ADR and a plurality of second conductive balls CM2 (e.g., second conductive members) disposed in a plurality, the second conductive balls CM2 including a plurality of second conductive balls CM2, the plurality of second conductive balls CM2 being dispersed in the adhesive resin ADR. The adhesive resin ADR may include or be formed of a thermosetting resin such as an epoxy resin. The second conductive ball CM2 may include the same structure as the first conductive ball CM1 described above.

The circuit board 300 to which the display driving circuit 200 is attached may be disposed below the conductive adhesive member CAM. That is, the display driving circuit 200 may face the conductive adhesive member CAM with the circuit board 300 therebetween. The circuit board 300 may include a first bump electrode BPE1 on a first surface of the circuit board 300. The first bump electrode BPE1 may be disposed on a first surface of the circuit board 300 facing the substrate SUB, and the display driving circuit 200 may be disposed on a second surface of the circuit board 300 opposite to the first surface thereof.

In the non-display area NDA, the conductive adhesive member CAM may overlap the gate signal line GLS and the gate line pad GP. The conductive adhesive member CAM may overlap or correspond to each of the circuit board 300 and the first bump electrode BPE1 along the thickness direction of the display panel 100.

The gate line pad GP, the first conductive ball CM1, the second conductive ball CM2, and the first bump electrode BPE1 may be electrically contacted with each other, such as by thermal compression. That is, the gate line pad GP may be in contact with the first conductive balls CM1 of the substrate SUB, the first conductive balls CM1 may be in contact with the second conductive balls CM2 of the conductive adhesive member CAM, and the second conductive balls CM2 may be in contact with the first bump electrode BPE1 of the circuit board 300. That is, in the non-display area NDA, the circuit board 300 is electrically connected to the signal lines by the contact of the circuit board 300 with the conductive adhesive member CAM and the contact of the conductive material in the substrate SUB with both the signal lines and the conductive adhesive member CAM.

In an embodiment, during the thermal pressing, the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be compressed in a thickness direction of the display panel 100 in a region of the circuit board 300 overlapping or corresponding to the first bump electrodes BPE1 of the circuit board 300. Accordingly, the gate line pad GP may be electrically connected to the circuit board 300 through the substrate SUB.

The entirety of the substrate SUB may include locations that are conductive, such as by conductive material within the base layer (e.g., first conductive balls CM 1). The first conductive balls CM1 of the substrate SUB may be thermally pressed only at positions of the substrate SUB aligned with the positions of the first bump electrodes BPE1 of the circuit board 300, and thus may be electrically connected to the second conductive balls CM2 at positions corresponding to the first bump electrodes BPE 1. Therefore, even if the entirety of the substrate SUB includes a position to be electrically conductive through the first conductive balls CM1, the entirety of the substrate SUB may not necessarily exhibit electrical conductivity but may be functionally conductive only in the region of the circuit board 300 at the first bump electrode BPE1 thereof.

The data line pad DLP may be electrically connected to the circuit board 300 through the substrate SUB and the conductive adhesive member CAM.

Referring to fig. 10, the data signal line DLS and the data line pad DLP may be disposed in the non-display area NDA of the substrate SUB.

In the non-display region NDA of the substrate SUB, the first buffer layer BF1, the second buffer layer BF2, the gate insulating layer 130, the first interlayer insulating layer 141, the second interlayer insulating layer 142, and the first organic layer 150 may be sequentially stacked. The data signal line DLS and the data line pad DLP may be disposed on the second interlayer insulating layer 142. The second pad hole PH2 may extend through the first buffer layer BF1, the second buffer layer BF2, the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 to expose the top surface of the substrate SUB. The data line pad DLP may be electrically connected to the substrate SUB through the second pad hole PH 2. That is, the data line pad DLP may fill the second pad hole PH2 and may be in contact with the top surface of the substrate SUB.

The conductive adhesive member CAM may be disposed at a position of the substrate SUB corresponding to the non-display area NDA. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300 to each other. The circuit board 300 to which the display driving circuit 200 is attached may be disposed below the conductive adhesive member CAM. The circuit board 300 may further include a second bump electrode BPE2 on the first surface of the circuit board 300. The second bump electrode BPE2 may be disposed on a first surface of the circuit board 300 facing the substrate SUB, and the display driving circuit 200 may be disposed on a second surface of the circuit board 300 opposite to the first surface thereof.

In the non-display area NDA, the conductive adhesive member CAM may overlap the data signal line DLS and the data line pad DLP. The conductive adhesive member CAM may overlap or correspond to each of the circuit board 300 and the second bump electrode BPE2 along the thickness of the display panel 100.

The data line pad DLP, the first conductive ball CM1, the second conductive ball CM2, and the second bump electrode BPE2 may be electrically contacted with each other, such as by thermal compression. That is, the data line pad DLP may be in contact with the first conductive ball CM1 of the substrate SUB, the first conductive ball CM1 may be in contact with the second conductive ball CM2 of the conductive adhesive member CAM, and the second conductive ball CM2 may be in contact with the second bump electrode BPE2 of the circuit board 300.

In an embodiment, during the hot pressing, the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be compressed in a thickness direction of the display panel 100 in a region of the circuit board 300 overlapping or corresponding to the second bump electrode BPE2 of the circuit board 300. Accordingly, the data line pad DLP may be electrically connected to the circuit board 300 through the substrate SUB.

As described above, the entirety of the substrate SUB may include a position such as to be electrically conductive by the conductive material (e.g., the first conductive ball CM1), but the conductive function is provided only in the region of the circuit board 300 at the second bump electrode BPE2 including the thermally compressed first conductive ball CM 1. Therefore, even if the entirety of the substrate SUB includes a position to be electrically conductive through the first conductive balls CM1, the entirety of the substrate SUB may not necessarily exhibit electrical conductivity but may be functionally conductive only in the region of the circuit board 300 at the second bump electrode BPE2 thereof. In an embodiment, the substrate SUB may be functionally conductive only in a region of the circuit board 300 at the first and second bump electrodes BPE1 and BPE2 thereof.

Each of the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 may include an outer side surface. The outer side surfaces of the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 may be disposed to correspond to each other at the same side of the display device 10.

In an embodiment, the circuit board 300 under the substrate SUB and the conductive line over the substrate SUB, which are connected to each other through the substrate SUB, may be disposed such that the outer side surfaces of the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 are aligned and contacted with each other. That is, at the same side of the display device 10, the outer side surface of the substrate SUB may be aligned with and in contact with the outer side surface of the conductive adhesive member CAM, and the outer side surface of the conductive adhesive member CAM may be aligned with and in contact with the outer side surface of the circuit board 300. However, the embodiment is not limited thereto. Alternatively, the outer side surface of the conductive adhesive member CAM may be located inside the outer side surface of the substrate SUB, and/or the outer side surface of the circuit board 300 may be located inside the outer side surface of the substrate SUB. When inside, the elements may be spaced apart from other elements and closer to the display area DA than the other elements.

Accordingly, since the land area provided at the opposite surface of the substrate SUB and the circuit board 300 are connected to each other within the plane area of the substrate SUB, a plane such as a bending area where the circuit board 300 is bent from the first surface to the second surface along the outer side surface of the substrate SUB is eliminated. Therefore, the bezel size of the display device 10 can be reduced.

The sectional structures of the power supply pad VDP and the second sensor pad TP2 are not shown in fig. 10, but a description thereof will be omitted because they are substantially the same as the sectional structure of the data line pad DLP of fig. 10.

Fig. 11 is a cross-sectional view of an embodiment of the display device 10. Fig. 12 is a plan view of an embodiment of a substrate SUB of the display device 10 of fig. 11. Fig. 13 is a cross-sectional view of an embodiment of the display device 10 of fig. 11. Fig. 14 is an enlarged cross-sectional view of a portion of the display device 10 of fig. 13.

Referring to fig. 11 to 14, the display device 10 may include a substrate SUB including a conductive material providing a conductive function at a hot-pressing position. The display device 10 of fig. 11-14 is substantially the same as or similar to the display device 10 of fig. 3-10, except that the conductive material is disposed in only a portion of the substrate SUB. Therefore, the display device 10 of fig. 11 to 14 will be described hereinafter mainly focusing on differences from the display device 10 of fig. 3 to 10.

Referring to fig. 11 and 12, the display device 10 may include a display panel 100, a conductive adhesive member CAM, a display driving circuit 200, and a circuit board 300. The display panel 100 may include a substrate SUB, a display layer DISL, a sensor electrode layer SENL, and a polarizing film PF.

The substrate SUB may include a conductive material, for example, first conductive balls CM 1. The substrate SUB may include a first substrate region 20 and a second substrate region 30, the first substrate region 20 including or being formed of a polymer resin PSM, the second substrate region 30 being the remaining portion of the substrate SUB except the first substrate region 20. The first substrate region 20 and the second substrate region 30 may be disposed in the same plane (such as a plane defined by the first direction and the second direction). The edge of the first substrate region 20 may contact or meet the edge of the second substrate region 30. The first substrate region 20 may overlap with the light emitting element 170 of the display layer dil, and the second substrate region 30 may not overlap with the light emitting element 170.

The first substrate area 20 may be a planar area overlapping or corresponding to the display area DA and not including the first conductive balls CM 1. The first substrate region 20 may be a planar region including or formed of only the polymer resin PSM. The second substrate region 30 may be a planar region overlapping or corresponding to the non-display region NDA and including the polymer resin PSM and the first conductive balls CM1 dispersed in the polymer resin PSM. The second substrate area 30 may be disposed at an outer area of the substrate SUB and may be outside the plane of the display area DA. The second substrate area 30 may define an outer side surface of the substrate SUB.

Specifically, referring to fig. 13 and 14, the TFT ST, the light emitting element 170, and the sensor electrode layer SENL may be disposed in the display area DA of the substrate SUB. The gate signal lines GLS and the gate line pads GP may be disposed in the non-display area NDA of the substrate SUB.

The first substrate region 20 of the substrate SUB may overlap with the TFT ST, the light emitting element 170, and the sensor electrode layer SENL. The second substrate region 30 may not overlap the TFT ST and the light emitting element 170.

The first substrate region 20 may include only the polymer resin PSM to exhibit non-conductivity, and may not include the first conductive balls CM 1. The second substrate region 30 may include both the polymer resin PSM and the first conductive balls CM1 (conductive material dispersed in the polymer resin PSM) to exhibit conductivity. The first conductive balls CM1 may be randomly dispersed in the polymer resin PSM.

The first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 may be sequentially stacked on the second substrate region 30 of the substrate SUB. The gate signal line GLS and the gate line pad GP may be disposed on the gate insulating layer 130. A first pad hole PH1 exposing the substrate SUB to the outside of the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 may be provided. The gate line pad GP may be electrically connected to the substrate SUB through the first pad hole PH 1. That is, the gate line pad GP may fill the first pad hole PH1 to be in contact with the top surface of the substrate SUB at the first pad hole PH 1.

The conductive adhesive member CAM may be disposed under the second substrate region 30 of the substrate SUB. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300 to each other. The second substrate area 30 may overlap or correspond to the conductive adhesive member CAM and the circuit board 300. The conductive adhesive member CAM is spaced apart from the first substrate area 20 not including the conductive material in a direction along the substrate SUB.

The conductive adhesive member CAM may include an adhesive resin ADR and second conductive balls CM2 dispersed in the adhesive resin ADR. The circuit board 300 to which the display driving circuit 200 is attached may be disposed below the conductive adhesive member CAM. The first bump electrode BPE1 of the circuit board 300 may be disposed on a first surface of the circuit board 300, and the display driving circuit 200 may be disposed on a second surface of the circuit board 300 opposite to the first surface thereof.

The gate line pad GP, the first conductive ball CM1, the second conductive ball CM2, and the first bump electrode BPE1 may be thermally pressed together, and thus may be electrically contacted to each other. That is, the gate line pad GP may be in contact with the first conductive balls CM1 of the substrate SUB, the first conductive balls CM1 may be in contact with the second conductive balls CM2 of the conductive adhesive member CAM, and the second conductive balls CM2 may be in contact with the first bump electrode BPE1 of the circuit board 300. During the thermocompression, the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be compressed in a region of the circuit board 300 aligned with the first bump electrodes BPE1 of the circuit board 300. Accordingly, the gate line pad GP may be electrically connected to the circuit board 300 through the substrate SUB.

A portion of the substrate SUB (e.g., the second substrate region 30) may include first conductive balls CM 1. The first conductive ball CM1 may be thermocompressed only in a region where the circuit board 300 is aligned with the first bump electrode BPE1 of the circuit board 300, and thus may be electrically connected to the second conductive ball CM2 at the region of the circuit board 300. That is, the gate line pad GP of the display panel 100 and the first bump electrode BPE1 of the circuit board 300 may be electrically connected to each other by the second substrate region 30 including the first conductive balls CM1 and providing conductivity, which is disposed or formed in the region of the substrate SUB aligned with the display pad region DPA. Accordingly, the use of the conductive member may be reduced, and thus, the manufacturing cost of the display device 10 may be reduced.

Fig. 15 is a plan view of an embodiment of a substrate SUB of the display device 10. Fig. 16 is a sectional view of the display device 10 of fig. 15. Fig. 17 is a cross-sectional view of an embodiment of a portion of the display device 10 of fig. 15.

Referring to fig. 15 to 17, the display device 10 may include a substrate SUB including a conductive material. The display device 10 of fig. 15 to 17 is different from the display device 10 of fig. 3 to 14 in that a conductive material is provided as an island pattern (e.g., a discrete pattern) in a part of the substrate SUB. Therefore, the display device 10 of fig. 15 to 17 will be described below mainly focusing on differences from the display device 10 of fig. 3 to 14.

Referring to fig. 15, the substrate SUB of the display device 10 may include a conductive material, for example, first conductive balls CM 1. The substrate SUB may include a first substrate region 20 and a second substrate region 30 disposed in plural as the remaining portion of the substrate SUB except the first substrate region 20, the first substrate region 20 including or formed of a polymer resin PSM, and the second substrate region 30 including a plurality of second substrate regions 30.

The first substrate area 20 may be a planar area overlapping the display area DA and not including the first conductive balls CM 1. The first substrate region 20 may be disposed to be spaced apart from the first conductive balls CM 1. The first substrate region 20 may be a planar region disposed or formed only of the polymer resin PSM.

The second substrate area 30 may be a discrete planar area that does not overlap the display area DA, but overlaps the non-display area NDA. The discrete planar regions include a polymer resin PSM and first conductive balls CM1 dispersed in the polymer resin PSM. The second substrate region 30 may be arranged in the non-display region NDA as an island pattern. The second substrate regions 30 may be disposed to be spaced apart from each other by a predetermined distance, and may be surrounded by the first substrate regions 20.

Specifically, referring to fig. 16 and 17, the TFT ST, the light emitting element 170, and the sensor electrode layer SENL may be disposed in the display area DA of the substrate SUB. The gate signal lines GLS and the gate line pads GP may be disposed in the non-display area NDA of the substrate SUB. A cross-sectional structure of a region corresponding to the gate signal line GLS and the gate line pad GP will be described hereinafter. The sectional structure of the region where the data signal line DLS and the data line pad DLP are disposed is substantially the same as that described above with reference to fig. 10, and thus, a detailed description thereof will be omitted.

The first substrate region 20 of the substrate SUB may overlap with the TFT ST, the light emitting element 170, and the sensor electrode layer SENL. The second substrate region 30 of the substrate SUB may not overlap with the TFT ST and the light emitting element 170. In an embodiment, the light emitting element 170 is spaced apart from the second substrate region 30 including the conductive material in a direction along the substrate SUB.

The first substrate region 20 may include only the polymer resin PSM to exhibit non-conductivity, and may not include the first conductive balls CM 1. The second substrate region 30 may include both the polymer resin PSM and the first conductive balls CM1 (conductive material dispersed in the polymer resin PSM) to exhibit conductivity. The first conductive balls CM1 may be randomly dispersed in the polymer resin PSM.

The first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 may be sequentially stacked on the second substrate region 30 of the substrate SUB. The gate signal line GLS and the gate line pad GP may be disposed on the gate insulating layer 130. A first pad hole PH1 exposing the substrate SUB to the outside of the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 may be provided. The gate line pad GP may be electrically connected to the substrate SUB through the first pad hole PH 1. That is, the gate line pad GP may fill the first pad hole PH1 to be in contact with the top surface of the substrate SUB at the first pad hole PH 1.

The conductive adhesive member CAM may be disposed under the second substrate region 30 of the substrate SUB. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300 to each other. The second substrate area 30 may overlap the conductive adhesive member CAM and the circuit board 300.

The conductive adhesive member CAM may include an adhesive resin ADR and second conductive balls CM2 dispersed in the adhesive resin ADR. The circuit board 300 to which the display driving circuit 200 is attached may be disposed under the conductive adhesive member CAM. The first bump electrode BPE1 of the circuit board 300 may be disposed on a first surface of the circuit board 300, and the display driving circuit 200 may be disposed on a second surface of the circuit board 300 opposite to the first surface thereof.

The gate line pad GP, the first conductive ball CM1, the second conductive ball CM2, and the first bump electrode BPE1 may be thermally pressed, and thus may be electrically contacted with each other. That is, the gate line pad GP may be in contact with the first conductive balls CM1 of the substrate SUB, the first conductive balls CM1 may be in contact with the second conductive balls CM2 of the conductive adhesive member CAM, and the second conductive balls CM2 may be in contact with the first bump electrode BPE1 of the circuit board 300. During the thermocompression, the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be compressed in a region of the circuit board 300 aligned with the first bump electrodes BPE1 of the circuit board 300. Accordingly, the gate line pad GP of the display panel 100 may be electrically connected to the circuit board 300 at the first bump electrode BPE1 of the circuit board 300 through the substrate SUB.

A portion of the substrate SUB (e.g., the second substrate region 30) may include first conductive balls CM 1. The first conductive ball CM1 may be thermocompressed only in a region of the circuit board 300 aligned with the first bump electrode BPE1 of the circuit board 300, and thus may be electrically connected to the second conductive ball CM 2. That is, the gate line pad GP and the first bump electrode BPE1 of the circuit board 300 may be electrically connected to each other by forming the second substrate region 30 including the first conductive balls CM1 in a region overlapping the pad region and providing conductivity. Accordingly, the use of the conductive member may be reduced, and thus, the manufacturing cost of the display device 10 may be reduced.

The substrate SUB may be provided by a solution process.

Fig. 18 to 20 are plan views illustrating an embodiment of a method of providing the substrate SUB.

Referring to fig. 18, a method of providing or fabricating a substrate SUB may include performing a solution process on a base substrate BSUB. Specifically, a base substrate BSUB is provided or prepared. The base substrate BSUB may be a rigid substrate, such as a glass substrate or a plastic substrate.

A solution in which a polymer resin PSM and a plurality of first conductive balls CM1 are combined is provided. The first conductive balls CM1 may be present in the polymer resin PSM in an amount of about 0.1 parts by weight to about 10 parts by weight per 100 parts by weight of the solution. In an embodiment, for example, 95 parts by weight of the polyimide resin and 5 parts by weight of the nickel conductive balls may be included in 100 parts by weight of the solution. However, the content of the first conductive balls CM1 is not particularly limited.

The solution may be applied to the base substrate BSUB using a solution process. The solution process may be performed using slit coating, nozzle coating, printing, or spin coating. The polymer resin PSM in which the first conductive balls CM1 are combined may be applied onto the base substrate BSUB (such as by the nozzle coating apparatus CN) and cured, thereby obtaining the substrate SUB of fig. 3. That is, the substrate SUB may include a base substrate BSUB having a polymer resin PSM and first conductive balls CM1 positioned in the polymer resin PSM.

Fig. 19 and 20 show an embodiment of a method of providing a substrate SUB.

Referring to fig. 19, a polymer resin PSM not including the first conductive balls CM1 is applied on the base substrate BSUB. The first substrate region 20 is disposed or formed by applying the polymer resin PSM excluding the first conductive balls CM1 onto a portion of the base substrate BSUB (such as using the nozzle coating apparatus CN) to form a pattern of the polymer resin PSM and curing the pattern of the polymer resin PSM excluding the first conductive balls CM 1.

Referring to fig. 20, the second substrate region 30 including a plurality of second substrate regions 30 disposed in a plural manner is disposed or formed by applying a polymer resin PSM having the first conductive balls CM1 therein to a planar region other than the planar region of the first substrate region 20 using a nozzle coating apparatus CN and curing the polymer resin PSM having the first conductive balls CM1 incorporated therein. In this way, the substrate SUB of fig. 15 can be obtained. The substrate SUB of fig. 12 can also be obtained by using the methods of fig. 19 and 20.

Alternatively, a lithographic method may be used to provide the substrate SUB comprising the first substrate region 20 and the second substrate region 30. In an embodiment, for example, a polymer resin PSM may be applied to the entirety of the base substrate BSUB, and the patterned first substrate region 20 may be disposed or formed by photolithography. Thereafter, a polymer resin PSM including a conductive member may be applied to the entirety of the base substrate BSUB, and then may be patterned only in a planar area except for the first substrate area 20, thereby forming the second substrate area 30.

As described above, since the circuit board 300 electrically connected to the pad region at the front surface of the substrate SUB including the conductive material is attached to the substrate SUB at the rear surface of the substrate SUB, the planar region of the display device 10 in which the circuit board 300 and/or the substrate SUB is bent may be omitted. Therefore, the bezel size of the display device 10 can be reduced.

At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.