阅读说明：本技术 基于22nm工艺条件的抗辐照FDSOI场效应管及其制备方法 (Anti-radiation FDSOI field effect transistor based on 22nm process condition and preparation method thereof ) 是由 刘红侠 刘孜煦 陈树鹏 王树龙 于 2021-08-05 设计创作，主要内容包括：本发明公开了一种基于22nm工艺条件的抗辐照FDSOI场效应管及其制备方法,其自下而上包括：衬底层(1)、P阱(2)、埋氧层(3)、Si层(4)、SiO-(2)栅氧化层(13)、HfO-(2)高k栅介质层(14)和金属栅(18)；P阱中自左向右依次插有三个浅槽隔离区(5,6,7)；且前两个浅槽隔离区之间为背栅(8)；栅极的两侧为左右两个侧墙(15,16)；每个侧墙下方为轻掺杂源漏区(17),该区两侧分别为源区(9)与源区抬起(11)和漏区(10)与漏区抬起(12)。本发明由于增设了背栅和源漏抬高区域,并在漏区注入Ge元素,减小了寄生效应,提高了器件工作可靠性和抗单粒子辐照能力,可用于航空航天电子设备。(The invention discloses an anti-irradiation FDSOI field effect transistor based on 22nm process conditions and a preparation method thereof, wherein the anti-irradiation FDSOI field effect transistor comprises the following components from bottom to top: the device comprises a substrate layer (1), a P well (2), an oxygen buried layer (3), a Si layer (4) and SiO 2 A gate oxide layer (13), HfO 2 A high-k gate dielectric layer (14) and a metal gate (18); three shallow trench isolation regions (5, 6, 7) are sequentially inserted into the P well from left to right; and a back gate (8) is arranged between the first two shallow trench isolation regions; the two sides of the grid are provided with a left side wall and a right side wall (15, 16); a lightly doped source/drain region (17) is arranged below each side wall, and a source region (9) and a source region uplift (11) and a drain region (10) and a drain region are respectively arranged at two sides of the regionThe drain region is raised (12). According to the invention, because the back gate and the source-drain raised area are additionally arranged, and Ge element is injected into the drain area, the parasitic effect is reduced, the working reliability and the single-particle irradiation resistance of the device are improved, and the device can be used for aerospace electronic equipment.)

1. An anti-irradiation FDSOI field effect transistor based on 22nm process conditions comprises the following components from bottom to top: a substrate layer (1), an oxygen buried layer (3), a Si layer (4), SiO₂A gate oxide layer (13) and a grid electrode (18), wherein two sides of the grid electrode (18) are respectively Si₃N₄A left side wall (15) and a right side wall (16), Si in the Si layer (4)₃N₄Two lightly doped sources are arranged below the left side wall (15) and the right side wall (16)Drain region (17), be close to buried oxide layer (3) top of left side wall (15) for source region (9), be close to buried oxide layer (3) top of right side wall (16) for drain region (10), its characterized in that:

a P well (2) is arranged between the substrate layer (1) and the buried oxide layer (3), a first shallow groove isolation region (5), a second shallow groove isolation region (6) and a third shallow groove isolation region (7) are sequentially inserted into the P well (2) from left to right, the second shallow groove isolation region (6) and the third shallow groove isolation region (7) are positioned on two sides of the buried oxide layer (3), and a back gate (8) is arranged between the first shallow groove isolation region (5) and the second shallow groove isolation region (6);

the SiO₂HfO is arranged above the gate oxide layer (13)₂A high-k gate dielectric layer (14);

a source region lifting part (11) is arranged above the source region (9);

and a drain region lifting part (12) is arranged above the drain region (10), and Ge elements are injected into the drain region (10) and the drain region lifting part (12).

2. The fet of claim 1 wherein:

b ions are implanted into the P trap (2) and the concentration of the B ions is 1.0 multiplied by 10¹⁶cm^-3-1.0×10¹⁷cm^-3；

Ge elements are implanted into the drain region (10) and the drain region lift (12), and the concentration of the Ge elements is 1.0 multiplied by 10¹⁹cm^-3-1.0×10²¹cm^-3。

3. The fet of claim 1 wherein:

the SiO₂The buried oxide layer (3) is 20-30nm thick;

the HfO₂A high-k gate dielectric layer (14) having a thickness of 1-3 nm;

the thickness of the source region lift-off (11) and the thickness of the drain region lift-off (12) are both 5nm-15 nm.

4. A preparation method of an anti-radiation FDSOI field effect transistor based on 22nm process conditions is characterized by comprising the following steps:

1) preparing an SOI substrate:

1a) selecting two silicon wafers, forming an oxygen burying layer (3) on a first silicon wafer by using a dry oxygen process, and then performing activation treatment on the first silicon wafer;

1b) h + or He + implantation is carried out on the second silicon wafer, and then bonding treatment and heat treatment are carried out on the first silicon wafer after activation treatment and the second silicon wafer implanted with H + or He + in sequence to form an SOI substrate;

2) removing the silicon layer on the SOI substrate by a wet etching process, and then carrying out P-type ion doping on the SOI substrate with the silicon layer removed to form a P-type substrate layer (1);

3) preparation of back gate (8):

3a) growing a first SiO on the buried oxide layer (3) by dry oxygen process₂A buffer layer on which the first Si is grown₃N₄A protective layer, on which a photoresist is spin-coated;

3b) removing the left partial area of the buried oxide layer (3) by exposure and etching to form a back gate region groove, epitaxially growing Si material in the back gate region groove, heavily doping the Si material, and removing the first SiO outside the back gate region groove₂Buffer layer, first Si₃N₄A back gate (8) is formed by the protective layer and the photoresist;

4) carrying out P-type ion heavy doping on the substrate below the buried oxide layer (3) to form a P well (2);

5) epitaxially growing a silicon layer on the buried oxide layer (3), and carrying out doping treatment on the silicon layer to form a Si layer (4);

6) preparing three shallow slot isolation regions:

6a) growing a second SiO on the Si layer (4) by means of a dry oxygen process₂A buffer layer on the second SiO₂Growing second Si on the buffer layer₃N₄A protective layer on the second Si₃N₄Spin-coating photoresist on the protective layer;

6b) removing partial thickness P well (2) and buried oxide layer (3) at two sides of back gate (8) and Si layer (4) by exposure and etching to form three shallow trench isolation region grooves, and depositing SiO respectively in each isolation region₂Preparing a first shallow trench isolation region (5), a second shallow trench isolation region (6) and a third shallow trench isolation region (7) by using materials, and removing second SiO outside the three shallow trench isolation regions₂Buffer layer, secondSi₃N₄A protective layer and a photoresist;

7) preparation of SiO on the Si layer (4) by means of a dry oxygen process₂A gate oxide layer (13) formed on the SiO layer by radio frequency sputtering₂Growing high-k dielectric HfO on the gate oxide layer (13)₂Material, preparation of Hf0₂A high-k gate dielectric layer (14);

8) preparing a metal grid (18):

8a) hf0 by chemical vapor deposition₂Sequentially depositing HfN and TaN on the high-K gate dielectric layer (14) to form a covering layer with the thickness of 1000-2000A DEG, and performing rapid thermal annealing on the TaN/HfN/HfO₂Carrying out high-temperature annealing on the high-K gate dielectric layer structure;

8b) removing TaN/HfN/HfO by wet etching₂Preparing a metal gate (18) on the high-K gate dielectric layer (14) with the TaN/HfN covering layer removed;

9) preparing a lightly doped source drain region (17):

9a) growing third SiO on two sides of the metal gate (18) and above the Si layer (4) by using a dry oxygen process₂A buffer layer of the third SiO₂Photoresist is coated on the buffer layer in a spinning mode;

9b) etching an injection window of a lightly doped source drain region on the photoresist on two sides of the metal gate (18) through exposure, then carrying out ion injection on the injection window of the lightly doped source drain region to form a lightly doped source drain region (17), and removing the residual photoresist;

10) in the third SiO₂Growing third Si on the buffer layer₃N₄A protective layer on the third Si₃N₄Spin-coating photoresist on the protective layer, etching an injection window on the photoresist, and aligning the third Si on the window₃N₄The protective layer is subjected to reactive ion etching to form Si₃N₄The left side wall (15) and the right side wall (16) are removed, and then the third SiO is removed₂Buffer layer, third Si₃N₄A protective layer and a photoresist;

11) preparing a source region (9), a source region lift (11), a drain region (10) and a drain region lift (12):

11a) by vapor phase epitaxial growthIn Si₃N₄Preparing a source region uplift region and a drain region uplift region on two sides of the left side wall (15) and the right side wall (16) and above the Si layer (4), and growing fourth SiO on the regions₂A buffer layer, wherein photoresist is spin-coated on the buffer layer;

11b) etching source region and drain region injection windows on the photoresist, and performing ion injection of V-group elements on the two injection windows to form a source region (9) and a source region lift (11); then, Ge element ion implantation is carried out on the implantation window of the drain region to form a drain region (10) and a drain region lift (12), and then fourth SiO is removed₂And (5) buffer layers and photoresist are used for completing the preparation of the device.

5. The method of claim 4, wherein the dry oxygen process used in 1a), 3a), 6a), 7) and 9a) is carried out at a temperature of 1000 ℃ to 1200 ℃.

6. The method of claim 4, wherein the sputtering gas used in the sputtering method of 7) is argon, the frequency of the AC power source is 5MHz-30MHz, and the target material is HfO₂。

7. The process for producing a field effect tube as claimed in claim 4, wherein the chemical vapor deposition method used in 8a) has a deposition temperature of 550 ℃ to 650 ℃, a reaction chamber pressure of 520Pa, reactants of tantalum powder and hafnium-based metal, and a reaction gas of NH having a purity of 99.999%₃。

8. The method for manufacturing a field effect tube according to claim 4, wherein the rapid annealing method used in 8a) has a temperature of 900 ℃ to 1100 ℃ and an annealing time of several seconds to several tens of seconds.

9. The method of manufacturing a field effect transistor according to claim 4,

the concentration of the doped B ions in the 2) is 1.2 multiplied by 10¹⁵cm^-3；

The concentration of the heavily doped B ions in the 3B) is 6 multiplied by 10¹⁷cm^-3；

The concentration of the heavily doped B ions in the step 4) is 6 multiplied by 10¹⁹cm^-3。

10. The method of manufacturing a field effect transistor according to claim 4, wherein:

the As ion concentration doped in the 5) is 1 x 10¹⁶cm^-3；

The As ion concentration doped in the 9b) is 1 x 10¹⁶cm^-3；

The As ion concentration doped in the 11b) is 6 x 10¹⁹cm^-3。

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to an anti-radiation FDSOI field effect transistor which can be used for aerospace electronic equipment.

Background

With the rapid development of integrated circuits and the improvement of the level of integrated circuit manufacturing processes, the integration level of chips is higher and higher, and the feature size is also developed from micron, submicron and deep submicron to ultra-deep submicron. When the feature size of the integrated circuit process is reduced to 45nm and below, a series of short channel effects occur in the conventional bulk silicon MOS transistor, so that the device cannot work normally. Many new structures have been developed to address this problem, including FinFET structures, and silicon-on-insulator SOI structures. Along with the rapid development of the national aerospace technology and the gradual maturity of the application of the silicon-on-insulator technology, the advantages of the SOI structure compared with the bulk silicon structure are gradually shown, and more aerospace technologies adopt the SOI structure.

The SOI structure comprises a top silicon layer, a middle insulating layer and a substrate silicon layer, and is divided into a partially depleted silicon-on-insulator (PDSOI) structure and a fully depleted silicon-on-insulator (FDSOI) structure. Wherein:

the top silicon film of the PDSOI is thick, and the depletion layer under the channel only occupies a part of the silicon film, which may generate a floating body effect, so that the performance of the circuit is reduced.

The top silicon film thickness of the FDSOI is reduced to 5-20nm, and a depletion layer below a channel can be filled with the whole silicon thin layer when the device works, so that parasitic effects such as a floating body effect and a short channel effect are overcome.

As shown in fig. 1, a conventional FDSOI field effect transistor is formed by sequentially stacking a substrate silicon layer, an intermediate insulating layer, a top silicon layer, a gate oxide layer, and a gate layer from bottom to top, where the top silicon layer includes a source region, a drain region, and a body region. The device is manufactured by firstly preparing an SOI substrate by a thermal oxidation method, wherein the SOI substrate comprises a substrate silicon layer, a middle insulating layer and a top silicon layer with the thickness of 5-20nm, and performing ion implantation on the substrate silicon layer to form a P/N type substrate layer; preparing a gate oxide layer on the top silicon layer by a thermal oxidation method; preparing a grid electrode with the grid length of 10-45nm on the grid oxide layer by a chemical vapor deposition method; and finally, forming a source region and a drain region on two sides of the grid electrode of the top silicon layer through ion implantation.

When the FDSOI field effect transistor with the structure is applied to aerospace electronic equipment, a sensitive region of a semiconductor device is injected by high-energy particles, the high-energy particles are ionized along with the injection of the particles to generate a large number of electron-hole pairs, the electron-hole pairs are collected by the device under the action of an electric field to form a single-particle pulse current, and the pulse current can change the logic state of the device and interfere or lose the function. And as the gate length of the device is reduced to 22nm or below, the amplification effect of the parasitic bipolar transistor is further enhanced, the single-particle transient current is larger and larger, and the probability of failure of the device is also larger and larger.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides an anti-irradiation FDSOI field effect transistor based on 22nm process conditions and a preparation method thereof, so as to reduce single-particle transient current and improve the anti-irradiation reliability of the device.

The technical scheme of the invention is realized as follows:

1. an anti-irradiation FDSOI field effect transistor based on 22nm process conditions comprises from bottom to top: substrate layer 1, buried oxide layer 3, Si layer 4, SiO₂A gate oxide layer 13, a gate 18, Si on both sides of the gate 18₃N₄Left side wall 15 and right side wall 16, Si in the Si layer 4₃N₄The below of left side wall 15 and right side wall 16 is two lightly doped source drain regions 17, and the top of the oxygen layer 3 that buries that is close to left side wall 15 is source region 9, and the top of the oxygen layer 3 that buries that is close to right side wall 16 is drain region 10, its characterized in that:

a P well 2 is arranged between the substrate layer 1 and the buried oxide layer 3, a first shallow slot isolation region 5, a second shallow slot isolation region 6 and a third shallow slot isolation region 7 are sequentially inserted into the P well 2 from left to right, the second shallow slot isolation region 6 and the third shallow slot isolation region 7 are positioned at two sides of the buried oxide layer 3, and a back gate 8 is arranged between the first shallow slot isolation region 5 and the second shallow slot isolation region 6;

the SiO₂An HfO layer is arranged above the gate oxide layer 13₂A high-k gate dielectric layer 14;

a source region lifting 11 is arranged above the source region 9;

and a drain region lifting part 12 is arranged above the drain region 10, and Ge elements are implanted into the drain region 10 and the drain region lifting part 12.

Furthermore, B ions are implanted into the P trap 2, and the concentration of the B ions is 1.0 multiplied by 10¹⁶cm^-3-1.0×10¹⁷cm^-3(ii) a Ge element is implanted into the drain region 10 and the drain region raised portion 12, and the concentration of the Ge element is 1.0 × 10¹⁹cm^-3-1.0×10²¹cm^-3；

Further, the SiO₂The buried oxide layer 3 is 20-30nm thick; the HfO₂A high-k gate dielectric layer 14 with a thickness of 1-3 nm; the thicknesses of the source region uplift 11 and the drain region uplift 12 are both 5nm-15 nm.

2. A preparation method of an anti-radiation FDSOI field effect transistor based on 22nm process conditions is characterized by comprising the following steps:

1) preparing an SOI substrate:

1a) selecting two silicon wafers, forming an oxygen burying layer 3 on a first silicon wafer by using a dry oxygen process, and then performing activation treatment on the first silicon wafer;

1b) h + or He + implantation is carried out on the second silicon wafer, and then the first silicon wafer after activation treatment and the second silicon wafer implanted with H + or He + are sequentially subjected to low-temperature bonding treatment and heat treatment to form an SOI substrate;

2) removing a silicon layer on the SOI substrate by a wet etching process, and then carrying out P-type ion doping on the SOI substrate with the silicon layer removed to form a P-type substrate layer 1;

3) preparation of a back gate 8:

3a) growing a first SiO on the buried oxide layer 3 by dry oxygen process₂A buffer layer on which the first Si is grown₃N₄A protective layer, on which a photoresist is spin-coated;

3b) removing the left part of the buried oxide layer 3 by exposure and etchingForming a back gate region groove in the region, epitaxially growing Si material in the back gate region groove, heavily doping the Si material, and removing the first SiO outside the back gate region groove₂Buffer layer, first Si₃N₄Forming a back gate 8 by the protective layer and the photoresist;

4) carrying out P-type ion heavy doping on the substrate below the buried oxide layer 3 to form a P well 2;

5) epitaxially growing a silicon layer on the buried oxide layer 3, and carrying out doping treatment on the silicon layer to form a Si layer 4;

6) preparing three shallow slot isolation regions:

6a) growing a second SiO on the Si layer 4 by means of a dry oxygen process₂A buffer layer on the second SiO₂Growing second Si on the buffer layer₃N₄A protective layer on the second Si₃N₄Spin-coating photoresist on the protective layer;

6b) removing partial thickness P well 2 and buried oxide layer 3 at two sides of back gate 8 and Si layer 4 by exposure and etching to form three shallow trench isolation region grooves, and respectively depositing SiO in each isolation region₂Preparing a first shallow trench isolation region 5, a second shallow trench isolation region 6 and a third shallow trench isolation region 7 by using materials, and removing a second SiO outside the three shallow trench isolation regions₂Buffer layer, second Si₃N₄A protective layer and a photoresist;

7) preparation of SiO on the Si layer 4 by means of a dry oxygen process₂A gate oxide layer 13 formed on the SiO layer by RF sputtering₂Growing high-k dielectric HfO on the gate oxide layer 13₂Material, preparation of Hf0₂A high-k gate dielectric layer 14;

8) preparing the metal grid 18:

8a) hf0 by chemical vapor deposition₂Sequentially depositing HfN and TaN on the high-K gate dielectric layer 14 to form a covering layer with the thickness of 1000-2000A DEG, and performing rapid thermal annealing on the TaN/HfN/Hf0₂Carrying out high-temperature annealing on the high-K gate dielectric layer structure;

8b) removing TaN/HfN/Hf0 by wet etching₂A TaN covering layer and an HfN covering layer in the high-K gate dielectric layer structure, and a metal gate is prepared on the high-K gate dielectric layer 14 with the TaN/HfN covering layer removed18；

9) Preparing a lightly doped source and drain region 17:

9a) growing third SiO on both sides of the metal gate 18 and above the Si layer 4 by using a dry oxygen process₂A buffer layer of the third SiO₂Photoresist is coated on the buffer layer in a spinning mode;

9b) etching the light doped source and drain regions by exposing the photoresist on both sides of the metal gate 18, performing ion implantation on the light doped source and drain regions to form a light doped source and drain region 17, and removing the residual photoresist

10) In the third SiO₂Growing third Si on the buffer layer₃N₄A protective layer on the third Si₃N₄Spin-coating photoresist on the protective layer, etching an injection window on the photoresist, and aligning the third Si on the window₃N₄The protective layer is subjected to reactive ion etching to form Si₃N₄A left side wall 15 and a right side wall 16, and removing the third SiO₂Buffer layer, third Si₃N₄A protective layer and a photoresist;

11) preparing a source region 9, a source region lift-off 11 and a drain region 10, a drain region lift-off 12:

11a) by vapor phase epitaxial growth on Si₃N₄Preparing a source region uplift region and a drain region uplift region on two sides of the left side wall 15 and the right side wall 16 and above the Si layer 4, and growing fourth SiO on the regions₂A buffer layer, wherein photoresist is spin-coated on the buffer layer;

11b) etching source region and drain region injection windows on the photoresist, and performing ion injection of V-group elements on the two injection windows to form a source region 9 and a source region lift-up 11; then, Ge element ion implantation is carried out on the implantation window of the drain region to form a drain region 10 and a drain region lift-off 12, and then the fourth SiO is removed₂And (5) buffer layers and photoresist are used for completing the preparation of the device.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the invention, because the back gate is led out on the basis of the conventional FDSOI field effect transistor, the source and drain lifting region is increased, the source and drain series resistance is reduced, and the performance of the device is improved.

2. According to the invention, as the Ge element is subjected to ion implantation in the drain region, the Ge element can provide an effective recombination center as a deep-level impurity in Si, the influence of a large number of hole-electron pairs generated by single-particle incidence on a device is weakened, and Si can be formed_1-xGe_xThe alloy form can improve the electrical property of the device and reduce the influence of single-particle transient current brought by parasitic effect by adjusting the energy band structure, so that the working reliability and the single-particle irradiation resistance of the device are higher.

Drawings

FIG. 1 is a schematic structural diagram of a conventional FDSOI field effect transistor;

FIG. 2 is a schematic structural diagram of an anti-radiation FDSOI field effect transistor based on 22nm process conditions according to the present invention;

FIG. 3 is a flow chart of an implementation of the present invention to fabricate the FET of FIG. 2;

FIG. 4 is a simulation graph of drain current versus collected charge over time for a device in accordance with example 1 of the present invention;

FIG. 5 is a simulation graph of drain current versus collected charge over time for a device according to example 2 of the present invention.

Detailed Description

The following describes in detail specific embodiments and effects of the present invention with reference to the drawings.

Referring to fig. 2, the structure of the FDSOI fet manufactured by the present invention includes, from bottom to top: substrate layer 1, P well 2, buried oxide layer 3, Si layer 4, SiO₂Gate oxide layer 13, HfO₂A high-k gate dielectric layer 14 and a metal gate 18; a first shallow trench isolation region 5, a second shallow trench isolation region 6 and a third shallow trench isolation region 7 are sequentially inserted into the P well 2 from left to right, and the second shallow trench isolation region 6 and the third shallow trench isolation region 7 are positioned on two sides of the buried oxide layer 3; a back gate 8 is arranged between the first shallow trench isolation region 5 and the second shallow trench isolation region 6; both sides of the gate 18 are Si₃N₄A left side wall 15 and a right side wall 16; si in the Si layer 4₃N₄Two lightly doped source/drain regions 17 are arranged below the left side wall 15 and the right side wall 16; the two sides of the lightly doped source/drain region 17 are close to the upper part of the buried oxide layer 3 of the left side wall 15 and are source regions9; a source region lift-up 11 is arranged above the source region 9; a drain region 10 is arranged above the buried oxide layer 3 close to the right side wall 16; above the drain region 10 is a drain lift 12.

Referring to fig. 3, the method of fabricating the fet shown in fig. 2 according to the present invention provides the following three embodiments:

example 1 preparation of HfO₂The thickness of the high-k gate dielectric layer is 1nm, and the concentration of implanted B ions in the P trap is 1.0 multiplied by 10¹⁶cm^-3And the concentration of Ge element implanted in the raising of the drain region and the drain region is 1.0 multiplied by 10¹⁹cm^-3The radiation-resistant FDSOI field effect transistor.

Step 1, preparing an SOI substrate.

1a) Selecting two silicon wafers, and growing SiO with the thickness of 20nm on the first silicon wafer at 1000 ℃ by using a dry oxygen process₂Burying an oxygen layer, performing activation treatment on the first silicon wafer at 550 ℃ for more than 6 minutes, and performing cleaning treatment by using an RCA cleaning agent;

1b) h is carried out on a second silicon wafer⁺Or He⁺Implanting, and implanting the activated first silicon wafer with implant H⁺Or He⁺The second silicon wafer is bonded, the first silicon wafer and the second silicon wafer which are bonded are subjected to heat treatment at 500 ℃, then high-temperature annealing treatment is carried out at 900 ℃, bonding strength is increased, chemical mechanical polishing is adopted to carry out flatness treatment on the surfaces of the silicon wafers, and the preparation of the SOI substrate is completed.

Step 2, removing the silicon layer on the SOI substrate by a wet etching process, and carrying out concentration of 1.2 multiplied by 10 on the silicon layer¹⁵cm^-3And doping the B ions to form a P-type substrate layer.

And 3, preparing a back gate.

3a) Growing a first SiO 5nm thick on the buried oxide layer at 1000 deg.C by dry oxygen process₂A buffer layer on the SiO₂Depositing a first Si layer with a thickness of 20nm on the buffer layer₃N₄A protective layer, on which a photoresist is spin-coated;

3b) exposing the photoresist to produce a window, etching to remove the left partial region of the buried oxide layer to form a back gate groove, and epitaxially growing Si material in the grooveThen the mixture is processed into the mixture with the concentration of 6 multiplied by 10¹⁷cm^-3Doping B ions, performing chemical mechanical polishing, cleaning the photoresist, and cleaning in hot phosphoric acid at 180 ℃ to remove the first SiO₂Buffer layer and first Si₃N₄And a protective layer.

Step 4, carrying out concentration of 1.0 multiplied by 10 on the substrate below the buried oxide layer¹⁶cm^-3And doping the B ions to form a P well.

Step 5, epitaxially growing a silicon layer on the buried oxide layer, and performing concentration of the silicon layer to be 1 × 10¹⁶cm^-3As ions to form a Si layer.

And 6, preparing three shallow slot isolation regions.

6a) Growing a second SiO layer with a thickness of 5nm on the Si layer at 1000 deg.C by dry oxygen process₂A buffer layer on the SiO₂Depositing a second Si layer with a thickness of 20nm on the buffer layer₃N₄A protective layer, on which a photoresist is spin-coated;

6b) exposing the photoresist to produce a window, etching to remove partial thickness of P well and buried oxide layer at two sides of back gate and Si layer to obtain three shallow trench isolation region grooves with depth of 60nm, and respectively depositing SiO on each isolation region₂Preparing a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region, performing chemical mechanical polishing, cleaning photoresist, and cleaning in hot phosphoric acid at 180 ℃ to remove second SiO₂Buffer layer and second Si₃N₄And a protective layer.

Step 7, growing SiO with the thickness of 1nm on the Si layer at 1000 ℃ by a dry oxygen process₂Gate oxide layer, bombarding HfO with 5MHz AC power supply₂Depositing a target material to obtain HfO with the thickness of 1nm₂A high-k dielectric layer.

And 8, preparing a metal gate.

8a) Sequentially introducing tantalum powder and a hafnium-based metal organic source into an MOCVD reaction chamber at 550 ℃, and adding NH with the purity of 99.999%₃Introducing into the reaction chamber from another gas path, maintaining the pressure in the reaction chamber at 520Pa, and forming HfN and TaN cover with thickness of 1000-2000A °Layer, then to TaN/HfN/HfO at 900 deg.C₂Carrying out high-temperature annealing on the high-K gate dielectric layer structure for 10 seconds;

8b) putting the silicon chip into a hot solution at 150 ℃ to boil for 5 minutes, and etching away TaN/HfN/HfO₂Soaking the silicon wafer in HF to H to form a TaN covering layer in the high-K dielectric layer structure₂Removing HfN/HfO in diluted hydrofluoric acid with O being 1: 100 for 5 min₂And preparing a metal gate on the high-K gate dielectric layer with the TaN/HfN covering layer removed.

And 9, preparing a lightly doped source drain region.

9a) Growing a third SiO layer with the thickness of 5nm on the buried oxide layer at the temperature of 1000 ℃ by using a dry oxygen process₂A buffer layer, a first electrode, a second electrode,

and spin-coating photoresist thereon;

9b) exposing the photoresist to light to form a window, and exposing the window to a concentration of 1 × 10¹⁶cm^-3As ions are implanted to form a lightly doped source drain region, and then chemical mechanical polishing is carried out to clean the photoresist.

Step 10, preparation of Si₃N₄A left side wall and a right side wall.

10a) In the third SiO₂Depositing third Si with a thickness of 20nm on the buffer layer₃N₄A protective layer on the third Si₃N₄Spin-coating photoresist on the protective layer;

10b) making an implantation window on the photoresist by exposure, and aligning a third Si layer on the window₃N₄The protective layer is subjected to reactive ion etching to form Si₃N₄A left side wall and a right side wall;

10c) performing chemical mechanical polishing, cleaning the photoresist, and cleaning in hot phosphoric acid at 180 deg.C to remove the third SiO₂Buffer layer and third Si₃N₄And a protective layer.

And 11, preparing a source region, a source region lifting and a drain region lifting.

11a) In Si₃N₄Epitaxially growing a source region lifting region and a drain region lifting region with the thickness of 5nm on two sides of the left side wall and the right side wall and above the Si layer, and then growing a silicon nitride layer on the Si layerGrowing fourth SiO with thickness of 5nm at 1000 deg.C by dry oxygen process₂A buffer layer, wherein photoresist is spin-coated on the buffer layer;

11b) etching source region and drain region implantation windows on the photoresist, and performing implantation at concentration of 6 × 10¹⁹cm^-3Implanting As ions, and performing a concentration of 1.0 × 10 at the implantation window of the drain region¹⁹cm^-3Implanting Ge element to form a source region, a drain region and a raised drain region;

11c) performing chemical mechanical polishing on the raised surfaces of the source region, the source region and the drain region, cleaning the photoresist, and removing the fourth SiO with hydrofluoric acid HF solution₂And (5) buffer layer to finish the preparation of the device.

Example 2 preparation of HfO₂The thickness of the high-k gate dielectric layer is 2nm, and the concentration of implanted B ions in the P trap is 5.0 multiplied by 10¹⁶cm^-3And the concentration of Ge element implanted in the raising of the drain region and the drain region is 1.0 multiplied by 10²⁰cm^-3The radiation-resistant FDSOI field effect transistor.

Step one, preparing an SOI substrate.

1.1) selecting two silicon wafers, and growing SiO with the thickness of 25nm on the first silicon wafer at 1100 ℃ by utilizing a dry oxygen process₂Burying an oxygen layer, performing activation treatment on the first silicon wafer at 550 ℃ for more than 6 minutes, and performing cleaning treatment by using an RCA cleaning agent;

1.2) H-treating the second silicon wafer⁺Or He⁺Implanting, and implanting the activated first silicon wafer with implant H⁺Or He⁺The second silicon wafer is bonded, the first silicon wafer and the second silicon wafer which are bonded are subjected to heat treatment at 500 ℃, then high-temperature annealing treatment is carried out at 1000 ℃, bonding strength is increased, and chemical mechanical polishing is adopted to carry out flatness treatment on the surfaces of the silicon wafers, so that the preparation of the SOI substrate is completed.

And step two, preparing a P-type substrate layer.

The specific implementation of this step is the same as step 2 in example 1.

And step three, preparing a back gate.

The specific implementation of this step is the same as step 3 in example 1.

Step four, the concentration of the substrate below the buried oxide layer is 5.0 multiplied by 10¹⁶cm^-3And doping the B ions to form a P well.

And step five, preparing the Si layer.

The specific implementation of this step is the same as step 5 in example 1.

And step six, preparing three shallow slot isolation regions.

The specific implementation of this step is the same as step 6 in example 1.

Step seven, growing SiO with the thickness of 1nm on the Si layer at 1100 ℃ by a dry oxygen process₂Gate oxide layer, bombarding HfO with alternating current power supply with frequency of 15MHz₂Depositing a target material to obtain HfO with the thickness of 2nm₂A high-k dielectric layer.

And step eight, preparing the metal gate.

8.1) sequentially introducing tantalum powder and a hafnium-based metal organic source into an MOCVD reaction chamber at 600 ℃, and then introducing NH with the purity of 99.999%₃Introducing into the reaction chamber from another gas path, maintaining the pressure in the reaction chamber at 520Pa to form HfN and TaN coating layer with thickness of 1000-2000A deg.C, and performing thermal treatment on the TaN/HfN/HfO coating layer at 1000 deg.C₂Carrying out high-temperature annealing on the high-K gate dielectric layer structure for 20 seconds;

8.2) putting the silicon chip into a hot solution at 150 ℃ to boil for 5 minutes, and etching away TaN/HfN/HfO₂Soaking the silicon wafer in HF to H to form a TaN covering layer in the high-K dielectric layer structure₂Removing HfN/HfO in diluted hydrofluoric acid with O being 1: 100 for 5 min₂And preparing a metal gate on the high-K gate dielectric layer with the TaN/HfN covering layer removed.

And step nine, preparing the lightly doped source drain region.

The specific implementation of this step is the same as step 9 in example 1.

Step ten, preparing Si₃N₄A left side wall and a right side wall.

The specific implementation of this step is the same as step 10 in example 1.

And eleventh, preparing a source region, lifting the source region, and lifting the drain region and the drain region.

11.1) in Si₃N₄Epitaxially growing 10 nm-thick source region raised and drain region raised regions on both sides of the left side wall and the right side wall and above the Si layer, and growing 5 nm-thick fourth SiO on the regions by dry oxygen process at 1100 deg.C₂A buffer layer, wherein photoresist is spin-coated on the buffer layer;

11.2) etching source region and drain region implantation windows on the photoresist, and performing concentration of 6 × 10 on the two implantation windows¹⁹cm^-3Implanting As ions, and performing a concentration of 1.0 × 10 at the implantation window of the drain region²⁰cm^-3Implanting Ge element to form a source region, a drain region and a raised drain region;

11.3) carrying out chemical mechanical polishing on the surfaces of the source region, the source region uplift and the drain region uplift, cleaning the photoresist, and removing the fourth SiO by using hydrofluoric acid HF solution₂And (5) buffer layer to finish the preparation of the device.

Example 3 preparation of HfO₂The thickness of the high-k gate dielectric layer is 3nm, and the concentration of implanted B ions in the P trap is 1.0 multiplied by 10¹⁷cm^-3And the concentration of Ge element implanted in the raising of the drain region and the drain region is 1.0 multiplied by 10²¹cm^-3The radiation-resistant FDSOI field effect transistor.

And step A, preparing an SOI substrate.

A1) Selecting two silicon wafers, and growing SiO with the thickness of 30nm on the first silicon wafer at 1200 ℃ by using a dry oxygen process₂Burying an oxygen layer, performing activation treatment on the first silicon wafer at 550 ℃ for more than 6 minutes, and performing cleaning treatment by using an RCA cleaning agent;

A2) h is carried out on a second silicon wafer⁺Or He⁺Implanting, and implanting the activated first silicon wafer with implant H⁺Or He⁺The second silicon wafer is bonded, the first silicon wafer and the second silicon wafer which are bonded are subjected to heat treatment at 500 ℃, then high-temperature annealing treatment is carried out at 1200 ℃, bonding strength is increased, chemical mechanical polishing is adopted to carry out flatness treatment on the surfaces of the silicon wafers, and the preparation of the SOI substrate is completed.

And step B, preparing a P-type substrate layer.

The specific implementation of this step is the same as step 2 in example 1.

And step C, preparing a back gate.

The specific implementation of this step is the same as step 3 in example 1.

Step D, carrying out concentration of 1.0 multiplied by 10 on the substrate below the oxygen burying layer¹⁷cm^-3And doping the B ions to form a P well.

And E, preparing the Si layer.

The specific implementation of this step is the same as step 5 in example 1.

And F, preparing three shallow slot isolation regions.

The specific implementation of this step is the same as step 6 in example 1.

Step G, growing SiO with the thickness of 1nm on the Si layer at 1200 ℃ by a dry oxygen process₂Gate oxide layer, bombarding HfO with 30MHz AC power supply₂Depositing a target material to obtain HfO with the thickness of 3nm₂A high-k dielectric layer.

And H, preparing a metal gate.

H1) Sequentially introducing tantalum powder and a hafnium-based metal organic source into an MOCVD reaction chamber at 650 ℃, and adding NH with the purity of 99.999%₃Introducing into the reaction chamber from another gas path, maintaining the pressure in the reaction chamber at 520Pa to form HfN and TaN coating layer with thickness of 1000-2000A deg.C, and performing thermal treatment on TaN/HfN/HfO at 1100 deg.C₂Carrying out high-temperature annealing on the high-K gate dielectric layer structure for 30 seconds;

H2) putting the silicon chip into a hot solution at 150 ℃ to boil for 5 minutes, and etching away TaN/HfN/HfO₂Soaking the silicon wafer in HF to H to form a TaN covering layer in the high-K dielectric layer structure₂Removing HfN/HfO in diluted hydrofluoric acid with O being 1: 100 for 5 min₂And preparing a metal gate on the high-K gate dielectric layer with the TaN/HfN covering layer removed.

And step I, preparing a lightly doped source drain region.

The specific implementation of this step is the same as step 9 in example 1.

Step J, preparation of Si₃N₄A left side wall and a right side wall.

The specific implementation of this step is the same as step 10 in example 1.

And K, preparing a source region, lifting the source region, and lifting the drain region and the drain region.

K1) In Si₃N₄Epitaxially growing a source region lifting region and a drain region lifting region with the thickness of 15nm on two sides of the left side wall and the right side wall and above the Si layer, and growing a fourth SiO with the thickness of 5nm above the regions at 1200 ℃ by using a dry oxygen process₂A buffer layer, wherein photoresist is spin-coated on the buffer layer;

K2) etching source region and drain region implantation windows on the photoresist, and performing implantation at concentration of 6 × 10¹⁹cm^-3Implanting As ions, and performing a concentration of 1.0 × 10 at the implantation window of the drain region²¹cm^-3Implanting Ge element to form a source region, a drain region and a raised drain region;

K3) performing chemical mechanical polishing on the raised surfaces of the source region, the source region and the drain region, cleaning the photoresist, and removing the fourth SiO with hydrofluoric acid HF solution₂And (5) buffer layer to finish the preparation of the device.

The effects of the present invention can be further illustrated by the following simulations:

firstly, simulation conditions:

irradiation parameters: the drain voltage is 1.0V, the substrate, the gate and the source voltage are 0V, the incident depth of heavy ions is 0.2 μm, the incident direction is vertical to the gate plane and downward, the incident position is at the PN junction of the drain region and the lightly doped drain region, the characteristic distance is defined as 0.06, and the incident time is 5 × 10^-11s, linear energy transfer LET value of 20MeV cm²/mg、40MeV·cm²/mg、60MeV·cm²/mg、80MeV·cm²/mg、100MeV·cm²/mg。

The three-dimensional model of the device is generated by a device description tool SDE of ISE-TCAD software, and the simulation physical environment is set by a device simulation tool SDEVICE.

The inventive device and the conventional device are generated by the ISE-TCAD software description tool SDE.

Secondly, simulating contents:

simulation 1, the drain current and the collected charge of the device manufactured in example 1 of the present invention and the conventional device were simulated with the above simulation parameters as a time-varying curve, and the result is shown in fig. 4. Wherein:

FIG. 4(a) is a graph showing the on-line energy transfer LET value of 100MeV cm for the device of the present invention and the conventional device²A plot comparing the drain current at/mg to the collected charge versus time;

FIG. 4(b) is a graph of drain current versus collected charge over time for a conventional device at different linear energy transfer LET values;

fig. 4(c) is a graph of drain current versus collected charge over time for devices made in example 1 of the present invention at different linear energy transfer LET values.

It can be seen from fig. 4(a) that the peak value and pulse of the drain current of the conventional device after heavy ion incidence are both larger than those of the device of the present invention, and the drain collected charge after integration is also significantly larger than that of the device of the present invention.

It can be seen from fig. 4(b) and 4(c) that the single-particle transient current peaks and pulses of the device of the present invention are still smaller than those of the conventional device at heavy particle incidence with different linear energy transfer LET values, indicating that the LET value is 20MeV cm no matter at linear energy transfer²About/mg ground heavy ion irradiation environment, and on-line energy transmission LET value of 80MeV cm²In the space application environment of about/mg, the single particle resistance of the device is superior to that of the conventional device.

Simulation 2, which simulates the drain current and the collected charge of the device manufactured in example 3 of the present invention and the conventional device with the above simulation parameters, according to the time-varying curves, the result is shown in fig. 5, wherein:

FIG. 5(a) is a graph showing the on-line energy transfer LET value of 100MeV cm for the device of the present invention and the conventional device²A comparative plot of drain current and collected charge versus time at/mg;

FIG. 5(b) is a graph of drain current versus collected charge over time for conventional devices at different linear energy transfer LET values;

fig. 5(c) is a graph of drain current versus collected charge over time for devices made in example 2 of the present invention at different linear energy transfer LET values.

It can be seen from fig. 5(a) that the peak value and pulse of the drain current of the conventional device after heavy ion incidence are both larger than those of the device of the present invention, and the drain collected charge after integration is also significantly larger than that of the device of the present invention.

It can be seen from fig. 5(b) and 5(c) that the single-particle transient current peaks and pulses of the device of the present invention are still smaller than those of the conventional device at heavy particle incidence with different linear energy transfer LET values, indicating that the LET value is 20MeV cm no matter at linear energy transfer²About/mg ground heavy ion irradiation environment, and on-line energy transmission LET value of 80MeV cm²In the space application environment of about/mg, the single particle resistance of the device is superior to that of the conventional device.

The simulation result shows that:

the single-particle transient current has stronger single-particle irradiation resistance, and the single-particle transient current is obviously reduced compared with the conventional FDSOI device under the condition of the same heavy ion incidence;

under the condition of heavy particle incidence of different linear energy transmission LET values, the single-particle transient current peak value and pulse are both smaller than those of a conventional 22nm FDSOI device, and the single-particle radiation resistant single-particle device has good single-particle radiation resistance.

The above description is only three preferred embodiments of the present invention and constitutes any limitation to the present invention, and it is obvious to those skilled in the art to which the present invention pertains that several simple deductions or substitutions can be made without departing from the inventive concept, but all should be considered as belonging to the protection scope of the present invention.