阅读说明：本技术 一种灵敏放大器半缓冲器 (Semi-buffer of sensitive amplifier ) 是由 李永福 张云芳 马策 王国兴 连勇 于 2021-07-01 设计创作，主要内容包括：本发明涉及电子器件的技术领域,公开了一种灵敏放大器半缓冲器,包括传输模块和握手信号产生模块,所述传输模块用于数据传输,所述握手信号产生模块用于根据传输的数据,生成握手信号,采用或非门结构,其输入端与传输模块的输出端连接,其输出端设置为握手信号Lack。本发明的SAHB仅使用了11个晶体管,与现有SAHB的33个晶体管相比减小了面积；没有使用数据信号的逻辑互补信号,降低了信号的复杂度,提高了运算速度。(The invention relates to the technical field of electronic devices, and discloses a sense amplifier half buffer which comprises a transmission module and a handshake signal generation module, wherein the transmission module is used for data transmission, the handshake signal generation module is used for generating handshake signals according to transmitted data, a NOR gate structure is adopted, the input end of the NOR gate structure is connected with the output end of the transmission module, and the output end of the NOR gate structure is set as a handshake signal Lack. The SAHB of the invention only uses 11 transistors, thus reducing the area compared with the 33 transistors of the prior SAHB; and a logic complementary signal of a data signal is not used, so that the complexity of the signal is reduced, and the operation speed is improved.)

1. A sense amplifier half-buffer, characterized by: comprises a transmission module and a handshake signal generation module, wherein the transmission module is used for data transmission, the handshake signal generation module is used for generating handshake signals according to the transmitted data, a NOR gate structure is adopted, the input end of the NOR gate structure is connected with the output end of the transmission module, the output end of the NOR gate structure is set as handshake signals rock,

the transmission module includes a plurality of handshake signal transistors and a plurality of logic transistors, the handshake signal transistors including: a first handshake signal transistor M1, a second handshake signal transistor M4, a third handshake signal transistor M7; the logic transistor includes: a first logic transistor M2, a second logic transistor M3, a third logic transistor M5, a fourth logic transistor M6;

the gate of the first logic transistor M2 is set as the input data A.F port, the source is connected to the drain of the first handshake signal transistor M1, the drain is connected to the drain of the second handshake signal transistor M4, the drain of the third logic transistor M5 and the output Q.T, and meanwhile, the gate is connected to the gate of the fourth logic transistor M6;

the gate of the second logic transistor M3 is set as the input data A.T port, the source is connected with the drain of the first handshake signal transistor M1, the drain is connected with the drain of the fourth logic transistor M6, the drain of the third handshake signal transistor M7 and the output terminal Q.F, and is also connected with the gate of the third logic transistor M5;

the gate of the third logic transistor M5 is connected to the output terminal Q.F, the source is grounded, and the drain is connected to the drain of the first logic transistor M2 and the drain of the second handshake signal transistor M4;

the gate of the fourth logic transistor M6 is connected to the output terminal Q.T, the source is grounded, and the drain is connected to the drain of the second logic transistor M3 and the drain of the third handshake signal transistor M7;

the grid electrode of the first handshake signal transistor M1 is connected with a handshake signal Rack, the source electrode is connected with a power supply VDD, and the drain electrode is connected with the source electrode of the first logic transistor M2 and the source electrode of the second logic transistor M3;

the gate of the second handshake signal transistor M4 is connected to the handshake signal Rack, the source is grounded, and the drain is connected to the drain of the first logic transistor M2 and the drain of the third logic transistor M5;

the gate of the third handshake signal transistor M7 is connected to the handshake signal Rack, the source is grounded, and the drain is connected to the drain of the second logic transistor M3 and the drain of the fourth logic transistor M6;

and the handshake signal Rack is set as a handshake output signal of the last adjacent asynchronous module on the same line.

2. The sense amplifier half-buffer of claim 1, wherein: the handshake signal generation module includes a fourth handshake signal transistor M8, a fifth handshake signal transistor M9, a sixth handshake signal transistor M10, and a seventh handshake signal transistor M11, the input terminals of which are connected with the output terminals Q.T and Q.F.

Technical Field

The invention relates to the technical field of electronic devices, in particular to a semi-buffer of a sensitive amplifier.

Background

The current digital circuit is mainly divided into two design methods of synchronous and asynchronous. Because the synchronous circuit is simpler, the application is wider at present. But synchronous circuits also have some disadvantages: the clock signal continuously turns over to cause huge power consumption; strict timing constraints are required, and the difficulty is high; errors may occur in the face of process, Voltage, Temperature (PVT) disturbances, and the like.

Asynchronous circuits can overcome these disadvantages: asynchronous circuits have more relaxed timing constraints; the robustness is better in the face of PVT disturbance; because the global clock signal is not available, the signal inversion is less, and the power consumption is lower; system performance is dependent on the average path delay rather than the critical path delay, with higher performance potential.

Asynchronous circuit data communication relies on asynchronous transfer protocols and can be classified into three types according to timing methods: 1) delay-insensitive (DI); 2) data Binding (BD); 3) Quasi-Delay-Insensitive (QDI)/time-pipelined (TP)/single-track (ST). For DI circuits, it is not practical since they do not assume gate, line delays, resulting in a circuit that contains only buffer cells and C-Muller cells. For BD circuits, their implementation relies on bundled gates, line delays similar to synchronous circuits, and therefore presents certain design challenges. For TP and ST circuits, they require timing constraints and are complex. The QDI circuit does not need to carry out time sequence constraint on a logic gate and a signal wire, and is simple in design; the data completion condition is detected according to the actual working load and the operation condition, and the method is most practical; the method adapts to unknown PVT changes and has strong robustness.

Among QDI circuits, there are circuit types such as PCHB (precharge Half Buffer) and SAHB (Sense Amplifier Half Buffer). The PCHB standard cell employs an asynchronous QDI protocol, working under the assumption that the wire fork (wire fork) between the LCD and functional block F is isochronous. PCHB has the advantages of low power consumption, strong robustness, etc., and has been successfully implemented commercially, but it also has the disadvantages of large area, not fast enough speed, unsuitability for sub-threshold operation, etc.

The existing SAHB is an asynchronous QDI four-phase protocol, and a schematic diagram thereof is shown in FIG. 1. Compared with PCHB, SAHB has the advantages of small area, low energy consumption and the like, but the defects are also obvious: the existing SAHB consists of two parts, namely an operation block and an amplification block, so that the area is not small enough; the pull-up network consists of nMOS and the number of transistors in series is large and therefore not fast enough.

Disclosure of Invention

The invention provides a semi-buffer of a sensitive amplifier, which solves the problems of large area, low speed and the like of the traditional semi-buffer of the sensitive amplifier.

The invention can be realized by the following technical scheme:

a sensitive amplifier semi-buffer comprises a transmission module and a handshake signal generation module, wherein the transmission module is used for data transmission, the handshake signal generation module is used for generating handshake signals according to transmitted data, a NOR gate structure is adopted, the input end of the NOR gate structure is connected with the output end of the transmission module, the output end of the NOR gate structure is set as handshake signals rock,

the transmission module includes a plurality of handshake signal transistors and a plurality of logic transistors, the handshake signal transistors including: a first handshake signal transistor M1, a second handshake signal transistor M4, a third handshake signal transistor M7; the logic transistor includes: a first logic transistor M2, a second logic transistor M3, a third logic transistor M5, a fourth logic transistor M6;

the gate of the first logic transistor M2 is set as the input data A.F port, the source is connected to the drain of the first handshake signal transistor M1, the drain is connected to the drain of the second handshake signal transistor M4, the drain of the third logic transistor M5 and the output Q.T, and meanwhile, the gate is connected to the gate of the fourth logic transistor M6;

the gate of the second logic transistor M3 is set as the input data A.T port, the source is connected with the drain of the first handshake signal transistor M1, the drain is connected with the drain of the fourth logic transistor M6, the drain of the third handshake signal transistor M7 and the output terminal Q.F, and is also connected with the gate of the third logic transistor M5;

the gate of the third logic transistor M5 is connected to the output terminal Q.F, the source is grounded, and the drain is connected to the drain of the first logic transistor M2 and the drain of the second handshake signal transistor M4;

the gate of the fourth logic transistor M6 is connected to the output terminal Q.T, the source is grounded, and the drain is connected to the drain of the second logic transistor M3 and the drain of the third handshake signal transistor M7;

the grid electrode of the first handshake signal transistor M1 is connected with a handshake signal Rack, the source electrode is connected with a power supply VDD, and the drain electrode is connected with the source electrode of the first logic transistor M2 and the source electrode of the second logic transistor M3;

the gate of the second handshake signal transistor M4 is connected to the handshake signal Rack, the source is grounded, and the drain is connected to the drain of the first logic transistor M2 and the drain of the third logic transistor M5;

the gate of the third handshake signal transistor M7 is connected to the handshake signal Rack, the source is grounded, and the drain is connected to the drain of the second logic transistor M3 and the drain of the fourth logic transistor M6;

and the handshake signal Rack is set as a handshake output signal of the last adjacent asynchronous module on the same line.

Further, the handshake signal generation module includes a fourth handshake signal transistor M8, a fifth handshake signal transistor M9, a sixth handshake signal transistor M10, and a seventh handshake signal transistor M11, and input ends thereof are connected to the output ends Q.T and Q.F.

The beneficial technical effects of the invention are as follows:

the SAHB of the invention only uses 11 transistors, thus reducing the area compared with the 33 transistors of the prior SAHB; and a logic complementary signal of a data signal is not used, so that the complexity of the signal is reduced, and the operation speed is improved.

Drawings

FIG. 1 is a schematic diagram of the general circuit structure of a prior art sense amplifier half buffer of the present invention;

FIG. 2 is a schematic diagram of the general circuit structure of the sense amplifier half-buffer of the present invention;

FIG. 3 is a schematic diagram of an equivalent circuit of a sense amplifier composed of logic transistors M2, M3, M5 and M6 according to the present invention.

Detailed Description

The following detailed description of the preferred embodiments will be made with reference to the accompanying drawings.

As shown in fig. 2, the present invention provides a sense amplifier half buffer, which includes a transmission module and a handshake signal generation module, where the transmission module is used for data transmission, and an input end of the transmission module is connected to handshake output signals of an adjacent previous asynchronous module on the same line in addition to input data to be transmitted; the handshake signal generation module is used for generating handshake signals according to transmitted data, adopts a NOR gate structure, has an input end connected with an output end of the transmission module, and has an output end set as handshake signal Lack, and the specific steps are as follows:

the transmission module includes a plurality of handshake signal transistors and a plurality of logic transistors, the handshake signal transistors including: a first handshake signal transistor M1, a second handshake signal transistor M4, a third handshake signal transistor M7; the logic transistor includes: a first logic transistor M2, a second logic transistor M3, a third logic transistor M5, a fourth logic transistor M6;

the gate of the first logic transistor M2 is set as the input data A.F port, the source is connected to the drain of the first handshake signal transistor M1, the drain is connected to the drain of the second handshake signal transistor M4, the drain of the third logic transistor M5 and the output Q.T, and meanwhile, the gate is connected to the gate of the fourth logic transistor M6;

the gate of the second logic transistor M3 is set as the input data A.T port, the source is connected with the drain of the first handshake signal transistor M1, the drain is connected with the drain of the fourth logic transistor M6, the drain of the third handshake signal transistor M7 and the output terminal Q.F, and is also connected with the gate of the third logic transistor M5;

the gate of the third logic transistor M5 is connected to the output terminal Q.F, the source is grounded, and the drain is connected to the drain of the first logic transistor M2 and the drain of the second handshake signal transistor M4;

the gate of the fourth logic transistor M6 is connected to the output terminal Q.T, the source is grounded, and the drain is connected to the drain of the second logic transistor M3 and the drain of the third handshake signal transistor M7;

the grid electrode of the first handshake signal transistor M1 is connected with a handshake signal Rack, the source electrode is connected with a power supply VDD, and the drain electrode is connected with the source electrode of the first logic transistor M2 and the source electrode of the second logic transistor M3;

the gate of the second handshake signal transistor M4 is connected to the handshake signal Rack, the source is grounded, and the drain is connected to the drain of the first logic transistor M2 and the drain of the third logic transistor M5;

the gate of the third handshake signal transistor M7 is connected to the handshake signal Rack, the source is grounded, and the drain is connected to the drain of the second logic transistor M3 and the drain of the fourth logic transistor M6;

and the handshake signal Rack is set as a handshake output signal of the last adjacent asynchronous module on the same line.

It can be seen that the gates of the first logic transistor M2 and the second logic transistor M3 constitute the dual-rail signals A.T and A.F of the input data, wherein the first logic transistor M2 is A.F, and the second logic transistor M3 is A.T. The gates of the third logic transistor M5 and the fourth logic transistor M6 are connected to the dual-rail signals Q.T and Q.F for outputting data, wherein the third logic transistor M5 is Q.F, and the fourth logic transistor M6 is Q.T. The gates of the first handshake transistor M1, the second handshake transistor M4, and the third handshake transistor M7 are input terminals for handshake output signals of the previous asynchronous module.

The handshake signal generation module includes a fourth handshake signal transistor M8, a fifth handshake signal transistor M9, a sixth handshake signal transistor M10, and a seventh handshake signal transistor M11, the input terminals of which are connected to the output terminals Q.T and Q.F.

The sense amplifier half-buffer SAHB of the present invention also adheres to a four-phase handshake protocol, which includes two alternating operations: evaluate and reset. When reset, the input handshake signal Rack is 1, which indicates that the input data is invalid, i.e., null, i.e., the input terminal A.T is A.F is 0. At this time, the first handshake signal transistor M1 in the pull-up logic is turned off, and the pull-up circuit is not turned on; the second handshake signal transistor M4 and the third handshake signal transistor M7 in the pull-down logic are turned on, the output signal Q.T is Q.F is 0, and the output handshake signal Lack is obtained through the nor gate in the handshake signal generation module, which indicates that the output is empty.

When evaluating, the input handshake signal Rack is 0 and the input data is valid, i.e. not empty. At this time, the first handshake signal transistor M1 in the pull-up logic is turned on, the second handshake signal transistor M4 and the third handshake signal transistor M7 in the pull-down logic are turned off, the logic transistors M2, M3, M5, and M6 form a sense amplifier, and an equivalent circuit is shown in fig. 3.

When the input data is 1, that is, the input terminal A.T is 1 and the input terminal A.F is 0, the first logic transistor M2 is turned on, the second logic transistor M3 is turned off, and the output terminal Q.T is pulled up to 1, so that the fourth logic transistor M6 is turned on and the output terminal Q.F is kept at 0; the 0 at the output Q.F keeps the third logic transistor M5 turned off, thereby ensuring that the output Q.T is not pulled low to 1, when the output handshake signal Lack is 0, indicating that the output data is valid.

When the input data is 0, that is, the input terminal A.T is 0 and the input terminal A.F is 1, the first logic transistor M2 is turned off, the second logic transistor M3 is turned on, and the output terminal Q.F is pulled high to 1, so that the third logic transistor M5 is turned on, and the output terminal Q.T is kept at 0; the 0 at the output Q.T keeps the fourth logic transistor M6 turned off, thereby ensuring that the output Q.F is not pulled low to 1, when the output handshake signal Lack is 0, indicating that the output data is valid.

The existing SAHB, as shown in FIG. 1, contains two modules: a calculation block and a sense amplifier block. The calculation block includes an input acknowledge signal Rack and a logic section, and the pull-up section and the pull-down section all use nMOS transistors to reduce parasitic capacitance. The logic part of the computing block is similar to that of the combinational circuit, and the Rack signal is used for controlling output; the pull-up part of the sense amplifier block is controlled by the input signal and the Rack signal together, and when the data is valid and the Rack signal is 0, the lower half of the sense amplifier is connected to the power supply VDD to amplify the output.

Whereas the SAHB of the present invention considers combining a computation block and a sense amplifier block to reduce an area and replacing a pull-up portion of the computation block with a pMOS transistor to increase an output speed. A pull-up circuit of an existing SAHB standard unit computing block is replaced by a pMOS transistor, a pull-down circuit is replaced by the lower half portion of a sensitive amplifier, the pull-up circuit and the pull-down circuit jointly form the sensitive amplifier, and whether the amplifier works or not is controlled by a handshaking signal Rack. When the handshake signal Rack is 0, the amplifier should function to amplify and latch the output; when the acknowledge signal Rack is 1, the amplifier should be turned off and the circuit to VSS should be turned on, pulling the output low.

Therefore, the SAHB of the present invention uses only 11 transistors, reducing the area compared to the 33 transistors of the prior SAHB; and a logic complementary signal of a data signal is not used, so that the complexity of the signal is reduced, and the operation speed is improved.

It should be noted that the present invention is not limited to the buffer, and the first logic transistor M2 and the second logic transistor M3 may be replaced by pull-up logic of other logic circuits, such as nand or nor, and thus may be an asynchronous logic unit using the SAHB logic.

Although specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely examples and that many variations or modifications may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is therefore defined by the appended claims.