Magnetic recording array
阅读说明：本技术 磁记录阵列 (Magnetic recording array ) 是由 佐佐木智生 于 2020-03-05 设计创作，主要内容包括：本实施方式的磁记录阵列(200)具备多个自旋元件(100)和与相邻的第一自旋元件和第二自旋元件连接的共用晶体管(STr),所述多个自旋元件分别具有配线(20)和层叠于所述配线的包含第一铁磁性层(1)的层叠体(10),所述共用晶体管具有第一栅极(G1)、第二栅极(G2)、第一区域(A1)、第二区域(A2)和第三区域(A3),在从所述层叠体的层叠方向俯视时,所述第一区域被所述第一栅极和所述第二栅极夹着,所述第二区域和所述第一区域夹着所述第一栅极,所述第三区域和所述第一区域夹着所述第二栅极,所述第二区域和第三区域中的一者与所述第一自旋元件连接,另一者与所述第二自旋元件连接。(A magnetic recording array (200) of the present embodiment includes a plurality of spin elements (100) each having a wiring (20) and a stacked body (10) including a first ferromagnetic layer (1) stacked on the wiring, and a common transistor (STr) connected to the adjacent first spin element and second spin element, the common transistor having a first gate (G1), a second gate (G2), a first region (A1), a second region (A2), and a third region (A3), the first region being sandwiched between the first gate and the second gate, the second region and the first region sandwiching the first gate, the third region and the first region sandwiching the second gate, and one of the second region and the third region being connected to the first spin element when viewed in plan from the stacked direction of the stacked body, the other is connected to the second spin element.)
1. A magnetic recording array, characterized by:
provided with a plurality of spin elements and a common transistor connected to the adjacent first spin element and second spin element,
each of the spin elements has a wiring and a laminated body including a first ferromagnetic layer laminated on the wiring,
the common transistor has a first gate, a second gate, a first region, a second region, and a third region,
when viewed from above in the stacking direction of the stacked body,
the first region is sandwiched by the first gate and the second gate,
the second region and the first region sandwich the first gate,
the third region and the first region sandwich the second gate,
one of the second and third regions is connected to the first spin element, and the other is connected to the second spin element.
2. The magnetic recording array of claim 1,
there is a plurality of said common transistors,
the semiconductor device further includes a first wiring connected to the first region of the plurality of common transistors.
3. The magnetic recording array of claim 2,
the semiconductor device further includes a first wiring control transistor connected to the first wiring.
4. The magnetic recording array of claim 2 or 3,
a plurality of the first wiring lines are provided,
the adjacent first wirings are connected via a short-circuit transistor.
5. The magnetic recording array of any of claims 1-4,
the spin memory further includes a second wire connected to the stack of the plurality of spin elements.
6. The magnetic recording array of claim 5,
and a second wiring control transistor connected to the second wiring.
7. The magnetic recording array of any of claims 1-6,
the semiconductor device further includes a first gate line connected to the first gate and a second gate line connected to the second gate.
8. The magnetic recording array of claim 7,
the first gate wiring and the second gate wiring are at different heights.
9. The magnetic recording array of any of claims 1-8,
the common transistor has a first common transistor, a second common transistor and a third common transistor,
the first spin element is connected to the second regions of the first and second common transistors,
the second spin element is connected to the third regions of the second common transistor and the third common transistor.
10. The magnetic recording array of any of claims 1-9,
at least one of the plurality of spin elements is a first reference element in which the resistance of the wiring is higher than the other spin elements,
at least one of the plurality of spin elements is a second reference element in which the wiring has a lower resistance than the other spin elements.
11. The magnetic recording array of any of claim 10,
the wiring width of the wiring of the first reference element is narrower than the wiring widths of the other spin elements,
the wiring width of the wiring of the second reference element is wider than the wiring widths of the other spin elements.
12. The magnetic recording array of any of claims 1-11,
the laminated body has the first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer from a side close to the wiring,
the wiring is any of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide, which have a function of generating spin current by a spin hall effect when a current flows.
13. The magnetic recording array of any of claims 1-11,
the laminated body has a nonmagnetic layer and the first ferromagnetic layer from a side close to the wiring,
the wiring is a ferromagnetic layer capable of having a magnetic domain wall inside.
Technical Field
The present invention relates to a magnetic recording array.
Background
A new generation of nonvolatile memory, which replaces flash memory and the like, which are seen as limitations in the refinement, is attracting attention. As a new generation of nonvolatile memory, for example, mram (magnetic Random Access memory), reram (resistance Random Access memory), pcram (phase Change Random Access memory), and the like are known.
MRAM is a memory element using a magnetoresistive effect element. The resistance value of the magnetoresistance effect element varies depending on the difference in the relative angle of the directions of magnetization of the two magnetic films. The MRAM records the resistance value of the magnetoresistive effect element as data.
Among spin elements utilizing magnetoresistance change, a spin orbit torque type magnetoresistance effect element (for example, patent document 1) utilizing Spin Orbit Torque (SOT) or a domain wall movement type magnetic recording element (for example, patent document 2) utilizing movement of a magnetic domain wall attracts attention.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2017-216286.
Patent document 2: japanese patent No. 5441005.
Disclosure of Invention
Problems to be solved by the invention
In the 3-terminal type spin element, a current path at the time of writing data is different from a current path at the time of reading data. These spin elements require a plurality of transistors in order to control the read current and the write current, respectively. That is, in order to operate one spin element, it is necessary to secure an area corresponding to a plurality of transistors.
The present invention has been made in view of the above problems, and an object thereof is to provide a magnetic recording array capable of improving integration.
Means for solving the problems
(1) A first aspect provides a magnetic recording array including a plurality of spin elements each having a wiring and a stacked body including a first ferromagnetic layer stacked on the wiring, and a common transistor connected to a first spin element and a second spin element adjacent to each other, the common transistor including a first gate, a second gate, a first region, a second region, and a third region, the first region being sandwiched between the first gate and the second gate, the second region and the first region sandwiching the first gate, the third region and the first region sandwiching the second gate, one of the second region and the third region being connected to the first spin element, and the other being connected to the second spin element, when viewed in a plan view from a stacking direction of the stacked body.
(2) The magnetic recording array of the above-described aspect may further include a plurality of the common transistors, and a first wiring connected to the first region of the plurality of the common transistors.
(3) The magnetic recording array of the above aspect may further include a first wiring control transistor connected to the first wiring.
(4) In the magnetic recording array of the above aspect, a plurality of the first wirings may be provided, and the adjacent first wirings may be connected to each other via a short-circuit transistor.
(5) The magnetic recording array of the above aspect may further include a second wiring connected to the laminated body of the plurality of spin elements.
(6) The magnetic recording array of the above aspect may further include a second wiring control transistor connected to the second wiring.
(7) The magnetic recording array of the above aspect may further include a first gate wiring connected to the first gate and a second gate wiring connected to the second gate.
(8) In the magnetic recording array of the above aspect, the first gate wiring and the second gate wiring may be at different heights.
(9) In the magnetic recording array according to the above aspect, the common transistor may include a first common transistor, a second common transistor, and a third common transistor, the first spin element may be connected to the second region of the first common transistor and the second common transistor, and the second spin element may be connected to the third region of the second common transistor and the third common transistor.
(10) In the magnetic recording array of the above aspect, at least one of the plurality of spin elements may be a first reference element in which the resistance of the wire is higher than that of the other spin elements, and at least one of the plurality of spin elements may be a second reference element in which the resistance of the wire is lower than that of the other spin elements.
(11) In the magnetic recording array of the above aspect, the wiring width of the wiring of the first reference element may be narrower than the wiring widths of the other spin elements, and the wiring width of the wiring of the second reference element may be wider than the wiring widths of the other spin elements.
(12) In the magnetic recording array according to the above aspect, the laminated body may include the first ferromagnetic layer, the nonmagnetic layer, and the second ferromagnetic layer from a side close to the wiring, and the wiring may be any of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide, which have a function of generating a spin current by a spin hall effect when a current flows.
(13) In the magnetic recording array of the above aspect, the laminated body may have a nonmagnetic layer and the first ferromagnetic layer from a side close to the wiring, and the wiring may be a ferromagnetic layer capable of having a magnetic domain wall therein.
Effects of the invention
The magnetic recording array of the above-described embodiment is excellent in integration.
Drawings
FIG. 1 is a circuit diagram of a magnetic recording array of a first embodiment.
FIG. 2 is a cross-sectional view of the magnetic recording array of the first embodiment.
FIG. 3 is a top view of the magnetic recording array of the first embodiment.
Fig. 4 is a sectional view of the spin element of the first embodiment.
FIG. 5 is a circuit diagram of a magnetic recording array of a second embodiment.
FIG. 6 is a circuit diagram of a magnetic recording array of a third embodiment.
Fig. 7 is a sectional view of a spin element of a fourth embodiment.
Fig. 8 is a sectional view of a spin element of the fifth embodiment.
Detailed Description
Hereinafter, the present embodiment will be described in detail with reference to the drawings as appropriate. In the drawings used in the following description, a part to be a feature may be enlarged at low cost in order to facilitate understanding of the feature, and the dimensional ratio of each component may be different from the actual one. The materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited thereto, and can be appropriately modified and implemented within a range in which the effects of the present invention are achieved.
First, the direction is defined. One direction of one surface of a substrate Sub (see fig. 2) described later is referred to as an x direction, and a direction orthogonal to the x direction is referred to as a y direction. The x direction is, for example, a row direction in which spin elements are arranged in a magnetic recording array described later. The y direction is, for example, a column direction in which spin elements are arranged in a magnetic recording array described later. The z direction is a direction orthogonal to the x direction and the y direction. The z direction is an example of the stacking direction. Hereinafter, the + z direction is sometimes expressed as "up" and the-z direction is sometimes expressed as "down". Up and down do not necessarily coincide with the direction in which the weight is applied.
(first embodiment)
FIG. 1 is a circuit diagram of a magnetic recording array 200 of a first embodiment. Magnetic recording array 200 has an integration area IA and a peripheral area PA.
The integration area IA is an area where the plurality of magnetoresistance effect elements 100 are integrated. The magnetoresistive element 100 is an example of a spin element. The integrated area IA includes, for example, a plurality of magnetoresistance effect elements 100, a plurality of common transistors STr, a plurality of first wirings L1, a plurality of second wirings L2, a plurality of first gate wirings GL1, and a plurality of second gate wirings GL 2. The recording density of magnetic recording array 200 is increased if the integration in integration area IA is increased.
The magnetoresistive elements 100 are arranged in a matrix, for example. The common transistor STr is, for example, between the magnetoresistive effect elements 100 adjacent in the x direction. The common transistor STr is a member that combines two transistors Tr. The common transistor STr is connected to each of two magnetoresistive effect elements 100 adjacent in the x direction, for example. One magnetoresistance effect element 100 connected to the common transistor STr is sometimes referred to as a first magnetoresistance effect element, and the other magnetoresistance effect element 100 is sometimes referred to as a second magnetoresistance effect element. The first magnetoresistance element is an example of a first spin element, and the second magnetoresistance element is an example of a second spin element.
The first wiring L1 is connected to a wiring 20 of the magnetoresistive element 100, which will be described later, via the transistor Tr, for example. The first wirings L1 extend in the y direction, for example, and are arranged in the x direction. The first wiring L1 is connected to each of the magnetoresistive elements 100 in the same column, for example.
The second wiring L2 is connected to, for example, a laminated body 10 of the magnetoresistive element 100, which will be described later. A switching element (e.g., a transistor) may be provided between the stacked body 10 and the second wiring L2. The second wirings L2 extend in the y direction, for example, and are arranged in the x direction. The second wiring L2 is connected to each of the magnetoresistive elements 100 in the same column, for example.
The first gate line GL1 is connected to a first gate G1, described later, of the common transistor STr. The first gate lines GL1 extend in the x direction and are arranged in the y direction, for example. The first gate line GL1 is connected to, for example, the common transistors STr in the same row.
The second gate line GL2 is connected to a second gate G2, described later, of the common transistor STr. The second gate lines GL2 extend in the x direction and are arranged in the y direction, for example. The second gate line GL2 is connected to, for example, the common transistors STr in the same row.
The peripheral area PA is an area where control elements for controlling the operation of the magnetoresistive element 100 in the integrated area IA are mounted. The peripheral area PA is, for example, outside the integration area IA. The peripheral region PA has, for example, a plurality of first wiring control transistors Tr3, a plurality of second wiring control transistors Tr4, a plurality of first gate transistors GTr1, and a plurality of second gate transistors GTr 2.
The first wiring control transistors Tr3 are connected to the first wirings L1, respectively. The first wiring control transistor Tr3 is connected to, for example, an end of the first wiring L1. The first wiring control transistor Tr3 controls a current flowing through the first wiring L1. By controlling the first wiring control transistor Tr3 and the transistor Tr, writing of data to the magnetoresistive element 100 can be controlled.
The second wiring control transistors Tr4 are connected to the second wirings L2, respectively. The second wiring control transistor Tr4 is connected to, for example, an end of the second wiring L2. The second wiring control transistor Tr4 controls the current flowing through the second wiring L2. By controlling the second wiring controlling transistor Tr4 and the transistor Tr, reading of data from the magnetoresistive element 100 can be controlled.
The first gate transistors GTr1 are connected to the first gate lines GL1, respectively. The first gate transistor GTr1 is connected to an end of the first gate line GL 1. The first gate transistor GTr1 controls a current flowing through the first gate line GL1, and controls on/off of one transistor Tr in the common transistor STr.
The second gate transistors GTr2 are connected to the second gate lines GL2, respectively. The second gate transistor GTr2 is connected to an end of the second gate line GL 2. The second gate transistor GTr2 controls the current flowing through the second gate line GL2, and controls the on/off of the one transistor Tr in the common transistor STr.
The first wiring control transistor Tr3, the second wiring control transistor Tr4, the first gate transistor GTr1, and the second gate transistor GTr2 are, for example, field effect transistors. The first wiring control transistor Tr3, the second wiring control transistor Tr4, the first gate transistor GTr1, and the second gate transistor GTr2 may be replaced with different switching elements. The switching element is, for example, an element utilizing a phase change of a crystal layer such as an Ovonic Threshold Switch (OTS), an element utilizing a change of a band structure such as a metal-insulator transition (MIT) Switch, an element utilizing a breakdown voltage such as a zener diode and an avalanche diode, or an element having a conductivity changing with a change of an atomic position.
FIG. 2 is a cross-sectional view of a magnetic recording array 200 of the first embodiment. Fig. 2 is an xz cross section passing through the center of the magnetoresistive effect element 100 in the y direction. In fig. 2, for the sake of explanation, the first gate line GL1 and the second gate line GL2 at different positions in the y direction are illustrated by broken lines. Fig. 3 is a plan view of the magnetic recording array 200 of the first embodiment as viewed in the z direction. Fig. 3 shows only the portion having conductivity extracted.
The magnetoresistance effect element 100 and the common transistor STr are on the substrate Sub. The magnetoresistive element 100 and the common transistor STr are connected by a via wiring V1. The magnetoresistive element 100 and the common transistor STr are located at different positions in the z direction and in different layers.
The magnetoresistive element 100, the common transistor STr, and the via wiring V1 are covered with an insulating layer In. The insulating layer In is an insulating layer for insulating the wiring of the multilayer wiring from one element to another. The insulating layer In is, for example, silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon carbide (SiC), chromium nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al)2O3) Zirconium oxide (ZrO)x) And the like.
The common transistor STr is, for example, an electric field effect transistor. The common transistor STr has a first gate G1, a second gate G2, a gate insulating film GI, a first region a1, a second region a2, and a third region A3.
The first region a1, the second region a2, and the third region A3 are source regions or drain regions of transistors. The first, second, and third regions a1, a2, and A3 are formed on the substrate Sub. The substrate Sub is, for example, a semiconductor substrate. The first region a1 is sandwiched by the first gate G1 and the second gate G2 when viewed from the z direction. The second region a2 and the first region a1 sandwich the first gate G1 when viewed from the z direction. The third region A3 and the first region a1 sandwich the second gate G2 when viewed from the z direction.
The first gate G1 controls the flow of charges between the first region a1 and the second region a 2. The second gate G2 controls the flow of charges between the second region a2 and the third region A3. The first region a1, the second region a2, and the first gate G1 function as one transistor Tr, and the first region a1, the third region A3, and the second gate G2 function as one transistor Tr.
The first region a1 is connected to the first wiring L1, for example. The first wiring L1 is connected to the first regions a1 of the plurality of common transistors STr adjacent to each other in the y direction, for example.
The second region a2 and the third region A3 are connected via the magnetoresistance effect element 100 and the via wiring V1. The second region a2 and the third region A3 are connected to different magnetoresistive effect elements 100. For example, the second region a2 is connected to the first magnetoresistance element 100A via wiring V1, and the third region is connected to the second magnetoresistance element 100B via a via wiring V1.
The first gate G1 is connected to the first gate line GL 1. The second gate G2 is connected to the second gate line GL 2. The first gate wiring GL1 and the second gate wiring GL2 are at different heights in the z direction, for example. If the first gate line GL1 and the second gate line GL2 have different heights in the z direction, connection of the lines becomes easy, and integration of the integration area IA improves.
In the common transistors STr adjacent to each other in the x direction, the arrangement order of the components constituting the common transistors STr is reversed. For example, three common transistors arranged in the x direction among the common transistors STr are referred to as a first common transistor STr1, a second common transistor STr2, and a third common transistor STr 3. The first common transistor STr1 is arranged in the x direction in the order of the third region A3, the second gate G2, the first region a1, the first gate G1, and the second region a2, whereas the second common transistor STr2 is arranged in the x direction in the order of the second region a2, the first gate G1, the first region a1, the second gate G2, and the third region A3.
The first and second common transistors STr1 and STr2 are connected to the first magnetoresistance element 100A, for example. The second common transistor STr2 and the third common transistor STr3 are connected to the second magnetoresistance effect element 100B, for example.
The first magnetoresistance element 100A is connected to the second region a2 of the first and second common transistors STr1 and STr2, respectively. That is, writing of data into the first magnetoresistance element 100A is controlled by the first gate G1 of the first common transistor STr1 and the second common transistor STr 2.
The second magnetoresistance element 100B is connected to the third region A3 of the second common transistor STr2 and the third common transistor STr3, respectively. That is, writing of data into the second magnetoresistance element 100B is controlled by the second gate G2 of the second common transistor STr2 and the third common transistor STr 3.
In the magnetoresistance effect element 100, an element for controlling writing by the first gate G1 (for example, the first magnetoresistance effect element 100A) and an element for controlling writing by the second gate G2 (for example, the second magnetoresistance effect element 100B) are alternately arranged in the x direction.
Fig. 4 is a sectional view of the magnetoresistance effect element 100 according to the first embodiment. Fig. 4 is a cross section of the magnetoresistive element 100 cut by an xz plane passing through the center of the y-direction width of the wiring 20.
The magnetoresistive element 100 includes, for example, a laminate 10, a wire 20, and conductive portions 31 and 32. The resistance value of the laminate 10 in the z direction changes due to spin injection from the wire 20 into the laminate 10. The magnetoresistance effect element 100 is a spin element using Spin Orbit Torque (SOT), and may be called a spin orbit torque type magnetoresistance effect element, a spin injection type magnetoresistance effect element, or a spin current magnetoresistance effect element. In addition, the wiring 20 is sometimes called a spin orbit torque wiring.
The laminate 10 is laminated on the wiring 20. Another layer may be provided between the laminate 10 and the wiring 20. The laminate 10 is sandwiched by the wiring 20 and the electrode E in the z direction. The stacked body 10 is a columnar body. The shape is, for example, a circle, an ellipse, or a quadrangle when viewed from the z direction of the laminate 10.
The laminate 10 has a first ferromagnetic layer 1, a second ferromagnetic layer 2, and a nonmagnetic layer 3. The first ferromagnetic layer 1 is, for example, in contact with the wiring 20, and is laminated on the wiring 20. Spins are injected from the wiring 20 into the first ferromagnetic layer 1. The magnetization of the first ferromagnetic layer 1 receives Spin Orbit Torque (SOT) by the injected spins, and the orientation direction changes. The second ferromagnetic layer 2 is in the z-direction of the first ferromagnetic layer 1. The first ferromagnetic layer 1 and the second ferromagnetic layer 2 sandwich the nonmagnetic layer 3 in the z direction.
The first ferromagnetic layer 1 and the second ferromagnetic layer 2 each have magnetization. When a predetermined external force is applied, the orientation direction of the magnetization of the second ferromagnetic layer 2 is less likely to change than the magnetization of the first ferromagnetic layer 1. The first ferromagnetic layer 1 is sometimes referred to as a magnetization free layer, and the second ferromagnetic layer 2 is sometimes referred to as a magnetization fixed layer or a magnetization reference layer. The laminated body 10 changes in resistance value according to the difference in relative angle of magnetization of the first ferromagnetic layer 1 and the second ferromagnetic layer 2 sandwiching the nonmagnetic layer 3.
The first ferromagnetic layer 1 and the second ferromagnetic layer 2 include a ferromagnetic material. The ferromagnetic material is, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, an alloy containing these metals and at least one or more of B, C and N, or the like. The ferromagnetic material is, for example, Co-Fe-B, Ni-Fe, Co-Ho alloy, Sm-Fe alloy, Fe-Pt alloy, Co-Pt alloy, or CoCrPt alloy.
The first ferromagnetic layer 1 and the second ferromagnetic layer 2 may also include a wheatstone alloy. The Wheatstone alloy comprises a metal having XYZ or X2Intermetallic compounds of chemical composition YZ. X is a transition metal element or a noble metal element of Co, Fe, Ni, or Cu group on the periodic table, Y is a transition metal of Mn, V, Cr, or Ti group or an element type of X, and Z is a typical element of III to V group. Wheatstone alloys being, for example, Co2FeSi、Co2FeGe、Co2FeGa、Co2MnSi、Co2Mn1－aFeaAlbSi1－b、Co2FeGe1－cGacAnd the like. Wheatstone alloys have a high spin polarizability.
The laminate 10 may have an antiferromagnetic layer on the surface of the second ferromagnetic layer 2 opposite to the nonmagnetic layer 3 with a spacer layer interposed therebetween. The second ferromagnetic layer 2, the spacer layer, and the antiferromagnetic layer are of a synthetic antiferromagnetic structure (SAF structure). The synthetic antiferromagnetic structure is composed of two magnetic layers sandwiching a nonmagnetic layer. Since the second ferromagnetic layer 2 and the antiferromagnetic layer are antiferromagnetically coupled, the coercive force of the second ferromagnetic layer 2 becomes large as compared with the case where there is no antiferromagnetic layer. The antiferromagnetic layer is, for example, IrMn, PtMn, or the like. The spacer layer contains at least one selected from the group consisting of Ru, Ir, and Rh, for example.
The laminate 10 may have layers other than the first ferromagnetic layer 1, the second ferromagnetic layer 2, and the nonmagnetic layer 3. For example, the base layer may be provided between the wiring 20 and the laminate 10. The underlayer improves the crystallinity of each layer constituting the laminate 10.
The wiring 20 is, for example, in contact with one surface of the laminate 10. The wiring 20 is a write wiring for writing data to the magnetoresistive element 100. The wiring 20 extends in the x direction. At least a part of the wiring 20 sandwiches the first ferromagnetic layer 1 in the z direction together with the nonmagnetic layer 3.
The wiring 20 generates a spin current by the spin hall effect when the current I flows, and injects a spin into the first ferromagnetic layer 1. The wiring 20 imparts Spin Orbit Torque (SOT) to the magnetization of the first ferromagnetic layer 1 by an amount that can invert the magnetization of the first ferromagnetic layer 1, for example. The spin hall effect is a phenomenon in which a spin current is induced in a direction orthogonal to a flowing direction of a current based on a spin orbit interaction when the current is caused to flow. The spin hall effect is common to the ordinary hall effect at the point where the moving charge (electrons) bends the direction of motion (movement). In the case of the usual hall effect, the direction of movement of charged particles moving in a magnetic field is bent due to the lorentz force. In contrast, in the spin hall effect, the direction of movement of the spin is bent by the amount of movement of the electrons (the amount of current flow) even in the absence of a magnetic field.
For example, if a current flows through the wiring 20, a first spin oriented in one direction and a second spin oriented in a direction opposite to the first spin are bent by the spin hall effect in a direction orthogonal to the direction in which the current I flows, respectively. For example, a first spin oriented in the-y direction is curved in the + z direction, and a second spin oriented in the + y direction is curved in the-z direction.
In a non-magnetic body (a material that is not a ferromagnetic body), the number of electrons of the first spin and the number of electrons of the second spin generated by the spin hall effect are equal. That is, the number of electrons having the first spin directed in the + z direction is equal to the number of electrons having the second spin directed in the-z direction. The first spin and the second spin flow in a direction to eliminate the polarization of the spins. In the movement of the first spin and the second spin in the z direction, the flows of the charges cancel each other, so that the amount of current is zero. Spin current that does not accompany current is particularly referred to as pure spin current.
If the electron current of the first spin is denoted as J↑The electron current of the second spin is denoted as J↓Denote spin current as JSAccording to JS＝J↑－J↓And (4) defining. Spin current JSGenerated along the z direction. The first spin is injected from the wiring 20 into the first ferromagnetic layer 1.
The wiring 20 includes any of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide, which have a function of generating a spin current by the spin hall effect when the current I flows.
The wiring 20 contains, for example, a nonmagnetic heavy metal as a main element. The main element is the element having the highest proportion among the elements constituting the wiring 20. The wiring 20 contains, for example, a heavy metal having a specific gravity of yttrium (Y) or more. The nonmagnetic heavy metal has a large atomic number of 39 or more and has d or f electrons in the outermost layer, and therefore generates a strong spin-orbit interaction. The spin hall effect is generated by spin orbit interaction, and spins are easily biased in the wiring 20, and a spin current J is easily generatedS. The wiring 20 includes, for example, any one selected from the group consisting of Au, Hf, Mo, Pt, W, and Ta.
The wiring 20 may also contain a magnetic metal. The magnetic metal is a ferromagnetic metal or an antiferromagnetic metal. The nonmagnetic material contains a small amount of magnetic metal as a spin scattering factor. The trace amount is, for example, 3% or less of the total molar ratio of the elements constituting the wiring 20. If spins are scattered due to the magnetic metal, the spin-orbit interaction is enhanced, and the generation efficiency of spin current with respect to current is improved.
The wiring 20 may also include a topological insulator. The topological insulator is a substance in which an insulator or a high-resistance body is present inside the substance, but a spin-polarized metallic state is generated on the surface thereof. The topological insulator generates an internal magnetic field through spin-orbit interaction. The topological insulator exhibits a new topological phase by the effect of spin-orbit interaction even in the absence of an external magnetic field. Topological insulators are able to efficiently generate pure spin currents through strong spin-orbit interactions and the breaking of the inversion symmetry of the edges.
Topological insulators being, e.g., SnTe, Bi1.5Sb0.5Te1.7Se1.3、TlBiSe2、Bi2Te3、Bi1－xSbx、(Bi1－ xSbx)2Te3And the like. The topological insulator is capable of efficiently generating spin current.
The conductive portions 31 and the conductive portions 32 sandwich the laminate 10 in the x direction when viewed from the z direction. The conductive portions 31 and 32 are connected to, for example, via wiring V1. The conductive portions 31 and 32 are made of a material having excellent conductivity. The conductive portions 31 and 32 include any one selected from the group consisting of Ag, Cu, Co, Al, and Au, for example.
Next, a method of manufacturing the integration area IA of the magnetic recording array 200 will be described. The integrated area IA is formed by a lamination process of each layer and a processing process of processing a part of each layer into a predetermined shape. The layers can be stacked by a sputtering method, a Chemical Vapor Deposition (CVD) method, an electron beam evaporation method (EB evaporation method), an atomic laser deposition method, or the like. The layers can be processed by photolithography or the like.
First, impurities are doped at predetermined positions of the substrate Sub to form a first region a1, a second region a2, and a third region A3.
Next, an insulating layer of a certain thickness is formed on the substrate Sub. For example, an opening is formed in the insulating layer by anisotropic etching. The opening is formed at a position between the first region a1 and the third region A3 when viewed from above in the z direction. The opening does not penetrate to the substrate Sub, leaving an insulating film at the bottom. The insulating film remaining on the bottom becomes the gate insulating film GI. The opening is filled with a conductor to become the second gate G2.
Next, a conductive layer is stacked over the insulating layer, and the conductive layer is processed to form the second gate line GL 2. The second gate wiring GL2 is connected to the second gates G2 arranged in the x direction.
Next, an insulating layer covering the second gate line GL2 is stacked. For example, an opening is formed in the insulating layer by anisotropic etching. The opening is formed at a position between the first region a1 and the second region a2 when viewed from above in the z direction. The opening does not penetrate to the substrate Sub, leaving an insulating film at the bottom. The insulating film remaining on the bottom becomes the gate insulating film GI. The opening is filled with a conductor to become the first gate G1.
Next, a conductive layer is stacked over the insulating layer, and the conductive layer is processed to form the first gate line GL 1. The first gate wiring GL1 is connected to the first gates G1 arranged in the x direction.
Next, an insulating layer covering the second gate line GL2 is stacked. For example, an opening is formed in the insulating layer by anisotropic etching. The opening is formed at a position overlapping with the second region a2 and the third region A3 when viewed from above in the z direction. The opening reaches the surface of the substrate Sub. The opening is filled with a conductor to form a via wiring V1.
Next, after an insulating layer covering the via hole wiring V1 is overlapped, the conductive portions 31 and 32 are formed at positions overlapping the via hole wiring V1. The conductive portions 31 and 32 are made of a material harder than the via wiring V1, for example. The surfaces of the insulating and conductive portions 31, 32 are subjected to Chemical Mechanical Polishing (CMP). By using a hard material for the conductive portions 31 and 32, the flatness of the surface is improved.
Next, the wiring layer, the ferromagnetic layer, the nonmagnetic layer, and the ferromagnetic layer are stacked in this order on the surfaces of the insulating layer and the conductive portions 31 and 32. Next, the wiring layer is processed into a predetermined shape. The wiring layer is processed into a predetermined shape to form a wiring 20. Next, the laminated body formed on the wiring layer is processed into a predetermined shape to form the laminated body 10, thereby obtaining the magnetoresistive element 100. Through the above steps, the integration area IA of the magnetic recording array 200 can be manufactured.
Next, the operation of the magnetic recording array 200 according to the first embodiment will be described. The operation of the magnetic recording array 200 includes a write operation and a read operation of the magnetoresistive element 100.
First, a writing operation of any magnetoresistive element 100 will be described. The case of writing data into the first magnetoresistance element 100A as an arbitrary magnetoresistance element 100 will be described as an example.
First, the first gate transistor GTr1 connected to the first magnetoresistance element 100A is turned ON (ON). When the first gate transistor GTr1 is turned on, the first gate G1 connected to the first gate line GL1 is opened. The first region a1 and the second region a2 of the shared transistor STr are electrically connected.
Next, the first wiring control transistor Tr3 connected to the first wiring L1 is turned on, and the first wiring control transistor Tr3 is connected to the first common transistor STr1 and the second common transistor STr 2. Since the two adjacent first wirings L1 are electrically connected with the first magnetoresistance element 100A interposed therebetween, the write current flows through the wiring 20. On the other hand, since the second gate G2 is not opened, the write current does not flow through the second magnetoresistance element 100B.
If a write current flows through the wiring 20, a spin hall effect is generated, and spin is injected into the first ferromagnetic layer 1. The spin injected into the first ferromagnetic layer 1 applies Spin Orbit Torque (SOT) to the magnetization of the first ferromagnetic layer 1, changing the orientation direction of the magnetization of the first ferromagnetic layer 1. If the direction of current flow is reversed, the direction of the spin injected into the first ferromagnetic layer 1 is reversed, and therefore the direction of magnetization can be freely controlled.
The resistance value in the lamination direction of the laminated body 10 becomes small when the magnetization of the first ferromagnetic layer 1 and the magnetization of the second ferromagnetic layer 2 are parallel to each other, and becomes large when the magnetization of the first ferromagnetic layer 1 and the magnetization of the second ferromagnetic layer 2 are antiparallel to each other. Data is recorded as the resistance value in the lamination direction of the laminated body 10 in the magnetoresistance effect element 100.
Next, first, a reading operation of data from any of the magnetoresistive elements 100 will be described. The case of reading data from the first magnetoresistance element 100A as an arbitrary magnetoresistance element 100 will be described as an example.
When data is read, first, the first gate transistor GTr1 connected to the first magnetoresistance element 100A is also turned ON (ON). When the first gate transistor GTr1 is turned on, the first gate G1 connected to the first gate line GL1 is opened. The first region a1 and the second region a2 of the shared transistor STr are electrically connected.
Next, the second wiring control transistor Tr4 connected to the second wiring L2 is turned on, and the second wiring control transistor Tr4 is connected to the first magnetoresistance element 100A. The first wiring control transistor Tr3 connected to the first wiring L1 is turned on, and the first wiring L1 is connected to the first common transistor STr1 or the second common transistor STr 2. Since the first wiring L1 and the second wiring L2 are electrically connected, the sense current flows in the stacking direction of the stack 10. On the other hand, since the second gate G2 is not opened, the read current does not flow through the second magnetoresistance element 100B.
If the resistance value in the lamination direction of the laminated body 10 changes according to ohm's law, the output voltage changes. Therefore, for example, by reading the voltage in the stacking direction of the stacked body 10, the data recorded in the first magnetoresistance element 100A can be read.
The magnetic recording array 200 of the first embodiment can improve the integration of the integration area IA. The first region a1 of the common transistor STr functioning as the two transistors Tr also serves as the source region or the drain region of the two transistors, and therefore the common transistor STr requires a smaller area than the case where the two transistors Tr are arranged. Therefore, the distance between the magnetoresistive elements 100 adjacent in the x direction can be shortened, and the integration of the integration area IA can be improved.
The first embodiment has been described as an example, but the present invention is not limited to this example.
(second embodiment)
FIG. 5 is a circuit diagram of a magnetic recording array 201 of a second embodiment. With the magnetic recording array 201 of the second embodiment, the point at which a part of the magnetoresistive effect element 100 within the integration area IA1 is the first reference element 101 and the second reference element 102 is different from the magnetic recording array 200 of the first embodiment. In the second embodiment, the same configurations as those of the first embodiment will not be described.
The first reference element 101 and the second reference element 102 are present in one column, for example. The first reference element 101 and the second reference element 102 are connected to one first wiring L1 one by one, for example. The number of the first reference elements 101 and the second reference elements 102 is not limited to this case. The first reference element 101 and the second reference element 102 each reside at least one by one within the magnetic recording array 201.
The first reference element 101 has the same configuration as the magnetoresistance effect element 100 except for the point where the resistance of the wiring 20 is higher than the resistance of the magnetoresistance effect element 100. The resistance of the wiring 20 of the first reference element 101 may be, for example, 105% or more, or 110% or more of the resistance of the wiring 20 of the magnetoresistive element 100.
The difference in resistance between the first reference element 101 and the magnetoresistance effect element 100 can be freely designed by changing the width, thickness, and material of the wiring 20. For example, the width of the wiring 20 of the first reference element 101 is narrower than the width of the wiring 20 of the magnetoresistance effect element 100. The width of the wiring 20 of the first reference element 101 is, for example, 95% or less, or may be 90% or less of the width of the wiring 20 of the magnetoresistance effect element 100.
The second reference element 102 has the same structure as the magnetoresistance effect element 100 except for the point that the resistance of the wiring 20 is lower than the resistance of the magnetoresistance effect element 100. The resistance of the wiring 20 of the second reference element 102 is, for example, 95% or less, or may be 90% or less of the resistance of the wiring 20 of the magnetoresistive element 100.
The difference in resistance between the second reference element 102 and the magnetoresistance effect element 100 can be freely designed by changing the width, thickness, and material of the wiring 20. For example, the width of the wiring 20 of the second reference element 102 is wider than the width of the wiring 20 of the magnetoresistance effect element 100. The width of the wiring 20 of the second reference element 102 is, for example, 105% or more, or 110% or more of the width of the wiring 20 of the magnetoresistive element 100.
The first reference element 101 and the second reference element 102 are used for confirming whether or not the magnetoresistive element 100 is properly written.
For example, when the writing operation is performed on the magnetoresistance effect element 100, the same writing operation is performed on the first reference element 101 and the second reference element 102 paired with the magnetoresistance effect element 100. The first reference element 101 and the second reference element 102 paired with the magnetoresistance effect element 100 are, for example, the first reference element 101 and the second reference element 102 connected to the first wiring L1 similarly to the magnetoresistance effect element 100. The voltage applied to the wiring of each of the first reference element 101 and the second reference element 102 is set to be the same as that of the magnetoresistance effect element 100. The same load as that of the magnetoresistive element 100 is applied to the first reference element 101 and the second reference element, and the same data is written.
Next, the resistances of the magnetoresistance effect element 100, the first reference element 101, and the second reference element 102 are compared. The resistance value is, for example, the resistance between the electrode E and the conductive portion 32. The respective resistance values are obtained by applying a sense current. When operating properly, the first reference element 101 has a higher resistance than the magnetoresistance effect element 100. In addition, the resistance of the second reference element 102 is lower than that of the magnetoresistance effect element 100.
When the resistance of the magnetoresistance effect element 100 is not between the resistance of the first reference element 101 and the resistance of the second reference element 102, it can be determined that a failure has occurred in the magnetoresistance effect element 100.
One way of failure of the magnetoresistive element 100 is deterioration or breakage of the wiring 20 between the laminated body 10 and the conductive portions 31 and 32. If the wiring 20 is deteriorated or broken, an appropriate writing operation cannot be performed. For example, when the wiring 20 between the stacked body 10 and the conductive portion 31 is deteriorated or broken, the write operation cannot be performed, but the read operation can be performed. This is because the write current flowing between the conductive portion 31 and the conductive portion 32 does not flow normally, but the read current flows normally between the stacked body 10 and the conductive portion 32. In this case, the data is read without noticing unwritten data, and the risk of erroneous reading of the data increases. This failure mode can be appropriately detected if the resistance of the magnetoresistive effect element 100 is compared with the resistances of the first reference element 101 and the second reference element 102.
The magnetic recording array 201 of the second embodiment is excellent in integration as in the magnetic recording array 200 of the first embodiment.
In the magnetic recording array 201 according to the second embodiment, the presence or absence of a failure of the magnetoresistive element 100 can be evaluated in real time by comparing the resistances of the first reference element 101 and the second reference element 102 with the resistance of the magnetoresistive element 100.
Further, since the first reference element 101 and the second reference element 102 are in the same temperature environment as the magnetoresistive element 100, the variation of the reference point which becomes the threshold value of data recording due to the temperature change can be suppressed. Further, since the first reference element 101 and the second reference element 102 are applied with the same load as the magnetoresistive element 100, the variation of the reference point which becomes the threshold value of data recording due to deterioration can be suppressed.
(third embodiment)
FIG. 6 is a circuit diagram of a magnetic recording array 202 of a third embodiment. The magnetic recording array 202 of the third embodiment differs from the magnetic recording array 200 of the first embodiment in that the point at which the adjacent first wiring lines L1 are connected via the shorting transistor Tr 5. In the third embodiment, the same configurations as those of the first embodiment will not be described.
The short-circuit transistor Tr5 belongs to the peripheral area PA 1. The short-circuit transistor Tr5 does not affect the integration of the integration area IA.
The short-circuit transistor Tr5 connects the second ends of the adjacent first wirings L1 to each other. The second end is an end opposite to the end of the first wiring L1 connected to the first wiring control transistor Tr 3. The short-circuit transistor Tr5 is OFF (OFF) when data is written and ON (ON) when data is read. If the short-circuit transistor Tr5 is on, the adjacent first wiring L1 is short-circuited.
If the adjacent first wiring L1 is short-circuited, the sense current is shunted from the laminated body 10 toward both ends of the wiring 20. By determining the resistance value of the magnetoresistive element 100 based on the two divided read currents, data can be read with higher accuracy.
In addition, the magnetic recording array 202 of the third embodiment is excellent in integration as in the magnetic recording array 200 of the first embodiment.
(fourth embodiment)
Fig. 7 is a sectional view of a magnetized rotating element 110 of the fourth embodiment. Fig. 7 is a cross section of the magnetization rotating element 110 cut by an xz plane passing through the center of the y-direction width of the wiring 20. The magnetization rotating element 110 according to the fourth embodiment is different from the magnetoresistance effect element 100 according to the first embodiment in that it does not have the nonmagnetic layer 3 and the second ferromagnetic layer 2. The other structure is the same as that of the magnetoresistive element 100 according to the first embodiment, and the description thereof is omitted.
The magnetization rotating element 110 is an example of a spin element. The magnetization rotating element 110 evaluates, for example, light incident on the first ferromagnetic layer 1 and reflected by the first ferromagnetic layer 1. If the orientation direction of magnetization changes due to the magneto-optical kerr effect, the state of deflection of the reflected light changes. The magnetization rotating element 110 can be used as an optical element such as an image display device that utilizes a difference in the deflection state of light.
The magnetization rotating element 110 can also be used alone as an anisotropic magnetic sensor, an optical element utilizing the magnetic faraday effect, or the like.
The magnetization rotating element 110 according to the fourth embodiment can obtain the same effect as the magnetoresistance effect element 100 according to the first embodiment by removing only the nonmagnetic layer 3 and the second ferromagnetic layer 2. The magnetoresistive element 100 according to the second and third embodiments may be replaced with a magnetization rotating element 110.
(fifth embodiment)
Fig. 8 is a cross-sectional view of a magnetoresistance effect element 120 of the fifth embodiment. Fig. 8 is a cross section of the magnetoresistive element 120 cut by an xz plane passing through the center of the y-direction width of the wiring 40. The magnetoresistive element 120 is different from the magnetoresistive element 100 in that the laminated body 11 is composed of the nonmagnetic layer 5 and the first ferromagnetic layer 4 from the side close to the wiring 40. The same reference numerals are given to the same structures as those of the magnetoresistive element 100, and the description thereof is omitted.
The magnetoresistive element 120 includes a laminate 11, a wiring 40, and conductive portions 31 and 32. The laminated body 11 is composed of the nonmagnetic layer 5 and the first ferromagnetic layer 4 from the side close to the wiring 40. The magnetoresistance effect element 120 is an element whose resistance value changes due to the movement of the domain wall DW, and may be referred to as a domain wall moving element or a domain wall moving magnetoresistance effect element. The magnetoresistive element 120 is an example of a spin element.
The wiring 40 is a magnetic layer. The wiring 40 includes a ferromagnetic body. As the magnetic material constituting the wiring 40, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, an alloy containing these metals and at least one or more of B, C and N, or the like can be used. Specific examples thereof include Co-Fe and Co-Fe-B, Ni-Fe.
The wiring 40 is a layer capable of magnetically recording information by a change in internal magnetic state. The wiring 40 has a first magnetic region 41 and a second magnetic region 42 inside. The magnetization of first magnetic region 41 and the magnetization of second magnetic region 42 are oriented in opposite directions, for example. The boundary of the first and second magnetic regions 41 and 42 is a magnetic domain wall DW. The wire 40 can have a magnetic domain wall DW inside.
The magnetoresistance effect element 120 can record data in a plurality of values or continuously according to the position of the magnetic domain wall DW of the wire 40. When a read current is applied, data recorded on the wiring 40 is read as a change in resistance value of the magnetoresistive element 120.
The magnetic domain wall DW is moved by passing a write current in the x direction of the wire 40 or applying an external magnetic field. For example, if a write current (e.g., a current pulse) is applied to the + x direction of the wire 40, electrons flow in the-x direction opposite to the current, and thus the magnetic domain wall DW moves in the-x direction. When a current flows from the first magnetic region 41 toward the second magnetic region 42, the spin-polarized electrons in the second magnetic region 42 invert the magnetization of the first magnetic region 41. The magnetic domain wall DW moves in the-x direction due to the magnetization reversal of the first magnetic region 41.
The first ferromagnetic layer 4 and the nonmagnetic layer 5 are the same as the first ferromagnetic layer 1 and the nonmagnetic layer 3, respectively, of the first embodiment.
The magnetoresistance effect element 120 of the fifth embodiment can also obtain the same effects as the magnetoresistance effect element 100 of the first embodiment. The magnetoresistive element 100 according to the second and third embodiments may be replaced with the magnetoresistive element 120.
The magnetic recording arrays of the first to fifth embodiments can be applied to a neuromorphic device. Neuromorphic devices are elements that mimic the human brain through a neural network. Neuromorphic devices artificially mimic the relationship of neurons and synapses in the human brain.
The neuromorphic device has, for example, a chip (neurons in the brain) arranged in a layered manner and a transfer unit (synapses in the brain) connecting between them. The neuromorphic device learns through the transmission units (synapses) to increase the positive resolution rate of the problem. Learning to find the knowledge that will likely be used in the future from the information, weights the data entered in the neuromorphic device.
Each synapse mathematically performs a product-sum operation. The magnetic recording arrays according to the first to fifth embodiments can perform product-sum computation by arranging the magnetoresistive elements or magnetization rotating elements in an array. For example, if a current is caused to flow through the read path of the magnetoresistive element, the product of the input and output currents and the resistance of the magnetoresistive element is calculated. If a plurality of magnetoresistive elements are connected by a common wiring, the product operation is added by the common wiring, and the sum operation is performed. Therefore, the magnetic recording arrays of the first to third embodiments can be applied to a neuromorphic device as a product-sum calculator.
Description of the symbols
1. 4 first ferromagnetic layer
2 second ferromagnetic layer
3. 5 nonmagnetic layer
4 first ferromagnetic layer
10. 11 laminated body
20. 40 wiring
100 magnetoresistance effect element
100A first magnetoresistance element
100B first magnetoresistance effect element
101 first reference element
102 second reference element
200. 201, 202 magnetic recording array
A1 first region
A2 second region
A3 third region
DW magnetic domain wall
G1 first grid
G2 second grid
GL1 first gate line
GL2 second gate line
L1 first wiring
L2 second wiring
STr shared transistor
STr1 first common transistor
Second shared transistor of STr2
Third shared transistor of STr3
Tr3 first wiring control transistor
Tr4 second wiring control transistor
Tr5 shorts the transistors.