Pin distribution structure and high-speed chip

文档序号：1816364 发布日期：2021-11-09 浏览：12次中文

阅读说明：本技术 一种pin脚分布结构及高速芯片 (Pin distribution structure and high-speed chip ) 是由李永翠于 2021-06-29 设计创作，主要内容包括：本发明公开一种pin脚分布结构及高速芯片,相邻pin脚行各对应pin脚交错分布,同时设置两类差分信号pin脚对,其中一类差分信号pin脚对的两个差分信号pin脚在同一行,另一类差分信号pin脚对的两个差分信号pin脚分布在相邻的两行,且两类差分信号pin脚对交叉分布,使相邻的两个差分信号pin脚对呈一定角度分布,与传统并排平行排布对比,串扰得到明显提升,提升了链路的信号完整性,避免串扰带来的信号失效,同时合理利用pin脚分布空间,避免过涉及带来的成本浪费。本发明的结构简洁高效易实现,同时增加了系统设计可靠性。(The invention discloses a pin distribution structure and a high-speed chip, wherein adjacent pin rows respectively correspond to pins in a staggered distribution mode, two types of differential signal pin pairs are simultaneously arranged, two differential signal pins of one type of differential signal pin pair are in the same row, two differential signal pins of the other type of differential signal pin pair are distributed in two adjacent rows, and the two types of differential signal pin pairs are distributed in a crossed mode, so that the two adjacent differential signal pin pairs are distributed at a certain angle, compared with the traditional parallel arrangement, crosstalk is obviously improved, the signal integrity of a link is improved, signal failure caused by the crosstalk is avoided, meanwhile, the pin distribution space is reasonably utilized, and cost waste caused by the related relation is avoided. The invention has simple structure, high efficiency and easy realization, and simultaneously increases the reliability of system design.)

1. A pin distribution structure is characterized by comprising a plurality of rows of pins, wherein each pin in the upper row and each corresponding pin in the next adjacent row are in staggered distribution;

the pin pins comprise a grounding pin and a differential signal pin, wherein the differential signal pin comprises a positive differential signal pin and a negative differential signal pin, and one positive differential signal pin and one negative differential signal pin form a differential signal pin pair;

the differential signal pin pairs comprise a first type differential signal pin pair and a second type differential signal pin pair, wherein two differential signal pins of the first type differential signal pin pair are distributed in the same row, and two differential signal pins of the second type differential signal pin pair are distributed in two adjacent rows;

a plurality of first-type differential signal pin pairs and a plurality of second-type differential signal pin pairs are distributed on the structure, and the first-type differential signal pin pairs and the second-type differential signal pin pairs are arranged in a crossed mode.

2. The pin distribution structure of claim 1, wherein the first type of differential signal pin pairs are arranged at an angle of 45 degrees with respect to the adjacent second type of differential signal pin pairs.

3. The pin distribution structure according to claim 1 or 2, wherein at least one of the two differential signal pins of the second type of differential signal pin pair is located in a row adjacent to the first type of differential signal pin pair.

4. The pin distribution structure of claim 3, wherein there is no ground pin between two differential signal pins of the first type of differential signal pin.

5. The pin distribution structure of claim 4, wherein for two differential signal pins of the second type differential signal pin pair, the differential signal pin of the previous row and one of the next row and its nearest neighbor form the second type differential signal pin pair.

6. The pin distribution structure of claim 5, wherein the first row of pin pins are ground pin pins.

7. The pin distribution structure of claim 6, wherein the first pin at the left end of each of the remaining rows is a ground pin except the first row.

8. The pin distribution structure of claim 7, wherein the differential signal pins are divided into RX signal pins and TX signal pins;

the RX signal pin comprises a positive RX signal pin and a negative RX signal pin, namely an RX + signal pin and an RX-signal pin;

the TX signal pin comprises a positive TX signal pin and a negative TX signal pin, namely a TX + signal pin and a TX-signal pin;

the first RX signal pin at one end of the structure is separated from the first TX signal pin at the other end by at least one row.

9. The pin distribution structure of claim 8, wherein the structure comprises six rows of pins, each row comprising seven pins;

the first pin and the third pin from the left side of the second row are RX + signal pins, the second pin is RX-signal pin, and the rest pins of the row are grounding pins;

the fourth pin and the sixth pin from the left side of the third row are RX + signal pins, the fifth pin and the seventh pin are RX-signal pins, and the rest pins of the row are grounding pins;

the second pin from the left side of the fourth line is a TX + signal pin, the sixth pin is an RX-signal pin, and the rest pins of the line are grounding pins;

the second pin and the fourth pin from the left side of the fifth row are TX-signal pins, the third pin and the fifth pin are TX + signal pins, and the rest pins of the row are grounding pins;

the fourth pin and the sixth pin from the left side of the sixth row are TX-signal pins, the fifth pin is a TX + signal pin, and the rest pins of the row are grounding pins.

10. A high-speed chip, characterized in that the pin distribution structure of any of claims 1-9 is configured.

Technical Field

The invention relates to the field of pin distribution, in particular to a pin distribution structure and a high-speed chip.

Background

In the design of the Incloud server, particularly in a PCIE5.0 high-speed signal interconnection topological link, the board card density is increased along with the increase of the signal rate, the laminated plate thickness is increased, and how to achieve small volume and excellent performance in the design of a high-speed system link becomes the target pursued by designers.

For pin distribution (i.e., pin map) design of a high-speed chip, the existing design is generally distributed as shown in fig. 1, a TX signal pin and an RX distribution pin are in different columns and are separated by a ground pin (i.e., GND pin), but no isolation ground pin is arranged between the TX + signal pin and the TX-signal pin TX or between the RX + signal pin and the RX-signal pin, because in the distribution, the isolation ground pin is added between the TX + signal pin and the TX-signal pin TX or between the RX + signal pin and the RX-signal pin, which greatly increases the size and cost of the chip.

Disclosure of Invention

In order to solve the above problems, the present invention provides a pin distribution structure and a high-speed chip, which can reasonably utilize the pin distribution space and reduce crosstalk.

In a first aspect, the technical solution of the present invention includes a pin distribution structure, including a plurality of rows of pins, each pin in a previous row being in staggered distribution with each corresponding pin in an adjacent next row;

Further, the first type differential signal pin pair and the adjacent second type differential signal pin pair are distributed at an angle of 45 degrees.

Furthermore, at least one differential signal pin in the two differential signal pin pairs of the second type differential signal pin pair is located in a row where the adjacent first type differential signal pin pair is located.

Further, there is no ground pin between two differential signal pins of the first type of differential signal pin.

Further, for two differential signal pin feet of the second type differential signal pin foot pair, the differential signal pin foot of the upper row, the next row and one of the adjacent and nearest pin feet form the second type differential signal pin foot pair.

Furthermore, the first row of pin pins are all grounding pin pins.

Furthermore, except for the first row, the first pin pins at the left ends of the other rows are all grounding pin pins.

Furthermore, the differential signal pin is divided into an RX signal pin and a TX signal pin;

the RX signal pin comprises a positive RX signal pin and a negative RX signal pin, namely an RX + signal pin and an RX-signal pin;

the TX signal pin comprises a positive TX signal pin and a negative TX signal pin, namely a TX + signal pin and a TX-signal pin;

the first RX signal pin at one end of the structure is separated from the first TX signal pin at the other end by at least one row.

Further, the structure comprises six rows of pin legs, each row comprising seven pin legs;

the first pin and the third pin from the left side of the second row are RX + signal pins, the second pin is RX-signal pin, and the rest pins of the row are grounding pins;

the fourth pin and the sixth pin from the left side of the third row are RX + signal pins, the fifth pin and the seventh pin are RX-signal pins, and the rest pins of the row are grounding pins;

the second pin from the left side of the fourth line is a TX + signal pin, the sixth pin is an RX-signal pin, and the rest pins of the line are grounding pins;

the second pin and the fourth pin from the left side of the fifth row are TX-signal pins, the third pin and the fifth pin are TX + signal pins, and the rest pins of the row are grounding pins;

the fourth pin and the sixth pin from the left side of the sixth row are TX-signal pins, the fifth pin is a TX + signal pin, and the rest pins of the row are grounding pins.

In a second aspect, the technical solution of the present invention further includes a high-speed chip configured with any one of the pin distribution structures described above.

Compared with the prior art, the pin distribution structure and the high-speed chip provided by the invention have the following beneficial effects: adjacent pin foot row respectively corresponds pin foot crisscross distribution, set up two types of differential signal pin foot pairs simultaneously, two differential signal pin feet of one type of differential signal pin foot pair are in same line, two differential signal pin feet of another type differential signal pin foot pair distribute at two adjacent lines, and two types of differential signal pin foot are to cross distribution, make two adjacent differential signal pin foot pairs be certain angular distribution, with the tradition contrast of arranging in parallel side by side, it obviously promotes to crosstalk, the signal integrality of link has been promoted, the signal failure of avoiding crosstalk to bring, simultaneously rational utilization pin foot distribution space, avoid involving the cost waste who brings. The invention has simple structure, high efficiency and easy realization, and simultaneously increases the reliability of system design.

Drawings

For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional pin distribution architecture;

FIG. 2 is a schematic diagram of a pin distribution architecture provided by the present invention;

fig. 3 is a schematic diagram of a pin distribution structure according to an embodiment of the invention.

Detailed Description

The core of the invention is to provide a pin distribution structure and a high-speed chip, wherein adjacent pin rows respectively correspond to pins in staggered distribution, and two types of differential signal pin pairs are simultaneously arranged, wherein two differential signal pins of one type of differential signal pin pair are in the same row, two differential signal pins of the other type of differential signal pin pair are distributed in two adjacent rows, and the two types of differential signal pin pairs are distributed in a crossed manner, so that the two adjacent differential signal pin pairs are distributed at a certain angle, the pin distribution space is reasonably utilized, and crosstalk is reduced.

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Example one

Therefore, this embodiment provides a pin foot distribution structure, makes adjacent pin foot row crisscross distribution, and is certain angle between the adjacent differential signal pair, for the parallel distribution of tradition side by side, optimizes pin distribution space, reduces and disturbs.

Fig. 2 is a schematic diagram of a pin distribution structure provided in this embodiment, which includes multiple rows of pins, where each pin in an upper row and each corresponding pin in an adjacent lower row are in staggered distribution, and for example, a first pin in a second row is located between two pins before the first row.

The pin pins comprise a grounding pin and a differential signal pin, wherein the differential signal pin comprises a positive differential signal pin and a negative differential signal pin, and one positive differential signal pin and one negative differential signal pin form a differential signal pin pair.

In order to realize that the adjacent differential signal pin pairs are distributed at a certain angle, the differential signal pin pairs of the embodiment are provided with two types, namely a first type differential signal pin pair and a second type differential signal pin pair. The two differential signal pin pairs of the first type of differential signal pin pair are distributed in the same row, and the two differential signal pin pairs of the second type of differential signal pin pair are distributed in two adjacent rows.

In addition, a plurality of first-type differential signal pin pairs and a plurality of second-type differential signal pin pairs are distributed on the structure, and the first-type differential signal pin pairs and the second-type differential signal pin pairs are arranged in a crossed mode.

Because of the crisscross distribution of each pin foot that two adjacent lines of pin feet correspond, first type differential signal pin foot pair and second type differential signal pin foot pair are alternately arranged simultaneously, make adjacent differential signal pin foot pair no longer parallel arrangement side by side, but be certain angular distribution, through the emulation, for traditional parallel arrangement side by side, it obviously promotes to crosstalk, and can optimize pin foot distribution space.

The pin foot distribution structure that this embodiment provided, adjacent pin foot row respectively corresponds pin foot crisscross distribution, set up two types of differential signal pin foot pairs simultaneously, wherein two differential signal pin feet of one type differential signal pin foot pair are in same row, two differential signal pin feet of another type differential signal pin foot pair distribute at two adjacent lines, and two types of differential signal pin foot are to cross distribution, make two adjacent differential signal pin foot pairs be certain angular distribution, arrange the contrast with the tradition parallel side by side, it obviously promotes to crosstalk, the signal integrality of link has been promoted, the signal inefficacy of avoiding crosstalk to bring, simultaneously rational utilization pin foot distribution space, avoid involving the cost waste who brings. The invention has simple structure, high efficiency and easy realization, and simultaneously increases the reliability of system design.

Example two

This embodiment provides a pin foot distribution structure, makes adjacent pin foot row crisscross distribution, and is certain angle between the adjacent differential signal pair, for the parallel distribution side by side of tradition, optimizes pin distribution space, reduces and crosstalk.

This embodiment makes and is 45 degrees angular distributions between first type differential signal pin foot pair and the adjacent second type differential signal pin foot pair, through the emulation, can avoid crosstalking by great extent. In fig. 2, the two pins connected by the dotted line are a differential signal pin pair, the horizontal dotted line is a first differential signal pin pair, the oblique dotted line is a second differential signal pin pair, and the 45-degree angle of the embodiment means that an angle of 45 degrees is formed between the horizontal dotted line and the oblique dotted line.

In order to optimize the pin distribution space, at least one differential signal pin in the two differential signal pins of the second-type differential signal pin pair of this embodiment is located in a row where the adjacent first-type differential signal pin pair is located. For the second type differential signal pin having the first type differential signal pin on both sides, the two differential signal pins are respectively located in the row where the corresponding first type differential signal pin is located, such as the first second type differential signal pin on the upper side in fig. 2. For the second type differential signal pins with the first type differential signal pins on one side, one of the differential signal pins is located in the row corresponding to the first type differential signal pin, as shown in fig. 2, the second type differential signal pin on the upper side and the first differential signal pin on the lower side.

In the structure of this embodiment, there is no ground pin between two differential signal pins of the first-type differential signal pin pair, and in addition, for two differential signal pins of the second-type differential signal pin pair, the differential signal pin of the previous row, the next row and one of the adjacent and closest pins form the second-type differential signal pin pair. It should be noted that, the nearest adjacent pin is selected from the second type differential signal pin pair, and it is ensured that the first type differential signal pin pair and the second type differential signal pin pair are distributed at an angle of 45 degrees, at this time, the two adjacent rows of pins are staggered, specifically, the pin of a certain row is located in the middle of two corresponding pins in another row, for example, the first pin of the second row is located in the middle of the first two pins in the first row in fig. 2, and the rest is analogized. It should be noted that the spacing between the pins in each row is uniform.

The structure of this embodiment makes first line pin foot be ground connection pin foot, and except first line, the first pin foot of all other lines left end is ground connection pin foot simultaneously, further reduces the crosstalk influence.

The differential signal pin is divided into an RX signal pin and a TX signal pin. The RX signal pins comprise a positive RX signal pin and a negative RX signal pin, namely an RX + signal pin and an RX-signal pin; the TX signal pin includes a positive TX signal pin and a negative TX signal pin, i.e., a TX + signal pin and a TX-signal pin.

In this embodiment, the first RX signal pin at one end of the structure is separated from the first TX signal pin at the end by at least one line, that is, the RX signal pin and the TX signal pin are separated.

An embodiment is provided below, and fig. 3 is a schematic diagram illustrating a pin distribution structure according to the embodiment.

The pin distribution structure of this embodiment includes six rows of pins, each row including seven pins.

The first row is a ground pin.

The first pin and the third pin from the left side of the second row are RX + signal pins, the second pin is RX-signal pin, and the rest pins of the row are grounding pins.

The fourth pin and the sixth pin from the left side of the third row are RX + signal pins, the fifth pin and the seventh pin are RX-signal pins, and the rest pins of the row are grounding pins.

And the second pin from the left side of the fourth line is a TX + signal pin, the sixth pin is an RX-signal pin, and the rest pins of the line are grounding pins.

The second pin and the fourth pin from the left side of the fifth row are TX-signal pins, the third pin and the fifth pin are TX + signal pins, and the rest pins of the row are grounding pins.

The fourth pin and the sixth pin from the left side of the sixth row are TX-signal pins, the fifth pin is a TX + signal pin, and the rest pins of the row are grounding pins.

Through simulation, the pin distribution structure of the embodiment has obviously better crosstalk than the traditional parallel distribution.

EXAMPLE III

The present embodiment provides a high-speed chip, which is configured with the pin distribution structure in the first embodiment or the second embodiment.

The high-speed chip of this embodiment is implemented based on the foregoing pin distribution structure, and therefore, the specific implementation in the apparatus can be seen from the foregoing embodiment section of the pin distribution structure, and therefore, the specific implementation thereof can refer to the description of the corresponding respective section embodiments, and is not described herein again.

In addition, since the high-speed chip of this embodiment is implemented based on the pin distribution structure, the function of the high-speed chip corresponds to that of the method described above, and is not described herein again.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.

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Pin distribution structure and high-speed chip

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