阅读说明：本技术 一种自动修正mos器件漏电通路的方法 (Method for automatically correcting leakage path of MOS device ) 是由 王莹雪 方益 于 2021-08-31 设计创作，主要内容包括：本发明提供一种自动修正MOS器件漏电通路的方法包括：读入版图文件,利用预设的漏电通路修正模块自动修正；在所述漏电通路修正模块中定义有存在漏电通路的MOS器件的修正方式：在M0切断层添加M0C,添加缺少的V0通孔。有效解决由于产生漏电通路而影响MOS器件电性测试的问题,利于提高器件电学特性测试的真实性；步骤简洁,不依赖于人工操作与经验,节约人力和工时,降低工艺研发成本,解决了手动实现修正费时且失误风险高的问题,自动修正结果的可靠性更好,利于制造水平和产品整体质量的提高。(The invention provides a method for automatically correcting a leakage path of an MOS device, which comprises the following steps: reading in a layout file, and automatically correcting by using a preset leakage path correction module; the leakage path correction module defines a correction mode of a MOS device with a leakage path: M0C was added at M0 cut layer, and the missing V0 via was added. The problem that the electrical property test of the MOS device is influenced due to the generation of a leakage path is effectively solved, and the authenticity of the electrical property test of the device is favorably improved; the method has the advantages of simple steps, no dependence on manual operation and experience, labor and time saving, process development cost reduction, time-consuming manual correction and high error risk, better reliability of automatic correction results, and contribution to improvement of manufacturing level and overall product quality.)

1. A method for automatically correcting a leakage path of a Metal Oxide Semiconductor (MOS) device is characterized in that: the method comprises the following steps: reading in a layout file, and determining an MOS device of a leakage path to be corrected as a target device; correcting the leakage path of the target device by using a preset leakage path correction module;

wherein, a correction mode of the MOS device with the leakage path is defined in the leakage path correction module; the correction mode comprises the following steps:

s1, adding M0C to an M0 cut-off layer, and cutting off an M0 connecting line to disconnect the source end and/or the drain end of the target device from the source end and/or the drain end of other MOS devices;

s2, judging whether a source end, a drain end and a gate end of the target device can be connected to an M1 connecting line through an existing V0 through hole respectively; if not, adding the missing V0 through hole;

the M0 connecting line is arranged on the M0 layer and is used for connecting an active region or a grid; the M1 connecting wire is arranged on the M1 layer and is connected with the M0 connecting wire through the V0 through hole.

2. The method of claim 1, wherein the method further comprises: the correction mode further comprises: after the step S2, deleting redundant V0 vias; the redundant V0 via is the V0 via that is no longer used to connect the target device after the M0C is added.

3. The method of claim 1, wherein the method further comprises: the leakage path correction for the target device is realized by adding a first identification layer in the layout file, wherein first information for positioning the target device is added in the first identification layer;

the first information includes: and representing coordinate information and shape information of an M0 connecting line connecting the source terminal and/or the drain terminal of the target device with the source terminal and/or the drain terminal of other MOS devices.

4. The method of claim 3, wherein the method further comprises: and after the leakage path of the target device is corrected, deleting the first information of the target device in the first identification layer.

5. The method of claim 1, wherein the method further comprises: after the leakage path of the target device is corrected, adding a second identification layer in the corrected layout file of the target device, wherein the second identification layer is used for adding second information of the target device after the correction is completed;

the second information includes: and representing the corrected coordinate information and shape information of the target device.

6. The method of claim 1, wherein the method further comprises: the target devices are multiple;

after the leakage path of the target device is corrected, adding respective exclusive identification layers to the layout file for each corrected target device;

the exclusive identification layer comprises third information, and the third information represents coordinate information and shape information of the target device.

7. The method for automatically correcting the leakage path of the MOS device according to any one of claims 1 to 6, wherein: after correcting the leakage path of the target device, verifying the corrected layout file of the target device, and if the corrected layout file conforms to a preset layout process design rule, indicating that the correction is finished; and if the layout is not in accordance with the preset layout process design rule, returning to correct again.

8. The method of claim 1, wherein the method further comprises: the method for determining the MOS device of the leakage path to be corrected as the target device comprises the following steps:

acquiring MOS device information in the layout file;

screening whether a leakage path exists in the MOS device by using a preset leakage path screening module; a judgment condition whether the MOS device has a leakage path or not is defined in the leakage path screening module;

and thirdly, taking the MOS device with the leakage path obtained by screening as the target device.

9. The method of claim 8, wherein the method further comprises: the judgment condition includes: and if the source end and/or the drain end of one MOS device is connected with the source ends and/or the drain ends of other MOS devices, judging that the MOS device is the MOS device with the leakage path.

10. The method of claim 8, wherein the method further comprises: when the MOS device to be screened in the layout file needs to be specified, the second step further includes:

determining the MOS device to be screened in the layout file as a screening target device, and positioning the screening target device;

adding a screening identification layer in the layout file, and adding fourth information of the screening target device to the screening identification layer; the fourth information includes: characterizing coordinate information and shape information of the screening target device;

and in the second step, only whether the screening target device in the screening identification layer has the leakage path is judged by using a leakage path screening module.

Technical Field

The invention belongs to the technical field of semiconductor design and manufacture, and particularly relates to a method for automatically correcting a leakage path of an MOS (metal oxide semiconductor) device.

Background

Whether a chip can work normally or not is of great concern in the semiconductor industry, and from the viewpoint of circuit composition, the chip is composed of devices, and the electrical characteristics of the devices are critical to the whole chip. The electrical characteristics of the device can be preliminarily acquired through Simulation, and Simulation (Simulation) data is obtained through Simulation; after chip production, the devices were measured and test (Silicon) data was obtained. The simulation data is compared with the test data (S2S). And through comparison, the accuracy of the simulation data is verified and the correctness of the test data is assisted to be judged. If the simulation data can accurately reflect the real electrical characteristics of the device, the simulation data can be used for designing a novel device, improving an old device, replacing a silicon wafer experiment with higher cost, reducing the cost, shortening the development period and improving the yield.

For the MOS device, a specific target device is selected according to requirements in practical application, the specific target device is connected to a testable circuit for testing, and simulation data and test data of the specific target device are contrastingly analyzed. Among the common problems are: in a test structure, only the gate of a specific target device is connected with a signal, and the other devices are floating gates, and because the voltage on the floating gate is not fixed, the possibility of opening the floating gate to a certain degree exists, leakage path of the S/D end (source/drain end) of the target device is increased, and the corresponding Ioff current value is larger, so that the analysis of the real electrical characteristics of the device is influenced. However, currently, for a MOS device, the existence of such leakage path is not generally considered, that is, the influence of such leakage path on the accurate measurement of the electrical characteristics of the MOS device is not particularly noticed. Even if the problem caused by the leakage path is concerned, the manual correction can be carried out only by depending on the subjective experience, the overall production efficiency is influenced by the low correction efficiency, and the correction result is not ideal and unstable.

Therefore, it is necessary to research a method for automatically correcting the leak path of the MOS device so as to avoid the adverse effect of the leak path on the accuracy of measuring the electrical characteristics of the MOS device, thereby further promoting the deep development and wide application of the semiconductor design and manufacturing technology.

Disclosure of Invention

The invention provides a method for automatically correcting the leakage path of the MOS device for a layout file, which aims to solve all or part of problems in the prior art. The solution of the invention is: the method for automatically correcting the leakage path of the MOS device comprises the following steps: reading in a layout file, and determining an MOS device of a leakage path to be corrected as a target device; correcting the leakage path of the target device by using a preset leakage path correction module; wherein, a correction mode of the MOS device with the leakage path is defined in the leakage path correction module; the correction mode comprises the following steps: s1, adding M0C to an M0 cut-off layer, wherein the M0 connecting line is cut off to disconnect the source end and/or the drain end of the target device from the source end and/or the drain end of other MOS devices (namely floating gates); s2, judging whether a source end, a drain end and a gate end of the target device can be connected to an M1 connecting line through an existing V0 through hole respectively; if not, adding the missing V0 through hole; the M0 connecting line is arranged on the M0 layer and is used for connecting an active region or a grid; the M1 connecting wire is arranged on the M1 layer and is connected with the M0 connecting wire through the V0 through hole.

The correction mode further comprises: after the step S2, deleting redundant V0 vias; the redundant V0 via is the V0 via that is no longer used to connect the target device after the M0C is added. That is, after the addition of M0C to the target device and the addition of the missing V0 via, as judged, the redundant V0 via is deleted.

The leakage path correction for the target device is realized by adding a first identification layer in the layout file, wherein first information for positioning the target device is added in the first identification layer; the first information includes: coordinate information and shape information of an M0 connection line characterizing that the source terminal and/or the drain terminal of the target device is connected with the source terminal and/or the drain terminal of other MOS devices (floating gate).

And after the leakage path of the target device is corrected, deleting the first information of the target device in the first identification layer.

After the leakage path of the target device is corrected, adding a second identification layer in the corrected layout file of the target device, wherein the second identification layer is used for adding second information of the target device after the correction is completed; the second information includes: and representing the corrected coordinate information and shape information of the target device.

The target devices are multiple; after the leakage path of the target device is corrected, adding respective exclusive identification layers to the layout file for each corrected target device; the exclusive identification layer comprises third information, and the third information represents coordinate information and shape information of the target device. The exclusive identification layer can be combined with other identification layers except the exclusive identification layer to analyze the electric leakage path correction condition of the target device.

After correcting the leakage path of the target device, verifying the corrected layout file of the target device, and if the corrected layout file meets a preset layout process design rule (such as DRC verification), indicating that the correction is finished; and if the layout is not in accordance with the preset layout process design rule, returning to correct again.

The method for determining the MOS device of the leakage path to be corrected as the target device comprises the following steps: acquiring MOS device information in the layout file; screening whether a leakage path (leakage path) exists in the MOS device by using a preset leakage path screening module; a judgment condition whether the MOS device has a leakage path or not is defined in the leakage path screening module; and thirdly, taking the MOS device with the leakage path obtained by screening as the target device.

The judgment condition includes: and if the source end and/or the drain end of one MOS device is connected with the source ends and/or the drain ends of other MOS devices, judging that the MOS device is the MOS device with the leakage path. Specifically, the method comprises the following steps: if the source end and the drain end of a certain MOS device are connected with the source ends and the drain ends of other MOS devices, judging that the MOS device is the MOS device with a leakage path; and if the source end or the drain end of a certain MOS device is connected with the source ends or the drain ends of other MOS devices, judging that the MOS device is the MOS device with the leakage path.

When the MOS device to be screened in the layout file needs to be specified, the second step further includes: determining the MOS device to be screened in the layout file as a screening target device, and positioning the screening target device; adding a screening identification layer in the layout file, and adding fourth information of the screening target device to the screening identification layer; the fourth information includes: characterizing coordinate information and shape information of the screening target device; and in the second step, only whether the screening target device in the screening identification layer has the leakage path is judged by using a leakage path screening module.

Compared with the prior art, the invention has the main beneficial effects that:

1) according to the method for automatically correcting the leakage path of the MOS device, the preset leakage path correction module is utilized, so that the automatic correction of the leakage path (leakage path) of the MOS device can be realized, the problem that the electrical property test of the MOS device is influenced due to the generation of the leakage path (leakage path) is effectively solved, and the authenticity of the electrical property test of the device is improved; 2) after the layout file is read in, the correction process is automatically executed by utilizing the predefined correction mode in the leakage path correction module, the steps are simple, manual operation and subjective experience are not relied on, the manpower and time are greatly reduced, the efficiency is improved, the process research and development cost is reduced, the problems of time consumption and high error risk of manual correction are solved, and particularly when the number of devices is large, the advantages are obvious; 3) by adding the respective exclusive identification layer to the layout file for each corrected target device, layer operation can be performed on the identification layers representing the leakage path and the like, the leakage path condition of each corrected target device is obtained, subsequent data analysis of S2S is facilitated, and the manufacturing level and quality of the chip are improved effectively.

Drawings

Fig. 1 is a schematic diagram of a method for automatically correcting a leakage path of a MOS device according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a modification method according to a first embodiment of the invention.

Fig. 3 is a schematic diagram of a layout file before correction according to a first embodiment of the present invention.

Fig. 4 is a schematic diagram of a layout file after modification according to the first embodiment of the present invention.

Fig. 5 is a schematic diagram of a leakage path screening process according to a second embodiment of the present invention.

Fig. 6 is a schematic diagram of a layout file before correction according to a second embodiment of the present invention.

Detailed Description

The technical solutions in the specific embodiments of the present invention will be clearly and completely described below, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be noted that the flow charts and block diagrams in the figures illustrate the operational procedures which may be implemented by the methods according to the embodiments of the present invention. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the alternative, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and manual acts.

Example one

As shown in fig. 1, the present embodiment provides a method for automatically correcting a leakage path of a MOS device, including: reading in a layout file, and determining an MOS device of a leakage path to be corrected as a target device; correcting a leakage path of a target device by using a preset leakage path correction module; in the leakage path correction module, a correction method of a MOS device having a leakage path is defined. The modification of this embodiment is as shown in fig. 2, step s1, adding M0C to the M0 disconnection layer, so as to disconnect the source and/or drain of the target device from the source and/or drain of another MOS device (i.e., floating gate), for disconnecting the M0 connection line; s2, judging whether a source end, a drain end and a gate end of the target device can be connected to an M1 connecting line through an existing V0 through hole respectively; if not, missing V0 vias are added to ensure that the source, drain and gate terminals of the target device can be connected to the M1 connection lines through the V0 vias, respectively. In the case of the example shown in fig. 3 and 4, it is judged that one V0 via is missing and the V0 via is added, but in some embodiments, the necessary V0 via is not missing after correction and is not required to be added, and the specific case is not limited here.

Referring to fig. 3 and 4, the M0 connection line of the present embodiment is at the M0 layer and is used for connecting the active region AA or the gate of the MOS device. The gate illustrated in the figure is on polysilicon POLY. The M1 connection line is on the M1 layer and is connected with the M0 connection line through a V0 through hole. In this embodiment, exemplary M0 includes M0A and M0P, M0A for connecting the source region (i.e., source or drain) and M0P for connecting the gate. The V0 via is connected to the gate through M0P.

As shown in fig. 3, in this embodiment, before a leakage path of a target device is corrected, a first identification layer is added to a read-in layout file, and first information for locating the target device is added to the first identification layer; the first information includes: coordinate information and shape information of an M0 connection line representing that the source terminal and/or the drain terminal of the target device is connected with the source terminal and/or the drain terminal of other MOS devices (floating gate). Exemplary shape information refers to the length and width of the M0 connection line.

As shown in fig. 4, in the present embodiment, after the leakage path of the target device is corrected, the first information of the target device in the first identification layer is deleted. In some embodiments, the first information is not deleted after the correction, and is not limited.

The modification defined in this embodiment further includes: after step S2 is completed, the redundant V0 via is deleted; the redundant V0 via refers to the V0 via that is no longer used to connect to the target device after the M0C is added. Comparing fig. 3 and 4, it can be seen that one redundant V0 via is eliminated.

In this embodiment, after the leakage path of the target device is corrected, the corrected layout file of the target device is verified, for example, DRC verification is performed, and if the corrected layout file conforms to a preset layout process design rule, the correction is completed; and if the layout process does not meet the preset layout process design rule, returning to the step of reusing the leakage path correction module to execute the step S1 to the step S2 for correction. Until the verification result meets the preset layout process design rule.

As shown in fig. 4, in this embodiment, after the leakage path of the target device is corrected, a second identification layer is further added to the layout file of the corrected target device, so as to add second information of the target device after the correction is completed. The second information includes: and representing the coordinate information and the shape information of the corrected target device. Exemplary modified target device shape information is the length and width of the modified device.

In one example of this embodiment, there are a plurality of target devices, and after the target devices are corrected, a respective dedicated identification layer (not shown) is added to the read layout file for each target device. The exclusive identification layer comprises third information, and the coordinate information and the shape information of the target device are represented by the third information. The shape information is the length and width of the target device. By using the dedicated identification layer and the identification layer (such as the first identification layer) representing the leakage path and the like to perform layer operation, the leakage path condition of each device can be obtained, which is convenient for subsequent data analysis of S2S.

Example two

In the embodiment, an example is developed for determining that the MOS device of the leakage path to be corrected is the target device after the layout file is read in, as shown in fig. 5, in the step one, the MOS device information in the read layout file is obtained; screening whether a leakage path exists in the MOS device by using a preset leakage path screening module; and step three, taking the MOS device with the leakage path obtained by screening as a target device.

And a preset leakage path screening module is defined with a judgment condition whether the MOS device has a leakage path or not. The determination conditions defined in this embodiment include: if the source end and the drain end of a certain MOS device are connected with the source ends and the drain ends of other MOS devices, judging that the MOS device is the MOS device with a leakage path; if the source end or the drain end of a certain MOS device is connected with the source ends or the drain ends of other MOS devices, the MOS device is judged to be the MOS device with the leakage path.

In this embodiment, when the MOS device to be screened in the read-in layout file needs to be specified, the second step further includes determining that the MOS device to be screened in the read-in layout file is the screening target device, and positioning the screening target device. As shown in fig. 6, a screening identification layer is added to the read layout file, and fourth information of the screening target device is added to the screening identification layer; the fourth information includes: coordinate information and shape information characterizing the screening target device. The shape information in the fourth information is the length and width of the screening target device. In the second step of this implementation, the leakage path screening module is used to determine whether the leakage path exists only in the screening target device in the screening identification layer. In some other specific implementation cases, the screening identification layer may not be added, and the judgment in the step two is to all the MOS devices that need to be screened in the read-in layout file, and is not limited.

In this embodiment, after the layout file is read in, the leakage path screening module determines that the MOS device of the leakage path to be corrected is the target device, and then the leakage path correction module is used to perform automatic correction. The invention does not limit the screening mode of the target device, the screening is carried out by utilizing the preset leakage path screening module and is not a unique way, the target device of the leakage path to be corrected can be screened manually, and then the automatic correction is carried out by utilizing the leakage path correcting module, and the invention is not limited.

For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof.

It is further noted that, herein, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The present invention has been described in detail, and the structure and operation principle of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method and core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.