阅读说明：本技术 半导体集成电路及半导体存储装置 (Semiconductor integrated circuit and semiconductor memory device ) 是由 清水优 井上谕 藤沢公 高田由美 于 2021-01-20 设计创作，主要内容包括：本发明的一实施方式提供一种能够将数据信号从输入电路恰当地传送到后段电路的半导体集成电路及半导体存储装置。根据一实施方式,提供一种具有输入电路的半导体集成电路。输入电路具有第1放大器及第2放大器。第2放大器电连接于第1放大器。第2放大器具有第1晶体管、第2晶体管、第3晶体管、第4晶体管及时间常数附加电路。第1晶体管的栅极电连接于第1放大器的第1节点。第2晶体管的栅极电连接于第1放大器的第2节点。第3晶体管配置在第1晶体管的漏极侧。第4晶体管配置在第2晶体管的漏极侧。时间常数附加电路电连接于第3晶体管的栅极与第3晶体管的漏极及第4晶体管的栅极之间。(One embodiment of the present invention provides a semiconductor integrated circuit and a semiconductor memory device which can appropriately transmit a data signal from an input circuit to a subsequent circuit. According to one embodiment, a semiconductor integrated circuit having an input circuit is provided. The input circuit has a 1 st amplifier and a 2 nd amplifier. The 2 nd amplifier is electrically connected to the 1 st amplifier. The 2 nd amplifier has a 1 st transistor, a 2 nd transistor, a 3 rd transistor, a 4 th transistor, and a time constant addition circuit. The gate of the 1 st transistor is electrically connected to the 1 st node of the 1 st amplifier. The gate of the 2 nd transistor is electrically connected to the 2 nd node of the 1 st amplifier. The 3 rd transistor is disposed on the drain side of the 1 st transistor. The 4 th transistor is disposed on the drain side of the 2 nd transistor. The time constant additional circuit is electrically connected between the gate of the 3 rd transistor and the drain of the 3 rd transistor and the gate of the 4 th transistor.)

1. A kind of semiconductor integrated circuit is disclosed,

the input circuit includes a 1 st amplifier and a 2 nd amplifier electrically connected to the 1 st amplifier, and

the 2 nd amplifier

Comprising:

a 1 st transistor having a gate electrically connected to a 1 st node of the 1 st amplifier;

a 2 nd transistor having a gate electrically connected to a 2 nd node of the 1 st amplifier;

a 3 rd transistor disposed on a drain side of the 1 st transistor;

a 4 th transistor disposed on a drain side of the 2 nd transistor; and

and a time constant additional circuit electrically connected between the gate of the 3 rd transistor and the drain of the 3 rd transistor and the gate of the 4 th transistor.

2. The semiconductor integrated circuit according to claim 1, wherein

The time constant additional circuit includes a resistance element having one end electrically connected to the gate of the 3 rd transistor and the other end electrically connected to the drain of the 3 rd transistor and the gate of the 4 th transistor.

3. The semiconductor integrated circuit according to claim 2, wherein

The time constant additional circuit further includes a capacitor element, and one end of the capacitor element is electrically connected to the gate of the 3 rd transistor.

4. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein

The 3 rd transistor and the 4 th transistor constitute a current mirror circuit via the time constant adding circuit.

5. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein

The 1 st amplifier

Comprising:

a 5 th transistor having a drain electrically connected to the 1 st node and a gate for receiving a reference signal; and

and a 6 th transistor having a drain electrically connected to the 2 nd node and a gate for receiving a data signal.

6. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein

The 1 st amplifier

Comprising:

a 5 th transistor having a drain electrically connected to the 1 st node and a gate for receiving the 1 st data signal; and

and a 6 th transistor having a drain electrically connected to the 2 nd node and a gate for receiving the 2 nd data signal.

7. A semiconductor integrated circuit according to any one of claims 1 to 3, which

And further includes an inverter electrically connected to the 2 nd amplifier.

8. A semiconductor memory device includes:

memory cell array, and

the semiconductor integrated circuit according to any one of claims 1 to 7 arranged in the periphery of the memory cell array.

Technical Field

The present embodiment relates to a semiconductor integrated circuit and a semiconductor memory device.

Background

In a semiconductor integrated circuit including an input circuit, a data signal may be received by the input circuit, and the received data signal may be transmitted from the input circuit to a subsequent circuit for a predetermined operation. In this case, it is desirable to appropriately transmit the data signal from the input circuit to the subsequent circuit.

Disclosure of Invention

One embodiment provides a semiconductor integrated circuit and a semiconductor memory device capable of appropriately transmitting a data signal from an input circuit to a subsequent circuit.

According to one embodiment, a semiconductor integrated circuit having an input circuit is provided. The input circuit has a 1 st amplifier and a 2 nd amplifier. The 2 nd amplifier is electrically connected to the 1 st amplifier. The 2 nd amplifier has a 1 st transistor, a 2 nd transistor, a 3 rd transistor, a 4 th transistor, and a time constant addition circuit. The gate of the 1 st transistor is electrically connected to the 1 st node of the 1 st amplifier. The gate of the 2 nd transistor is electrically connected to the 2 nd node of the 1 st amplifier. The 3 rd transistor is disposed on the drain side of the 1 st transistor. The 4 th transistor is disposed on the drain side of the 2 nd transistor. The time constant additional circuit is electrically connected between the gate of the 3 rd transistor and the drain of the 3 rd transistor and the gate of the 4 th transistor.

Drawings

Fig. 1 is a diagram showing a configuration of a memory system including a semiconductor memory device including a semiconductor integrated circuit according to an embodiment.

Fig. 2 is a diagram showing a configuration of a semiconductor memory device including the semiconductor integrated circuit according to the embodiment.

Fig. 3 is a diagram showing a configuration of an input/output circuit according to the embodiment.

Fig. 4 is a diagram showing the configuration of an input circuit and a data latch in the embodiment.

Fig. 5 is a diagram showing a configuration of an input circuit in the embodiment.

Fig. 6(a) to (c) are waveform diagrams showing operations of the input circuit in the embodiment.

Fig. 7(a) to (d) are diagrams showing a part of an input circuit and a configuration of an equivalent circuit thereof in the embodiment.

Fig. 8 is a diagram showing frequency characteristics of an input circuit in the embodiment.

Fig. 9(a) to (d) are waveform diagrams showing operations of the input circuit in the embodiment.

Fig. 10 is a diagram showing a configuration of an input circuit in variation 1 of the embodiment.

Fig. 11 is a diagram showing a configuration of an input circuit in variation 2 of the embodiment.

Fig. 12 is a diagram showing a configuration of an input circuit in variation 3 of the embodiment.

Detailed Description

Hereinafter, a semiconductor integrated circuit according to an embodiment will be described in detail with reference to the drawings. The present invention is not limited to the embodiment.

(embodiment mode)

The semiconductor integrated circuit of the embodiment has an input circuit. In a semiconductor integrated circuit, a data signal is received by an input circuit, and the received data signal is latched in clock synchronization for a predetermined operation. For example, a semiconductor integrated circuit can be used as a peripheral circuit in the semiconductor memory device 120 having a memory cell array. In addition, the semiconductor memory device 120 may be applied to the memory system 100 shown in fig. 1. Fig. 1 is a diagram showing a configuration of a memory system 100 including a semiconductor memory device 120, the semiconductor memory device 120 having a semiconductor integrated circuit.

The storage system 100 is communicably connected to an external host (not shown), for example, and can function as an external storage device for the host.

As shown in fig. 1, the memory system 100 has a controller 110 and a semiconductor memory device 120. The controller 110 receives a command from a host and controls the semiconductor memory apparatus 120 based on the received command. Specifically, the controller 110 writes data instructed to be written by the host into the semiconductor storage device 120, and reads data instructed to be read by the host from the semiconductor storage device 120 and transmits the data to the host. The controller 110 is connected to the semiconductor memory device 120 via a memory bus. The semiconductor memory device 120 includes a memory cell array in which a plurality of memory cells are arranged, and is, for example, a nonvolatile memory that stores data in a nonvolatile manner.

The memory bus lines are for various signals/CE, CLE, ALE,/WE, RE,/WP,/RB, DQS,/DQS, and DQ < 7 according to the memory interface: 0 >. The transmission and reception are performed through the respective signal lines. signal/CE is a signal for activating the semiconductor memory apparatus 120. The signal CLE is a signal DQ < 7 which notifies the semiconductor memory apparatus 120 that the signal flows to the semiconductor memory apparatus 120 while the signal CLE is at the "H (High))" level: 0 > is an instruction. The signal ALE is a signal DQ < 7 which notifies the semiconductor memory apparatus 120 that flows to the semiconductor memory apparatus 120 while the signal ALE is at the "H" level: 0 > is an address. The signal/WE is a signal DQ < 7 indicating that a signal to be flowed to the semiconductor memory apparatus 120 during the period in which the signal/WE is "L (Low))" level: 0 > is retrieved into the semiconductor memory device 120. Signals RE and/RE are complementary signals indicating that semiconductor memory device 120 outputs signals DQ < 7: 0 >. The signal/WP is a signal indicating that the semiconductor memory device 120 inhibits data writing and erasing. The signal RB indicates whether the semiconductor memory device 120 is in a ready state (a state of receiving an external command) or a busy state (a state of not receiving an external command). The DQS and/DQS signals are complementary signals and are used as strobe signals to control the signal DQ < 7: 0 > the operating time of the semiconductor memory device 120 concerned. Signal DQ < 7: 0 > for example, an 8-bit data signal. Data signal DQ < 7: 0 > is an entity of data transmitted and received between the semiconductor memory device 120 and the controller 110, and includes a command CMD, an address ADD, and data DAT. The data DAT includes write data, and read data.

The controller 110 includes a processor (CPU) 111, a Random Access Memory (RAM) 112, an ECC (Error Check and Correction) circuit 113, a Memory interface circuit 114, a buffer Memory 115, and a host interface circuit 116.

The processor 111 controls the overall operation of the controller 110. The processor 111 issues a read command based on a memory interface to the semiconductor memory device 120, for example, in response to a read command of data received from a host. The same applies to the case of writing and erasing. The processor 111 has a function of performing various operations on read data from the semiconductor memory device 120.

The built-in memory 112 is a semiconductor memory such as a DRAM (Dynamic RAM) and is used as a work area of the processor 111. The built-in memory 112 stores firmware for managing the semiconductor memory device 120, various management tables, and the like.

The ECC circuit 113 performs error detection and error correction processing. More specifically, when data writing is performed, an ECC code is generated for each certain number of data groups based on data received from the host. When data is read, ECC decoding is performed based on the ECC code, and the presence or absence of an error is detected. Also, when an error is detected, its bit position is specified, and the error is corrected.

The memory interface circuit 114 is connected to the semiconductor memory device 120 via a memory bus, and is responsible for communication with the semiconductor memory device 120. The memory interface circuit 114 transmits a command CMD, an address ADD, and write data to the semiconductor memory device 120 in accordance with an instruction from the processor 111. In addition, the memory interface circuit 114 receives read data from the semiconductor memory device 120.

The buffer memory 115 temporarily stores data and the like received by the controller 110 from the semiconductor memory device 120 and the host. The buffer memory 115 is also used as a storage area for temporarily storing read data from the semiconductor memory device 120, a calculation result for the read data, and the like, for example.

The host interface circuit 116 is connected to the host and is responsible for communication with the host. Host interface circuitry 116, for example, transfers commands and data received from the host into processor 111 and buffer memory 115, respectively.

The semiconductor memory device 120 may be configured as shown in fig. 2. Fig. 2 is a diagram showing the structure of the semiconductor memory device 120.

The semiconductor memory device 120 includes a memory cell array 121, a semiconductor integrated circuit 132, a group of input/output pins 130, and a group of logic control pins 131. The semiconductor integrated circuit 132 is disposed around the memory cell array 121. The semiconductor integrated circuit 132 is electrically connected between the memory cell array 121 and the input/output pin group 130 and the logic control pin group 131.

The semiconductor integrated circuit 132 has an input-output circuit 122, a logic control circuit 123, a register 124, a sequencer 125, a voltage generation circuit 126, a driver component 127, a row decoder 128, and a sense amplifier module 129.

The memory cell array 121 includes a plurality of nonvolatile memory cells (not shown) associated with word lines and bit lines. The plurality of nonvolatile memory cells are subjected to write processing and read processing in units of so-called pages, and are subjected to erase processing in units of so-called physical blocks BLK (BLK0, BLK1, …) including a plurality of pages. Each physical block BLK has a plurality of string units SU0 to SU 3. Each of the string units SU0 to SU3 functions as a drive unit in the physical block BLK. Each of the string units SU0 to SU3 includes a plurality of memory strings. Each memory string MST includes a plurality of memory cell transistors each functioning as a nonvolatile memory cell.

The data signal DQ < 7 is transmitted and received between the input/output circuit 122 and the controller 110: 0 >, and strobe signals DQS and/DQS. The input/output circuit 122 determines that the data signal DQ < 7 based on the strobe signal DQS and/DQS: 0 > and the address and transfer them into register 124. The input/output circuit 122 determines write data and read data based on the strobe signals DQS and/DQS, and transmits and receives the data to and from the sense amplifier module 129.

Logic control circuit 123 receives signals/CE, CLE, ALE,/WE, RE,/RE, and/WP from controller 110. In addition, the logic control circuit 123 transmits the signal/RB to the controller 110, thereby notifying the state of the semiconductor storage device 120 to the outside.

The register 124 holds instructions and addresses. Register 124 passes addresses into row decoder 128 and sense amplifier module 129, and instructions into sequencer 125.

Sequencer 125 receives the instruction, and controls the entire semiconductor memory device 120 in accordance with the sequence based on the received instruction.

The voltage generation circuit 126 generates voltages necessary for operations such as writing, reading, and erasing of data based on instructions from the sequencer 125. The voltage generation circuit 126 supplies the generated voltage into the driver component 127.

The driver component 127 includes a plurality of drivers that supply various voltages from the voltage generation circuit 126 into the row decoder 128 and the sense amplifier module 129 based on the address from the register 124. Driver component 127 supplies various voltages to row decoder 128, for example, based on the row address in the address.

The row decoder 128 receives a row address from the register 124, and selects memory cells of a row based on the row address. Also, to the memory cells of the selected row, the voltage from the driver component 127 is transferred via the row decoder 128.

The sense amplifier module 129 senses read data read from the memory cell to the bit line at the time of data read and transfers the sensed read data to the input-output circuit 122. The sense amplifier module 129 transfers write data written via the bit line to the memory cell at the time of data writing. In addition, the sense amplifier module 129 receives a column address among the addresses from the register 124 and outputs data of a column based on the column address.

The input/output pin group 130 transmits the data signal DQ < 7: 0 >, and strobe signals DQS and/DQS are passed to input-output circuit 122. The input/output pin group 130 converts the data signal DQ < 7 sent from the input/output circuit 122 into: 0 > is transferred to the outside of the semiconductor memory device 120.

The logic control pins 131 transmit the signals/CE, CLE, ALE,/WE, RE,/RE, and/WP received from the controller 110 to the logic control circuit 123. The logic control pin group 131 transmits the signal RB transmitted from the logic control circuit 123 to the outside of the semiconductor memory device 120.

The input/output circuit 122 in the semiconductor memory device 120 may be configured as shown in fig. 3. Fig. 3 is a block diagram for explaining a functional configuration of the input/output circuit 122.

As shown in FIG. 3, the input/output circuit 122 includes input circuits 221 < 7: 0 >, (iii) output circuit 222 < 7: 0 >, input circuit 223, output circuit 224, and data latch 225 < 7: 0 >. The input circuit 221 < k > is an input circuit for the data signal DQ < k >. The input circuit 223 is an input circuit for the strobe signals DQS,/DQS.

For the set of input circuit 221 < k > and output circuit 222 < k >, for example, the distribution data signal DQ < k > (0 ≦ k ≦ 7). That is, the input circuit 221 < k > and the output circuit 222 < k > groups can communicate with the external controller 110 via the pins 130 < k > in the input/output pin group 130, so that the data signals DQ < k > can be communicated. Input circuit 221 < K > if a data signal DQ < K > is received, a data signal DQ2 < K > is generated and sent out to the corresponding data latch 225 < K >.

The set of input circuit 223 and output circuit 224 can communicate with the external controller 110 via the pin 130_ DQS in the input/output pin group 130 with the strobe signals DQS and/DQS. Input circuit 223, if receiving strobe signals DQS and/DQS, generates strobe signals/DQS 2 and DQS2 and sends these signals out to data latches 225 < 7: 0 > medium.

Data latch 225 < 7: 0 > if the input signal from the corresponding input circuit 221 < 7: 0 > received data signals DQ2 < 7, respectively: 0 >, and receives the strobe signals/DQS 2 and DQS2 from the input circuit 223, the data signals DQ < 7: and 0 > the data contained therein.

Further, the input circuits 221, 223 are also referred to as input buffers or input receivers.

The input circuits 221 and 223 and the data latch 225 in the input/output circuit 122 may be configured as shown in fig. 4. Fig. 4 is a circuit diagram for explaining the configuration of the input circuits 221 and 223 and the data latch 225.

The input circuit 221 includes a comparator COMP1 and an inverter group IG 1. The input circuit 223 includes a comparator COMP2, and inverter groups IG2 and IG 3.

The comparator COMP1 includes a 1 st input terminal to which the data signal DQ is supplied, a 2 nd input terminal to which the reference signal VREF is supplied, and an output terminal connected to the input terminal of the inverter group IG 1. The reference signal VREF is a reference voltage having a fixed value and is used as a logical decision threshold of the data signal DQ. The comparator COMP1 compares the data signal DQ with the reference signal VREF, and outputs a data signal DQ1, the amplitude of which is amplified in correspondence with the data signal DQ 1. The inverter group IG1 includes a plurality of inverters INV-1 to INV-3 connected in series, and an output node of the inverter INV-3 at the final stage serves as an output terminal of the output data signal DQ 2. The inverter group IG1 generates a data signal DQ2 obtained by logically inverting the data signal DQ1 output from the comparator COMP1 when it includes an odd number of inverters, for example, and outputs the generated data signal DQ2 from an output terminal.

The comparator COMP2 includes a 1 st input terminal to which the strobe signal DQS is supplied, a 2 nd input terminal to which the strobe signal/DQS is supplied, a 1 st output terminal connected to the input terminal of the inverter group IG2, and a 2 nd output terminal connected to the input terminal of the inverter group IG 3. The comparator COMP2 compares the strobe signal DQS with the strobe signal/DQS and outputs a strobe signal/DQS 1 whose amplitude is amplified corresponding to the strobe signal/DQS from the 1 st output terminal and a strobe signal DQS1 whose amplitude is amplified corresponding to the strobe signal DQS from the 2 nd output terminal. The inverter groups IG2 and IG3 each include a plurality of inverters INV connected in series, and the output nodes of the inverters INV at the final stage serve as output terminals for outputting the strobe signals/DQS 2 and DQS 2. The inverter groups IG2 and IG3 each include a plurality of inverters INV connected in series, and the output nodes of the inverters INV at the final stage serve as output terminals for outputting the strobe signals/DQS 2 and DQS 2. The inverter groups IG2 and IG3 generate the same logic strobe signals/DQS 2 and DQS2 as the strobe signals/DQS 1 and DQS1 output from the comparator COMP2, respectively, when they include an even number of inverters, respectively, for example. The strobe signals/DQS 2 and DQS2 are, for example, signals whose logics are opposite to each other.

The data latch 225 includes a latch circuit 225e and a latch circuit 225 o. The latch circuits 225e and 225o are configured to receive the strobe signals/DQS 2 and DQS2 in inverted logic from each other, respectively. Thus, the latch circuits 225e and 225o alternately latch data adjacent to each other among the data included in the data signal DQ 2. That is, when the latch circuit 225e latches the even-numbered data included in the data signal DQ2, the latch circuit 225o latches the odd-numbered data included in the data signal DQ 2.

In the semiconductor integrated circuit 132, high speed and low power consumption are required for the input/output circuit 122.

If a high-speed data signal DQ is input to the input circuit 221 in order to meet the demand for higher speed, there is a possibility that the setup time and hold time in the data latch process cannot be sufficiently secured due to jitter of the data signal DQ2 transferred from the input circuit 221 to the data latch 225, and an erroneous data value is latched.

On the other hand, if the power supply current supplied to the input circuit 221 is increased, the input data signal DQ can be amplified with a high gain and a wide band, and the slew rate of the output data signal VOUT can be increased, so that jitter of the data signal DQ2 transferred to the data latch 225 can be suppressed. In this case, it is difficult to satisfy the low power consumption requirement of the input/output circuit 122. It is desirable to appropriately transfer a data signal from the input circuit 221 to the data latch 225 as a subsequent circuit while suppressing jitter and suppressing power consumption.

Therefore, in the present embodiment, the semiconductor integrated circuit 132 is provided with a time constant additional circuit added to the comparator COMP1 of the input circuit 221 to improve the characteristics of internal signal transmission, thereby achieving both suppression of jitter and suppression of power consumption.

Specifically, a first amplifier and a second amplifier are provided in the comparator COMP1 of the input circuit 221, and a time constant adding circuit is added between a load circuit in the second amplifier and an intermediate node. The time constant adding circuit adds a time constant between the load circuit and the intermediate node so as to improve characteristics of signal transmission from the load circuit to the intermediate node. For example, the time constant adding circuit adds a time constant between the load circuit and the intermediate node in such a manner that the phase of the signal waveform is advanced. Thereby, the waveform transition of the data signal in the second amplifier from the load circuit to the intermediate node can be made steep, thereby improving the slew rate. That is, the input data signal DQ can be amplified with a high gain and a wide band without increasing the power supply current supplied to the input circuit 221, and the slew rate of the output data signal DQ1 can be improved. As a result, since the jitter of the data signal DQ2 supplied to the data latch 225 can be suppressed, both the jitter and the power consumption can be suppressed. That is, the data signal can be appropriately transferred from the input circuit 221 to the data latch 225 as a subsequent stage circuit.

More specifically, the input circuit 221 may be configured as shown in fig. 5, for example. Fig. 5 is a diagram showing an example of the configuration of the input circuit 221. In the input circuit 221, the comparator COMP1 has a first amplifier 10 and a second amplifier 20. The second amplifier 20 is electrically connected to the first amplifier 10.

The first amplifier 10 is a single-ended input, differential output type amplifier. The first amplifier 10 has a differential circuit 11 and a load circuit 12. The differential circuit 11 is disposed between the power supply potential and the load circuit 12. The load circuit 12 is disposed between the differential circuit 11 and the ground potential. The differential circuit 11 and the load circuit 12 are electrically connected to each other via the nodes N1 and N2. Nodes N1 and N2 correspond to the N side and the P side of the differential, respectively. The first amplifier 10 receives the data signal DQ and the reference signal VREF, generates differential signals IMN and IMP corresponding to the data signal DQ, and outputs these signals to the second amplifier 20 via the nodes N1 and N2.

For example, as shown in fig. 6(a) and 6(b), the first amplifier 10 makes the signal IMP on the P side higher than the reference signal VREF and makes the signal IMN on the N side lower than the reference signal VREF, in response to the data signal DQ being lower than the reference signal VREF. The first amplifier 10 lowers the P-side signal IMP below the reference signal VREF and raises the N-side signal IMN above the reference signal VREF, depending on whether the data signal DQ is higher than the reference signal VREF. Thus, the first amplifier 10 differentially signals the data signal DQ, which is a single signal, into the signal IMP on the P side and the signal IMN on the N side.

The differential circuit 11 shown in fig. 5 includes a transistor M5, a transistor M6, and a current source CS. The transistor M5 and the transistor M6 form a differential pair. The transistor M5 and the transistor M6 may be each formed of a PMOS (P-channel Metal Oxide Semiconductor) transistor. The transistor M5 has a gate for receiving the reference signal VREF, a drain electrically connected to the node N1, and a source electrically connected to one end of the current source CS. The transistor M6 has a gate for receiving the data signal DQ, a drain electrically connected to the node N2, and a source electrically connected to one end of the current source CS. A gate of the transistor M6 constitutes an input node of the data signal DQ in the comparator COMP1, and a gate of the transistor M5 constitutes an input node of the reference signal VREF in the comparator COMP 1. The other end of the current source CS is electrically connected to the power supply potential. The current source CS may be formed of a transistor M10 such as a PMOS transistor. The transistor M10 has a gate for receiving a predetermined bias signal, a drain electrically connected to the transistor M5 and the transistor M6, and a source electrically connected to the power supply potential.

The load circuit 12 has an element Z11 and an element Z12. The element Z11 and the element Z12 may be each formed of a resistance element, or may be formed of an NMOS (N-channel Metal Oxide Semiconductor) transistor whose gate is supplied with a predetermined bias voltage. The element Z11 has one end electrically connected to the node N1 and the other end electrically connected to the ground potential. The element Z12 has one end electrically connected to the node N2 and the other end electrically connected to the ground potential.

The second amplifier 20 is a differential input, single-ended output type amplifier. The second amplifier 20 includes a differential circuit 21, a load circuit 22, a load circuit 23, and a time constant adding circuit 24. The differential circuit 21 is disposed between the power supply potential and the load circuits 22 and 23. The load circuit 22 is a load circuit on the N-side of the differential, and is a load circuit corresponding to the signal IMN on the N-side. The load circuit 23 is a load circuit on the P-side in the difference, and is a load circuit corresponding to the signal IMP on the P-side. The load circuit 22 and the load circuit 23 are respectively disposed between the differential circuit 21 and the ground potential. The differential circuit 21 and the load circuit 22 are electrically connected to each other via a node N4. The differential circuit 21 and the load circuit 23 are electrically connected to each other via a node N3. The node N3 constitutes an output node in the comparator COMP 1.

The time constant adding circuit 24 is disposed between the load circuit 22 and the node N5, and is electrically connected between the load circuit 22 and the node N5. The node N5 is electrically connected to the node N4, the time constant adding circuit 24, and the load circuit 23, and constitutes an intermediate node in the second amplifier 20. Thus, the time constant adding circuit 24 adds a time constant between the load circuit 22 and the node N5, thereby making it possible to improve the characteristics of signal transmission from the node N4 to the node N3 (output node) via the node N5 (intermediate node).

The differential circuit 21 includes a transistor M1, a transistor M2, an element Z1, and an element Z3. The transistor M1 and the transistor M2 form a differential pair. The transistor M1 and the transistor M2 may be PMOS transistors, respectively. The transistor M1 has a gate receiving the N-side signal IMN, a drain electrically connected to the node N4, and a source electrically connected to one end of the device Z1. The element Z1 has one end electrically connected to the transistor M1 and the other end electrically connected to a power supply potential. The transistor M2 has a gate receiving the signal IMP at the P-side, a drain electrically connected to the node N3, and a source electrically connected to one end of the device Z3. The element Z3 has one end electrically connected to the transistor M2 and the other end electrically connected to a power supply potential.

The load circuit 22 has a transistor M3 and an element Z2. The transistor M3 may be formed of an NMOS transistor. The transistor M3 has a gate electrically connected to the node N5 via the time constant additional circuit 24, a drain electrically connected to the node N4, and a source electrically connected to one end of the element Z2. The element Z2 has one end electrically connected to the transistor M3 and the other end electrically connected to the ground potential.

The load circuit 23 has a transistor M4 and an element Z4. The transistor M4 may be formed of an NMOS transistor. The transistor M4 has a gate electrically connected to the node N5, a drain electrically connected to the node N3, and a source electrically connected to one end of the device Z4. The element Z4 has one end electrically connected to the transistor M4 and the other end electrically connected to the ground potential.

The transistor M3 and the transistor M4 constitute a current mirror circuit via the time constant adding circuit 24. A current corresponding to a specified mirror ratio with respect to the current flowing through the node N4 flows to the node N3. That is, the signal IMN on the N side is transmitted to the node N3 by the path of the transistor M1 → the node N4 → the load circuit 22 (the transistor M3) and the time constant addition circuit 24 → the node N5 → the load circuit 23 (the transistor M4) → the node N3, and the signal IMP on the P side is transmitted to the node N3 by the path of the transistor M2 → the node N3. The difference between the signal on the N-side and the signal on the P-side is output from the node N3 to the inverter INV-1 in the form of an output data signal DQ 1.

In addition, the inverter INV-1 has transistors M21 and M22 and elements Z5 and Z6 connected in reverse. The transistor M21 is a PMOS transistor having a gate electrically connected to the node N3, a drain electrically connected to the node N11, and a source electrically connected to one end of the device Z5. The element Z5 has one end electrically connected to the transistor M21 and the other end electrically connected to a power supply potential. The transistor M22 is an NMOS transistor having a gate electrically connected to the node N3, a drain electrically connected to the node N11, and a source electrically connected to one end of the device Z6. The element Z6 has one end electrically connected to the transistor M22 and the other end electrically connected to the ground potential.

For example, as shown in fig. 6(b) and 6(c), the second amplifier 20 makes the output data signal DQ1 significantly lower than the reference signal VREF' according to the case where the signal IMN on the N side is lower than the signal IMP on the P side. The second amplifier 20 makes the output data signal DQ1 be substantially higher than the reference signal VREF' according to the condition that the signal IMN on the N side is higher than the signal IMP on the P side. Thus, the second amplifier 20 converts the P-side signal IMP and the N-side signal IMN, which are differential signals, into the output data signal DQ 1.

At this time, the time constant adding circuit 24 shown in fig. 5 adds a time constant between the transistor M3 and the node N5. The time constant adding circuit 24 and the load circuit 22 are configured such that the equivalent impedance observed from the node N4 becomes inductive. The time constant additional circuit 24 has a resistance element R1, and equivalently further has a parasitic capacitance Cp. One end of the resistor R1 is electrically connected to the gate of the transistor M3, and the other end is electrically connected to the node N5. The resistance element R1 has a resistance value of k Ω level, for example, a resistance value of about several k Ω. The parasitic capacitance Cp is an equivalent capacitance component parasitically formed between the line LN1 and the transistor M3 and the ground potential. A line LN1 electrically connects the gate of the transistor M3 to one end of the resistive element R1.

For example, as shown in FIG. 7(a), transistor M3 is equivalently the transconductance g_m(M3)And the function is played. As shown in fig. 7(b), the structure in which one end of the resistor element R1 and one end of the parasitic capacitor Cp are connected to the gate of the transistor M3 equivalently functions as a structure in which the series connection of the inductor element L and the resistor element R is connected in parallel to the line LN 2. That is, the time constant adding circuit 24 and the load circuit 22 substantially function as the sensing element L.

At this time, the inductance value of the inductive element L is expressed by the following expression 1, and the resistance value of the resistive element R is expressed by the following expression 2.

L＝(Cp·R1)/(g_m(M3)) … formula 1

R＝1/(g_m(M3)) … equation 2

In equation 1, Cp represents a capacitance value of the parasitic capacitance Cp, and R1 represents a resistance value of the resistive element R1. In numerical formula 1 and numerical formula 2, g_m(M3)Representing the transconductance value of transistor M3.

Fig. 7(c) shows a structure including the structure shown in fig. 7(b) and further including the transistor M1. In this configuration, the transistor M1 is equivalently a transconductance g_m(M1)And the function is played. The combined capacitance of the capacitance component parasitically generated between the line LN2 and the ground potential and the element connected to Vout is C_LThe signal input to the gate of the transistor M1 is set to V_inThe signal output from the node N5 is set to V_out. The series connection of the inductor L and the resistor R connected to the drain of the transistor M1 via the node N4 and the line LN2 function equivalently as a configuration in which a current value g is connected in parallel between the ground potential and the node N5 as shown in fig. 7(d)_m(M1)·V_inCurrent source, inductive element L and resistive element RAnd a parasitic capacitance C_L. In the configuration shown in FIG. 7(d), the input signal V is_inAnd an output signal V_outThe transfer function h(s) between them is expressed by the following equation 3.

H(s)＝-g_m(M1)·{(R+sL)/(s²LC_L+sRC_L+1) } … numerical formula 3

On the other hand, in the configuration in which the sensor L is omitted from fig. 7(d), the input signal V is input_inAnd an output signal V_outThe transfer function h(s) between them is expressed by the following equation 4.

H(s)＝-g_m(M1)·{R/(sRC_L+1) } … numerical formula 4

As can be seen from equation 4, in the frequency characteristic of the configuration in which the inductance element L is omitted from fig. 7(d), 1 pole exists and no zero exists as shown by the chain line of one dot in fig. 8. Fig. 8 is a graph showing the frequency characteristics of expressions 3 and 4, in which the vertical axis shows the gain of the circuit and the horizontal axis shows the magnitude of the frequency. The frequency characteristic represented by the single-dot chain line in fig. 8 appears at the desired frequency f_NThe tendency of the signal intensity to decay.

In contrast, according to equation 3, in the frequency characteristic having the configuration shown in fig. 7(d), the zero point and the pole are increased by 1 each, and as shown by the solid line in fig. 8, the frequency is slightly lower than the frequency f_NThe attenuation of the gain is suppressed so that the desired frequency f can be set_NThe gain is ensured. For example, the frequency of the zero point is slightly lower than the frequency f_NShows a tendency of a slight increase in gain in the vicinity of the frequency of the zero point, and the frequency of the pole is the frequency f_NAnd nearby, translates into a tendency for gain to decrease at the frequency of the pole. From the frequency characteristics shown by the solid line in fig. 8, it can be seen that the frequency f is the desired frequency f_NCan suppress the attenuation of the signal intensity.

As shown in fig. 9, the input circuit is viewed from the perspective of the signal waveform. Fig. 9 is a waveform diagram showing an operation of the input circuit in the embodiment. Fig. 9(a) shows waveforms of the data signal DQ and the reference signal VREF input to the first amplifier 10. Fig. 9(b) is a waveform of the gate potential of the transistor M3. Fig. 9(c) shows a waveform of the potential at the node N5, which can be regarded as a waveform of the gate potential of the transistor M4. Fig. 9(d) shows a waveform of the output data signal DQ1, which can also be regarded as a waveform of the potential of the node N3.

During the period from time t1 to t4 shown in fig. 9(a), the data signal DQ received by the comparator COMP1 is at the L level V_L1To H level V_H1And (4) converting.

The time constant adding circuit 24 is omitted from fig. 5. In this configuration, as shown by a one-dot chain line in fig. 9(b), the gate potential of the transistor M3 of the load circuit 22 is changed from the H level V in a period from time t2 to t6 later than time t1 to t4_H2To L level V_L2And (4) converting. Further, as shown by the one-dot chain line in fig. 9(c), the potential of the node N5 changes from the H level V during the period from time t2 to time t6_H3To L level V_L3And (4) converting. In contrast, as shown by the one-dot chain line in fig. 9(d), the output data signal DQ1 is outputted from the L level V in the period from time t3 to t8 later than time t2 to t6_L4To H level V_H4And (4) converting.

In contrast, in the configuration of fig. 5 including the time constant addition circuit 24, the slope of the waveform of the gate potential of the transistor M3 becomes more gentle as shown by the solid line in fig. 9(b), and the waveform of the potential of the node N5 can be undershot and the slope thereof can be made steeper as shown by the solid line in fig. 9 (c). That is, the gate potential of the transistor M3 changes from the H level V to the H level V in the later period from t2 to t8_H2To L level V_L2The potential at the node N5 changes from the H level V to the H level V at an earlier time point t2 to t5_H3To L level V_L3And (4) converting. In contrast, as shown by the solid line in fig. 9(d), the output data signal DQ1 is at the L level V during the earlier period from t3 to t7_L4To H level V_H4And (4) converting.

That is, the input data signal DQ can be amplified with a high gain and a wide band without increasing the power supply current supplied to the input circuit 221, and the slew rate of the rise in the waveform of the output data signal DQ1 can be improved. As a result, jitter of the data signal DQ2 transferred to the data latch 225 can be suppressed with low power consumption.

In addition, during the period from time t11 to time t14 shown in fig. 9(a), the data signal DQ received by the comparator COMP1 is at the H level V_H1To L level V_L1And (4) converting.

The time constant adding circuit 24 is omitted from fig. 5. In this configuration, as shown by a one-dot chain line in fig. 9(b), the gate potential of the transistor M3 of the load circuit 22 is changed from the L level V in a period from time t12 to t16 later than time t11 to t14_L2To H level V_H2And (4) converting. Further, as shown by the one-dot chain line in fig. 9(c), the potential of the node N5 changes from the L level V during the period from time t12 to time t16_L3To H level V_H3And (4) converting. In contrast, as shown by the one-dot chain line in fig. 9(d), the output data signal DQ1 is outputted from the H level V in the period from time t13 to t18 later than time t12 to t16_H4To L level V_L4And (4) converting.

In contrast, in the configuration of fig. 5 including the time constant addition circuit 24, the slope of the waveform of the gate potential of the transistor M3 becomes more gentle as shown by the solid line in fig. 9(b), and the waveform of the potential of the node N5 can be overshot and the slope thereof can be made steeper as shown by the solid line in fig. 9 (c). That is, the gate potential of the transistor M3 changes from the L level V during the later period from t12 to t18_L2To H level V_H2The potential at the node N5 changes from the L level V to the earlier time point t12 to t15_L3To H level V_H3And (4) converting. In contrast, as shown by the solid line in fig. 9(d), the output data signal DQ1 is at the H level V in the period from the earlier time point t13 to t17_H4To L level V_L4And (4) converting.

That is, the input data signal DQ can be amplified with a high gain and a wide band without increasing the power supply current supplied to the input circuit 221, and the slew rate of the drop in the waveform of the output data signal DQ1 can be improved. As a result, jitter of the data signal DQ2 transferred to the data latch 225 can be suppressed with low power consumption.

As described above, in the embodiment, the time constant addition circuit 24 is added between the load circuit 22 in the second amplifier 20 of the comparator COMP1 of the input circuit 221 and the intermediate node N5 in the semiconductor integrated circuit 132. The time constant appending circuit 24 appends a time constant between the load circuit 22 and the intermediate node N5 in order to improve the characteristics of signal transmission from the load circuit 22 to the intermediate node N5. Thus, the input data signal DQ can be amplified with a high gain and a wide frequency band without increasing the power supply current supplied to the input circuit 221, and the slew rate of the waveform of the output data signal DQ1 can be improved. As a result, jitter of the data signal DQ2 transferred to the data latch 225 can be suppressed with low power consumption. That is, the semiconductor integrated circuit 132 can suppress both jitter and power consumption.

The resistance element R1 in the time constant adding circuit 24 may be a variable resistance element whose resistance value can be changed according to a predetermined control signal. For example, by preparing a series connection of a plurality of sets of the resistance element and the switch and connecting the plurality of sets in parallel to form the resistance element R1, the resistance element R1 can be a variable resistance element.

Alternatively, as shown in fig. 10, the time constant addition circuit 24i may further include a capacitive element C1 in the second amplifier 20i of the comparator COMP1i of the input circuit 221 i. Fig. 10 is a diagram showing the configuration of the input circuit 221i in the first modification of embodiment 1. One end of the capacitor C1 is electrically connected to the line LN1, and the other end is electrically connected to the ground potential. According to this configuration, the time constant adding circuit 24i can add a time constant between the load circuit 22 and the intermediate node N5 so as to improve the characteristics of signal transmission from the load circuit 22 to the intermediate node N5.

Alternatively, in the first amplifier 10j and the second amplifier 20j of the comparator COMP1j of the input circuit 221j, as shown in fig. 11, the polarities of the transistors of the amplifiers may be inverted with respect to fig. 5. Fig. 11 is a diagram showing a configuration of an input circuit 221j in variation 2 of the embodiment.

In the first amplifier 10j, the transistor M5j and the transistor M6j of the differential circuit 11j may be formed of NMOS transistors. The current source CSj may be formed of a transistor M10j such as an NMOS transistor. The source of the transistor M10j is electrically connected to ground potential. The other end of the element Z11j and the other end of the element Z12j of the load circuit 12 are electrically connected to the power supply potential.

In the second amplifier 20j, the transistor M1j and the transistor M2j of the differential circuit 21j may be formed of NMOS transistors. The other ends of the element Z1j and the element Z3j are electrically connected to the ground potential. The transistor M3j of the load circuit 22j may be formed of a PMOS transistor. The other end of the element Z2j is electrically connected to the power supply potential. The transistor M4j of the load circuit 23j may be formed of a PMOS transistor. The other end of the element Z4j is electrically connected to the power supply potential. The time constant adding circuit 24j has a parasitic capacitance Cpj instead of the parasitic capacitance Cp (refer to fig. 5). The parasitic capacitance Cpj is an equivalent capacitance component parasitically formed between the line LN1 and the transistor M3j and the GND potential.

According to this configuration, the time constant adding circuit 24j can add a time constant between the load circuit 22j and the intermediate node N5 so as to improve the characteristics of signal transmission from the load circuit 22j to the intermediate node N5.

Alternatively, the comparator COMP1 of the input circuit 221 may be a combination of the first amplifier 10 shown in fig. 5 and the second amplifier 20j shown in fig. 11. According to this configuration, the time constant adding circuit 24j can add a time constant between the load circuit 22j and the intermediate node N5 so as to improve the characteristics of signal transmission from the load circuit 22j to the intermediate node N5.

Alternatively, the comparator COMP1 of the input circuit 221 may be a combination of the first amplifier 10j shown in fig. 11 and the second amplifier 20 shown in fig. 5. According to this configuration, the time constant adding circuit 24 can add a time constant between the load circuit 22 and the intermediate node N5 so as to improve the characteristics of signal transmission from the load circuit 22 to the intermediate node N5.

Alternatively, in the comparator COMP1k of the input circuit 221k, as shown in fig. 12, the first amplifier 10k may be a differential input/differential output type amplifier. The first amplifier 10k includes a differential circuit 11k instead of the differential circuit 11 (see fig. 5). The differential circuit 11k receives the data signal/DQ instead of the reference signal VREF by the gate of the transistor M5. The data signal/DQ is a signal of opposite polarity to the data signal DQ received with the gate of the transistor M6. For example, the first amplifier 10k makes the signal IMN on the P side higher than the reference signal VREF and makes the signal IMN on the N side lower than the reference signal VREF, depending on whether the data signal DQ is lower than the data signal/DQ. The first amplifier 10k lowers the P-side signal IMP below the reference signal VREF and raises the N-side signal IMN above the reference signal VREF, depending on whether the data signal DQ is higher than the data signal/DQ. Thus, the first amplifier 10k generates differential signals IMP and IMN from the differential signals DQ and/DQ, and supplies these signals to the second amplifier 20. The operation of the second amplifier 20 is the same as that of the embodiment. That is, according to this configuration, the time constant adding circuit 24 can add a time constant between the load circuit 22 and the intermediate node N5 so as to improve the characteristics of signal transmission from the load circuit 22 to the intermediate node N5.

Several embodiments of the present invention have been described, but these embodiments are only proposed as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in other various ways, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

[ description of symbols ]

10. 10j, 10k first amplifier

20. 20i, 20j second amplifier

24. 24i, 24j time constant adding circuit

120 semiconductor memory device

132 semiconductor integrated circuit

221, an input circuit.