阅读说明：本技术 一种基于非共享存储多核处理器的微系统架构 (Micro-system architecture based on non-shared storage multi-core processor ) 是由 王蕊 冯长磊 陈雷 张彦龙 张拓 阎渊海 王炳雅 于 2021-07-28 设计创作，主要内容包括：本发明公开了一种基于非共享存储多核处理器的微系统架构,在系统中增加可编程逻辑电路,多核处理器每个处理器核独立的存储接口扩展RAM型数据存储器,然后分别连接到可编程逻辑电路,ROM型程序存储器通过可编程逻辑电路实现共享,从而简化系统,同时解决了核间高速、高带宽的大数据量传输瓶颈,提高了系统处理能力。(The invention discloses a micro-system architecture based on a non-shared storage multi-core processor, which is characterized in that a programmable logic circuit is added in a system, an independent storage interface of each processor core of the multi-core processor expands an RAM type data memory and then is respectively connected to the programmable logic circuit, and an ROM type program memory realizes sharing through the programmable logic circuit, thereby simplifying the system, solving the bottleneck of high-speed and high-bandwidth large-data-volume transmission between cores and improving the processing capacity of the system.)

1. A micro-system architecture based on a non-shared storage multi-core processor is characterized by comprising the non-shared storage multi-core processor, an RAM type data memory, an ROM type program memory and a programmable logic circuit;

the unshared storage multi-core processor comprises a plurality of processor cores; the plurality of processor cores comprise a main core and more than one auxiliary core, the main core realizes the loading of a Boot Loader program, calls main core user program codes from a ROM type program memory to an exclusive RAM type data memory of the main core according to the Boot Loader program, and schedules and manages the auxiliary cores according to the main core user program codes; the slave core responds to the command of the master core, calls the slave core user program codes, the calculation models and the parameters from the ROM type program memory to the RAM type data memory exclusive to each slave core, and completes the calculation of the related algorithm and data processing;

the number of the RAM type data memory is the same as that of the processor cores, and the RAM type data memory is respectively exclusive to each processor core and used for calling each core user program code, each calculation model and each parameter from the ROM type program memory by external input or temporary data generated in each secondary core calculation process;

the ROM type program memory is used for storing configuration codes of the programmable logic circuit, Boot Loader programs, user program codes of various cores, and calculation models and parameters;

the programmable logic circuit is used for loading configuration codes of the programmable logic circuit in the ROM type program memory and solidifying a Boot Loader program, user program codes of various cores, parameters required by calculation and a calculation model to the ROM type program memory on the basis of the configuration codes of the programmable logic circuit; the device is used for loading a Boot Loader program in a ROM type program memory into a main core; the method is used for realizing data exchange between the processor cores and the ROM type program memory.

2. The microsystem architecture based on the unshared storage multi-core processor as claimed in claim 1, wherein the programmable logic circuit is internally provided with a Buffer and an interconnection module for realizing data exchange between the processor cores and the ROM-type program memory, each processor core corresponds to one group of buffers, the ROM-type program memory corresponds to one group of buffers, and the interconnection module selects a destination Buffer according to a destination address in a request sent by each processor core based on a packet routing protocol to establish two paths for data transmission.

3. The micro-system architecture based on the unshared storage multi-core processor as claimed in claim 2, wherein the interconnection module is provided with a plurality of groups of Buffer interfaces with asynchronous read-write functions, and is used for realizing data transmission between the interconnection module and each Buffer.

4. The micro-system architecture based on the unshared storage multi-core processor of claim 3, wherein when the plurality of processor cores send requests to the interconnection module, the interconnection module sorts the requests sent by the processor cores according to the time of sending the requests by the processor cores, and the requests are sequentially linked for transmission.

5. The architecture of claim 1, wherein each processor core of the unshared storage multi-core processor has an independent configuration storage interface, and is connected with the RAM type data storage and the programmable logic circuit through the independent configuration storage interfaces.

6. The micro-system architecture based on the unshared storage multi-core processor as claimed in claim 1, wherein the configuration code of the programmable logic circuit comprises a programming code, and the Boot Loader program, the user program codes of each core, and the calculation model and the parameters are solidified to the ROM type program memory by using a corresponding development tool through the programming code.

7. The micro-system architecture based on the unshared storage multi-core processor according to claim 1, wherein the programmable logic circuit is provided with an internal host port I _ HPI, DMA or EDMA transmission is established with the unshared storage multi-core processor through the internal host port I _ HPI, and a Boot Loader program, user program codes of cores, a calculation model and parameters in a ROM type program memory are loaded into the core processors.

8. The micro-system architecture based on the unshared storage multi-core processor of claim 7, wherein the programmable logic circuit is provided with an external host port E _ HPI, and data transmission is performed with an external host through the external host port E _ HPI; the external host port E _ HPI is directly communicated with the internal host port I _ HPI, and the external host directly controls the internal host port I _ HPI through the external host port E _ HPI.

9. The micro-system architecture based on the unshared storage multi-core processor, as claimed in claim 1, wherein the programmable logic circuit is provided with an external expansion interface for communicating with external devices, the external expansion interface comprising one or more of a low speed external expansion interface or a high speed external expansion interface; the low-speed external expansion interface comprises one or more of I2C, USART, SPI, CAN or 1553B, and the high-speed external expansion interface comprises one or more of SRIO, PCIE or gigabit Ethernet.

Technical Field

The invention belongs to the field of missile-borne weapon computer application, relates to a micro-system architecture, and particularly relates to a micro-system architecture based on an unshared storage multi-core processor.

Background

With the increasingly wide application of technologies such as real-time image processing, target capturing and tracking, accurate guidance and the like in the military field and the urgent requirements of a new generation of military equipment on high performance, miniaturization, light weight and high reliability of an electronic system, the adoption of an isomorphic or heterogeneous multi-core processor system becomes a main approach for solving the bottleneck of high-performance calculation and parallel calculation. A multi-core processor with non-shared storage is provided, the processor core is respectively provided with an independent storage interface and a storage body, each processor core can only access the storage space of the processor core, the storage space independently ensures the reliability and the consistency of data, simultaneously improves the bandwidth of the access memory and reduces the data conflict of the access memory. The unshared storage multi-core processor has the disadvantage that as the number of processor cores increases, a system is very large and complex, and cannot meet the requirement of miniaturization of new-generation military equipment.

Disclosure of Invention

The invention aims to overcome the defects and provides a micro-system architecture based on a non-shared storage multi-core processor, wherein a programmable logic circuit is added in the system, the independent storage interface of each processor core of the multi-core processor expands an RAM type data memory and then is respectively connected to the programmable logic circuit, and a ROM type program memory is shared through the programmable logic circuit, so that the system is simplified, meanwhile, the bottleneck of high-speed and high-bandwidth large-data-volume transmission among cores is solved, and the processing capacity of the system is improved.

In order to achieve the above purpose, the invention provides the following technical scheme:

a micro-system architecture based on a non-shared storage multi-core processor comprises the non-shared storage multi-core processor, an RAM type data memory, an ROM type program memory and a programmable logic circuit;

the unshared storage multi-core processor comprises a plurality of processor cores; the plurality of processor cores comprise a main core and more than one auxiliary core, the main core realizes the loading of a Boot Loader program, calls main core user program codes from a ROM type program memory to an exclusive RAM type data memory of the main core according to the Boot Loader program, and schedules and manages the auxiliary cores according to the main core user program codes; the slave core responds to the command of the master core, calls the slave core user program codes, the calculation models and the parameters from the ROM type program memory to the RAM type data memory exclusive to each slave core, and completes the calculation of the related algorithm and data processing;

the number of the RAM type data memory is the same as that of the processor cores, and the RAM type data memory is respectively exclusive to each processor core and used for calling each core user program code, each calculation model and each parameter from the ROM type program memory by external input or temporary data generated in each secondary core calculation process;

the ROM type program memory is used for storing configuration codes of the programmable logic circuit, Boot Loader programs, user program codes of various cores, and calculation models and parameters;

the programmable logic circuit is used for loading configuration codes of the programmable logic circuit in the ROM type program memory and solidifying a Boot Loader program, user program codes of various cores, parameters required by calculation and a calculation model to the ROM type program memory on the basis of the configuration codes of the programmable logic circuit; the device is used for loading a Boot Loader program in a ROM type program memory into a main core; the method is used for realizing data exchange between the processor cores and the ROM type program memory.

Furthermore, the programmable logic circuit is internally provided with a Buffer and an interconnection module for realizing data exchange between the processor cores and the ROM type program memory, each processor core corresponds to one group of buffers, the ROM type program memory corresponds to one group of buffers, and the interconnection module selects a target Buffer according to a target address in a request sent by each processor core based on a packet routing protocol, establishes two paths and transmits data.

Furthermore, the interconnection module is provided with a plurality of groups of Buffer interfaces with asynchronous read-write functions, and is used for realizing data transmission between the interconnection module and each Buffer.

Further, when the plurality of processor cores send requests to the interconnection module, the interconnection module sorts the requests sent by the processor cores according to the time of sending the requests by the processor cores, and the requests are sequentially linked and transmitted.

Furthermore, each processor core in the unshared storage multi-core processor is provided with an independent storage interface, and is connected with the RAM type data storage and the programmable logic circuit through the independent storage interfaces.

Furthermore, the configuration code of the programmable logic circuit comprises a programming program code, and a Boot Loader program, user program codes of various cores, a calculation model and parameters are solidified to a ROM type program memory by using a corresponding development tool through the programming program code.

Furthermore, the programmable logic circuit is provided with an internal host port I _ HPI, DMA or EDMA transmission is established with the unshared storage multi-core processor through the internal host port I _ HPI, and a Boot Loader program, user program codes of various cores and calculation models and parameters in the ROM type program memory are loaded into the various core processors.

Furthermore, the programmable logic circuit is provided with an external host port E _ HPI, and data transmission is carried out with an external host through the external host port E _ HPI; the external host port E _ HPI is directly communicated with the internal host port I _ HPI, and the external host directly controls the internal host port I _ HPI through the external host port E _ HPI.

Further, the programmable logic circuit is provided with an external expansion interface used for communicating with external equipment, and the external expansion interface comprises one or more of a low-speed external expansion interface or a high-speed external expansion interface; the low-speed external expansion interface comprises one or more of I2C, USART, SPI, CAN or 1553B, and the high-speed external expansion interface comprises one or more of SRIO, PCIE or gigabit Ethernet.

Compared with the prior art, the invention has the following beneficial effects:

(1) the invention relates to a micro-system architecture based on a non-shared storage multi-core processor.A programmable logic circuit is added in the system, and an independent storage interface of each processor core of the multi-core processor expands an RAM type data memory and is then respectively connected to the programmable logic circuit, thereby realizing the sharing of the ROM type program memory, simplifying the system and ensuring the reliability and consistency of data;

(2) according to the micro-system architecture based on the non-shared storage multi-core processor, data exchange is realized among the core processors and between each core processor and the ROM type program memory through the buffer and the special interconnection module, the data transmission bottleneck is solved, and the system processing capacity is improved;

(3) the invention relates to a micro-system architecture based on a non-shared storage multi-core processor.A plurality of ports are arranged on a programmable logic circuit and used for realizing data transmission between the non-shared storage multi-core processor and an external host, and a plurality of external expansion interfaces are also arranged and used for realizing the function expansion of a system;

(4) the micro-system architecture based on the unshared storage multi-core processor simplifies the system design, solves the data transmission bottleneck, improves the system efficiency, has the advantages of high integration level, small volume, good flexibility and the like, enables the realization of the unshared storage multi-core processor micro-system based on the micro-system integration to be possible, and has wide application prospect in the field of multi-core missile-borne main control calculation of high-speed signal processing with large computation amount and data amount.

Drawings

FIG. 1 is a schematic diagram of a basic architecture of a micro-system architecture based on an unshared storage multi-core processor according to the present invention;

FIG. 2 is a detailed system framework of a micro-system architecture based on an unshared storage multi-core processor according to the present invention;

FIG. 3 is a flowchart illustrating a program loading process based on a non-shared-memory multi-core processor according to the present invention.

Detailed Description

The features and advantages of the present invention will become more apparent and appreciated from the following detailed description of the invention.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

With the increase of the number of processor cores, a system based on a non-shared storage multi-core processor is very large and complex, especially, storage resources are greatly wasted, and the area or volume of the system is increased in proportion. In the prior art, in order to improve the bandwidth of an access memory and reduce data collision of the access memory, a non-shared memory multi-core processor is composed of a plurality of processor cores which are isomorphic or heterogeneous, and each processor core is respectively provided with an independent memory interface and a memory bank which comprise an RAM and an ROM. Each processor core can only access own memory space, which ensures the reliability and consistency of data. Meanwhile, the multi-core processor also comprises an inter-core communication hardware circuit.

The invention provides a micro-system architecture based on a non-shared storage multi-core processor, which consists of the non-shared storage multi-core processor, an RAM type data memory, an ROM type program memory and a programmable logic circuit.

The programmable logic circuit is added in the system, so that the ROM type program memory of the multi-core processor is shared through the programmable logic circuit, the system design is simplified, the data transmission bottleneck is solved, the system efficiency is improved, and the realization of the non-shared storage multi-core processor micro-system based on micro-system integration becomes possible. The invention is oriented to the field of multi-core missile-borne master control calculation of high-speed signal processing with large computation amount and data amount, and compared with the traditional multi-core missile-borne computer system, the micro system realized based on the invention has the advantages of high integration level, small volume, good flexibility and the like.

The invention provides a micro-system architecture based on a non-shared storage multi-core processor, which mainly comprises the non-shared storage multi-core processor, a RAM (random access memory) type data memory, a ROM (read only memory) type program memory and a programmable logic circuit, as shown in figure 1.

In a system architecture, a non-shared storage multi-core processor is composed of a plurality of processor cores which are isomorphic or heterogeneous, each processor core is respectively provided with an independent storage interface and an RAM type data memory, and each processor can only access the RAM type data memory of the processor. The plurality of processor cores of the unshared storage have a main core and the rest are auxiliary cores. The master core is responsible for the distribution, scheduling and management of tasks and the synchronization and state monitoring among other slave cores; the slave core responds to the command of the master core and completes the calculation of the related algorithm and data processing;

the RAM type data memory is used for storing programs and data of each core; the RAM type data memory is an independent memory of each processor core so as to ensure the reliability and consistency of data;

the ROM type program memory stores four parts: (1) programmable logic circuit configuration code, including code to program; (2) boot Loader programs of all cores; (3) each core user program code; (4) calculating a model and parameters;

the programmable logic circuit has an automatic loading function, a code solidification function, a multi-core processor BOOT function, an inter-core high-bandwidth data exchange function and an external expansion function.

The programmable logic circuit has different roles and different functions in different system operation stages, and is used as a system main control to realize an automatic loading function, a code curing function and a multi-core processor BOOT function in a system starting stage so as to complete the sequential loading of system programs; after the system is started, the inter-core high-bandwidth data exchange function and the peripheral extension function are realized, and the system is used as external equipment of the multi-core processor and realizes the extension of system functions through an external extension interface;

the function of the programmable logic circuit is described in detail as follows:

(1) auto-load and code curing functionality

After the programmable logic circuit is powered on, the programmable logic circuit configuration code, namely the FPGA configuration data in fig. 2, is automatically loaded from the ROM type program memory 0 address, and the programmable logic circuit configuration code includes a program-programming code, and after the programmable logic circuit is automatically loaded, a user can sequentially program-programming codes of each core, namely the core 1-core n program, the calculation model and the parameters in fig. 2, into the ROM type program memory by using a corresponding development tool.

(2) Multi-core processor BOOT

The programmable logic circuit is provided with two Host-Port interfaces (HPI for short), an internal Host Port (I _ HPI) is arranged between the programmable logic circuit and the multi-core processor, and an external Host Port (E _ HPI) is used for realizing communication with an external Host; the programmable logic circuit loads the codes in the ROM type program memory into each core processor through the interconnection module and the I _ HPI port to realize the guidance of the multi-core processor; or the E _ HPI port may be directly connected to the I _ HPI, and the start of the multi-core processor is handed over to an external host, which is described in detail as follows:

the programmable logic circuit sequentially initializes the storage space of each core through an Internal Host-Port Interface (I _ HPI), establishes DMA or EDMA transmission, configures an on-chip register and the like, loads a Boot Loader program to the 0 address space of the main core through the DMA or EDMA, wakes up the main core to execute from the 0 address, the main core moves user program codes of each core to the RAM type data memory corresponding to each processor core according to a secondary guide table in the Boot Loader program, the Boot Loader program finally jumps to instruct to start the user program, and the BOOT of the multi-core processor is finished.

The programmable logic circuit is also provided with an E _ HPI port (external host port), the E _ HPI port is in data transmission with an external host through the external host port E _ HPI, the E _ HPI port can also be directly connected to the I _ HPI, the starting of the multi-core processor is handed to the external host, the I _ HPI is completely controlled by the external host connected to the E _ HPI at the moment, and the mode is generally used in the system development stage.

In the system starting stage, the programmable logic circuit is used as the system main control to complete the sequential loading of the system programs, the loading sequence is as shown in fig. 3, and the automatic loading function and the code curing function as well as the BOOT function of the multi-core processor are jointly realized.

(3) Inter-core high-bandwidth data exchange functionality

This patent has proposed a scheme based on two-way Buffer, inside the programmable logic circuit, based on Buffer and an interconnection module, realize the high broadband data exchange between the core through Buffer and an interconnection module between each core and the programmable logic circuit, carry on the high-speed interconnection, as shown in fig. 2.

The interconnection module provides a mechanism for addressing and exchanging according to a packet routing protocol, provides a plurality of asynchronous read-write Buffer interfaces, and completes the connection between the interconnection module and each group of buffers and the routing forwarding function of data packets. When each processor core accesses the Buffer of the corresponding port through the corresponding memory interface or the programmable logic circuit accesses the Buffer of the corresponding port through the corresponding memory interface, the interconnection module selects the target Buffer according to the address information requested by each processor core, establishes two paths and transmits data. When a plurality of processor cores generate requests, the interconnection module forms a request queue according to the time of generating the requests, and the requests are sequentially linked and transmitted.

The Buffer provides a high-speed Buffer area for state information exchange and large data volume transmission, the routing forwarding function of data packets among a plurality of processor cores is realized, the inter-core high-broadband data exchange solves the bottleneck of inter-core high-speed and high-bandwidth large data volume transmission, and the system processing capacity is improved.

High-speed data exchange among the processors and the transfer of calculation models and parameters can be realized by using high-bandwidth data exchange among cores.

(4) Peripheral extended function

After the system is started, the programmable logic is used as external equipment of the unshared storage multi-core processor, and is provided with external expansion interfaces, such as low-speed external expansion interfaces I2C, USART, SPI, CAN, 1553B and the like, so that system function extension is realized; high-speed external expansion interfaces such as SRIO, PCIE, gigabit Ethernet and the like realize the transmission of the system and external data.

The invention has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to be construed in a limiting sense. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its embodiments without departing from the spirit and scope of the present invention, which fall within the scope of the present invention. The scope of the invention is defined by the appended claims.

Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.