阅读说明：本技术 用于执行相位控制操作的系统 (System for performing phase control operations ) 是由 崔谨镐 于 2020-09-11 设计创作，主要内容包括：一种用于执行相位控制操作的系统包括：内部时钟生成电路,其被配置成通过使时钟延迟第一延迟变量来生成内部时钟,并且通过使时钟延迟第二延迟变量来生成参考时钟,其中,内部时钟生成电路通过使时钟延迟根据内部时钟与参考时钟之间的相位差而被控制的第一延迟变量来生成内部时钟；以及数据输入/输出电路,其被配置成同步于内部时钟来输入/输出数据。(A system for performing a phase control operation comprising: an internal clock generation circuit configured to generate an internal clock by delaying the clock by a first delay variable and to generate a reference clock by delaying the clock by a second delay variable, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variable controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.)

1. A system for performing a phase control operation, comprising:

an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variable and to generate a reference clock by delaying the clock by a second delay variable, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variable controlled according to a phase difference between the internal clock and the reference clock; and

a data input/output circuit configured to input/output data in synchronization with the internal clock.

2. The system of claim 1, wherein the second delay variable is set to a delay variable that is 2N times greater than the first delay variable.

3. The system of claim 1, wherein the first delay variable and the second delay variable are set as delay variables that are changed once every time a phase difference between the internal clock and the reference clock is detected.

4. The system of claim 1, wherein the internal clock generation circuit comprises:

a divider circuit configured to generate a divided clock by dividing a frequency of the clock;

a delay amount control circuit configured to generate a target code and a reference code having a logic level combination changed by a phase detection signal in synchronization with the clock;

a target path circuit configured to have the first delay variable controlled according to a logic level combination of the target code and generate the internal clock by delaying the divided clock by the controlled first delay variable;

a reference path circuit configured to have the second delay variable controlled according to a logic level combination of the reference code and to generate the reference clock by delaying the divided clock by the controlled second delay variable; and

a detection circuit configured to generate the phase detection signal by comparing a phase of the internal clock with a phase of the reference clock.

5. The system of claim 4, wherein the delay amount control circuit comprises:

an operation control signal generation circuit configured to generate an operation control signal that is disabled by a reset signal and enabled based on the phase detection signal in synchronization with the clock;

a target code generation circuit configured to generate the target code in synchronization with the clock, the target code having a logic level combination that is changed in accordance with a logic level of the phase detection signal; and

a reference code generation circuit configured to generate the reference code having a logic level combination that is changed according to a logic level of the phase detection signal in synchronization with the clock after the operation control signal is enabled.

6. The system of claim 5, wherein the operation control signal generation circuit comprises:

a phase clock generation circuit configured to generate a phase clock that is disabled when the reset signal is input and enabled in synchronization with the clock;

a phase delay signal generation circuit configured to generate a first phase delay signal and a second phase delay signal by sequentially shifting the phase detection signal according to the phase clock; and

a latch circuit configured to generate the operation control signal, the operation control signal being disabled when the reset signal is input and enabled when the first phase delayed signal and the second phase delayed signal are different logic level combinations.

7. The system of claim 6, wherein the first and second sensors are arranged in a single unit,

wherein the phase clock is enabled in synchronization with the clock when two pulses of the clock are input after the phase clock is reset by the reset signal, an

Wherein the latch circuit generates the operation control signal that is disabled when the first phase delayed signal and the second phase delayed signal are at the same logic level combination.

8. The system of claim 5, wherein the object code generation circuitry comprises:

an internal target clock generation circuit configured to generate an internal target clock that is disabled when the reset signal is input and enabled in synchronization with the clock; and

a target code control circuit configured to generate the target code with a logic level combination counted up when the phase detection signal is at a first logic level and generate the target code with a logic level combination counted down when the phase detection signal is at a second logic level, in synchronization with the internal target clock.

9. The system of claim 8, wherein the internal target clock is enabled in synchronization with the clock when two pulses of the clock are input after the internal target clock is reset by the reset signal.

10. The system of claim 5, wherein the reference code generation circuit comprises:

an internal reference clock generation circuit configured to generate an internal reference clock that is disabled when the operation control signal is input and is enabled in synchronization with the clock; and

a reference code control circuit configured to generate the reference code with a combination of logic levels counted up when the phase detection signal is at a first logic level and generate the reference code with a combination of logic levels counted down when the phase detection signal is at a second logic level, in synchronization with the internal reference clock.

11. The system of claim 10, wherein the internal reference clock is enabled in synchronization with the clock when two pulses of the clock are input after the internal reference clock is reset by the operation control signal.

12. The system of claim 4, wherein the target path circuitry comprises:

a target delay path configured to delay the divided clock and output the delayed clock to a first node, and generate the internal clock by delaying a signal of the first node;

a first charge supply circuit comprising first and second capacitors coupled to the first and second nodes according to a logic level combination of the object code and configured to control the first delay variable of the first and second nodes according to the coupling of the first and second capacitors; and

a second charge supply circuit comprising third and fourth capacitors coupled to the first and second nodes according to a logic level combination of the object code and configured to control the first delay variable of the first and second nodes according to a coupling of the third and fourth capacitors.

13. The system of claim 12, wherein the first through fourth capacitors are selectively coupled to the first and second nodes by the object code, and the first delay variable is controlled according to a number of the first through fourth capacitors that are selectively coupled.

14. The system of claim 13, wherein the first to fourth capacitors have a first amount of charge.

15. The system of claim 4, wherein the reference path circuitry comprises:

a reference delay path configured to delay the divided clock and output the delayed clock to a third node, and generate the reference clock by delaying a signal of the third node;

a third charge supply circuit including fifth and sixth capacitors coupled to the third and fourth nodes according to a logic level combination of the reference code, and configured to control the second delay variable of the third and fourth nodes according to a coupling of the fifth and sixth capacitors; and

a fourth charge supply circuit comprising seventh and eighth capacitors coupled to the third and fourth nodes according to a logic level combination of the reference code and configured to control the second delay variable of the third and fourth nodes according to the coupling of the seventh and eighth capacitors.

16. The system of claim 15, wherein the fifth through eighth capacitors are selectively coupled to the third and fourth nodes by the reference code, and the second delay variable is controlled according to a number of the fifth through eighth capacitors that are selectively coupled.

17. The system of claim 16, wherein the fifth through eighth capacitors have a second amount of charge.

18. The system of claim 1, wherein the internal clock generation circuit generates the reference clock by delaying the clock by the second delay variable that is controlled according to a phase difference between the internal clock and the reference clock.

19. A system for performing a phase control operation, comprising:

a delay amount control circuit configured to generate first to fourth object codes and first to fourth reference codes having a combination of logic levels changed by the phase detection signal in synchronization with the clock;

a target path circuit configured to control a first delay variable according to a logic level combination of the first to fourth target codes and generate an internal clock by delaying a divided clock according to the controlled first delay variable; and

a reference path circuit configured to control a second delay variable according to a logic level combination of the first to fourth reference codes and generate a reference clock by delaying the divided clock according to the controlled second delay variable.

20. The system of claim 19, wherein the phase detection signal is enabled when the internal clock and the reference clock are out of phase.

21. The system of claim 19, wherein the second delay variable is set to a delay variable that is 2N times greater than the first delay variable.

22. The system of claim 19, wherein the first delay variable and the second delay variable are set as delay variables that are changed once every time a phase difference between the internal clock and the reference clock is detected.

23. The system of claim 19, wherein the delay amount control circuit comprises:

an operation control signal generation circuit configured to generate an operation control signal that is disabled by a reset signal and enabled based on the phase detection signal in synchronization with the clock;

a target code generation circuit configured to generate the first to fourth target codes in synchronization with the clock, the first to fourth target codes having a logic level combination that is changed in accordance with a logic level of the phase detection signal; and

a reference code generation circuit configured to generate the first to fourth reference codes having a logic level combination that is changed according to a logic level of the phase detection signal in synchronization with the clock after the operation control signal is enabled.

24. The system of claim 23, wherein the operation control signal generation circuit comprises:

a phase clock generation circuit configured to generate a phase clock that is disabled when the reset signal is input and enabled in synchronization with the clock;

a phase delay signal generation circuit configured to generate a first phase delay signal and a second phase delay signal by sequentially shifting the phase detection signal according to the phase clock; and

a latch circuit configured to generate the operation control signal, the operation control signal being disabled when the reset signal is input and enabled when the first phase delayed signal and the second phase delayed signal are different logic level combinations.

25. The system of claim 23, wherein the object code generation circuitry comprises:

an internal target clock generation circuit configured to generate an internal target clock that is disabled when the reset signal is input and enabled in synchronization with the clock; and

a target code control circuit configured to generate the first to fourth target codes having a logic level combination counted up when the phase detection signal is at a first logic level and generate the first to fourth target codes having a logic level combination counted down when the phase detection signal is at a second logic level in synchronization with the internal target clock.

26. The system of claim 23, wherein the reference code generation circuit comprises:

an internal reference clock generation circuit configured to generate an internal reference clock that is disabled when the operation control signal is input and is enabled in synchronization with the clock; and

a reference code control circuit configured to generate the first to fourth reference codes having a logic level combination counted up when the phase detection signal is at a first logic level and generate the first to fourth reference codes having a logic level combination counted down when the phase detection signal is at a second logic level in synchronization with the internal reference clock.

27. The system of claim 19, wherein the target path circuitry comprises:

a target delay path configured to delay the divided clock and output the delayed clock to a first node, and generate the internal clock by delaying a signal of the first node;

a first charge supply circuit including first to fourth capacitors coupled to the first and second nodes according to logic level combinations of the first to fourth target codes, and configured to control the first delay variable of the first and second nodes according to the coupling of the first to fourth capacitors; and

a second charge supply circuit including fifth to eighth capacitors coupled to the first and second nodes according to a logic level combination of the first to fourth object codes, and configured to control the first delay variable of the first and second nodes according to a coupling of the fifth to eighth capacitors.

28. The system of claim 27, wherein the first to eighth capacitors have a first amount of charge.

29. The system of claim 19, wherein the reference path circuitry comprises:

a reference delay path configured to delay the divided clock and output the delayed clock to a third node, and generate the reference clock by delaying a signal of the third node;

a third charge supply circuit including ninth to twelfth capacitors coupled to the third and fourth nodes according to logic level combinations of the first to fourth reference codes, and configured to control the second delay variable of the third and fourth nodes according to coupling of the ninth to twelfth capacitors; and

a fourth charge supply circuit including thirteenth to sixteenth capacitors coupled to the third and fourth nodes according to logic level combinations of the first to fourth reference codes, and configured to control the second delay variable of the third and fourth nodes according to coupling of the thirteenth to sixteenth capacitors.

30. The system of claim 29, wherein the ninth through sixteenth capacitors have a second amount of charge.

31. A system for performing a phase control operation, comprising:

an internal clock generation circuit configured to generate an internal clock by delaying a clock through a target path circuit, generate a reference clock by delaying the clock through a reference path circuit, and control a second delay variable of the reference path circuit after controlling a first delay variable of the target path circuit according to a phase difference between the internal clock and the reference clock; and

a data input/output circuit configured to input and output data in synchronization with the internal clock.

Technical Field

Embodiments are generally directed to a system for performing a phase control operation to control a phase of an internal clock according to PVT (process voltage temperature) variations.

Background

Recently, as the operating speed of semiconductor systems increases, high transfer rates between semiconductor devices included in the semiconductor systems are required. In order to satisfy a high transmission rate or a high bandwidth of data serially input/output between semiconductor devices, a new technique is applied. For example, a clock division technique is used to input/output data at high speed. When the frequency of the clock is divided, internal clocks having different phases are generated. The semiconductor system deserializes or serializes data using an internal clock and inputs/outputs data at high speed.

When the internal PVT variation of the semiconductor system occurs, the internal clock whose frequency is divided and the clock inputted from the outside become out of phase, causing an operation error of the semiconductor system. Accordingly, various methods for compensating for such PVT variations are proposed.

Disclosure of Invention

In one embodiment, a system for performing a phase control operation may comprise: an internal clock generation circuit configured to generate an internal clock by delaying the clock by a first delay variable (delay), and to generate a reference clock by delaying the clock by a second delay variable, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variable controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.

In one embodiment, a system for performing a phase control operation may comprise: a delay amount control circuit configured to generate first to fourth object codes and first to fourth reference codes having a combination of logic levels changed by the phase detection signal in synchronization with the clock; a target path circuit configured to control a first delay variable according to a logic level combination of the first to fourth target codes and generate an internal clock by delaying the divided clock according to the controlled first delay variable; and a reference path circuit configured to control a second delay variable according to a logic level combination of the first to fourth reference codes and generate a reference clock by delaying the divided clock according to the controlled second delay variable.

Drawings

Fig. 1 is a block diagram showing a configuration of a system for performing a phase control operation according to an embodiment.

Fig. 2 is a block diagram showing a configuration of a semiconductor device included in the system for performing a phase control operation shown in fig. 1.

Fig. 3 is a block diagram showing a configuration of a control circuit included in the semiconductor device shown in fig. 2.

Fig. 4 is a block diagram showing a configuration of an internal clock generation circuit included in the semiconductor device shown in fig. 2.

Fig. 5 is a block diagram showing a configuration of a delay amount control circuit included in the internal clock generation circuit shown in fig. 4.

Fig. 6 is a diagram showing a configuration of an operation control signal generation circuit included in the delay amount control circuit shown in fig. 5.

Fig. 7 is a diagram showing a configuration of an object code generating circuit included in the delay amount control circuit shown in fig. 5.

Fig. 8 is a diagram showing a configuration of a reference code generating circuit included in the delay amount control circuit shown in fig. 5.

Fig. 9 is a circuit diagram showing a configuration of a target path circuit included in the internal clock generation circuit shown in fig. 4.

Fig. 10 is a circuit diagram showing a configuration of a reference path circuit included in the internal clock generation circuit shown in fig. 4.

Fig. 11 is a timing diagram for describing the operation of a system for performing a phase control operation according to one embodiment.

Fig. 12 is a diagram illustrating a configuration of an electronic system to which the system for performing a phase control operation illustrated in fig. 1 to 11 is applied according to an embodiment.

Detailed Description

When a parameter is used in a process or algorithm, the term "preset" indicates that the value of the parameter is predetermined. According to one embodiment, the parameter values may be set at the beginning of a process or algorithm or may be set while the process or algorithm is being executed.

Terms such as "first" and "second" are used to distinguish between various components and are not limited by these components. For example, a first component can be referred to as a second component and vice versa.

When one element is referred to as being "coupled" or "connected" to another element, it may be indicated that the elements are directly coupled or connected to each other or are coupled or connected to each other through another element interposed therebetween. On the other hand, when one element is referred to as being "directly coupled" or "directly connected" to another element, it may indicate that the elements are directly coupled or connected to each other without another element interposed therebetween.

"logic high level" and "logic low level" are used to describe the logic levels of a signal. A signal having a "logic high level" is distinguished from a signal having a "logic low level". For example, when the signal having the first voltage corresponds to a "logic high level", the signal having the second voltage may correspond to a "logic low level". According to one embodiment, the "logic high level" may be set to a voltage higher than the "logic low level". According to one embodiment, the logic levels of the signals may be set to different logic levels or opposite logic levels. For example, according to one embodiment, a signal having a logic high level may be set to have a logic low level, and according to one embodiment, a signal having a logic low level may be set to have a logic high level.

Hereinafter, the present disclosure will be described in more detail by embodiments. The embodiments are merely illustrative of the present disclosure, and the scope of the present disclosure is not limited by the embodiments.

Embodiments may relate to a system for performing a phase control operation capable of controlling a phase of an internal clock by differently controlling delay variables for different paths according to PVT variations.

According to an embodiment of the present disclosure, the system may control the phase of the internal clock by controlling the delay variable for different paths in different ways according to PVT variations.

In addition, the system can input/output data by compensating the phase of the internal clock according to PVT variation, thereby preventing an operation error.

As shown in fig. 1, a system 1 for performing a phase control operation according to one embodiment may include a controller 110 and a semiconductor device 120. The semiconductor device 120 may include a control circuit 201, an internal clock generation circuit 203, a data input/output circuit 205, and a core circuit 207.

The controller 110 may include a first control pin 11, a second control pin 31, a third control pin 51, and a fourth control pin 71. The semiconductor device 120 may include a first semiconductor pin 21, a second semiconductor pin 41, a third semiconductor pin 61, and a fourth semiconductor pin 81. The first transmission line L11 may be coupled between the first control pin 11 and the first semiconductor pin 21. The second transmission line L31 may be coupled between the second control pin 31 and the second semiconductor pin 41. The third transmission line L51 may be coupled between the third control pin 51 and the third semiconductor pin 61. The fourth transmission line L71 may be coupled between the fourth control pin 71 and the fourth semiconductor pin 81. The controller 110 may transmit the clock CLK to the semiconductor device 120 through the first transmission line L11 in order to control the semiconductor device 120. The controller 110 may transmit a command CMD to the semiconductor device 120 through the second transmission line L31 in order to control the semiconductor device 120. The controller 110 may transmit the address ADD to the semiconductor device 120 through the third transmission line L51 in order to control the semiconductor device 120. The controller 110 and the semiconductor device 120 may transmit and receive DATA through the fourth transmission line L71.

The controller 110 may output a clock CLK, a command CMD, an address ADD, and DATA to the semiconductor device 120 to perform a normal operation. The normal operation may include a write operation and a read operation of the semiconductor device 120. The command CMD, the address ADD, and the DATA may be sequentially output in synchronization with the odd or even pulses included in the clock CLK.

The control circuit 201 can control a normal operation according to the command CMD and the address ADD in synchronization with the clock CLK.

The internal clock generation circuit 203 may perform a phase control operation of controlling the phase of the internal clock (ICLK of fig. 2) in order to control the input/output time point of the DATA during a normal operation.

The DATA input/output circuit 205 may input/output the DATA in synchronization with the internal clock (ICLK of fig. 2).

The core circuit 207 can perform a write operation and a read operation according to the clock CLK, the command CMD, the address ADD, and the DATA.

Fig. 2 is a block diagram showing the configuration of the semiconductor device 120 according to an embodiment. As shown in fig. 2, the semiconductor device 120 may include a control circuit 201, an internal clock generation circuit 203, a data input/output circuit 205, and a core circuit 207.

The control circuit 201 may generate the write signal WT, the read signal RD, and the internal address IADD <1: N > for controlling a normal operation according to the command CMD <1: L > and the address ADD <1: M > in synchronization with the clock CLK. The control circuit 201 can generate the write signal WT for performing the write operation by decoding the command CMD <1: L > in synchronization with the clock CLK. The control circuit 201 can generate a read signal RD for performing a read operation by decoding the command CMD <1: L > in synchronization with the clock CLK. The control circuit 201 can generate the internal addresses IADD <1: N > for performing the write operation and the read operation by decoding the addresses ADD <1: M > in synchronization with the clock CLK. The number of bits "L" included in the command CMD <1: L > may be set to various values according to embodiments. The number of bits "M" included in the address ADD <1: M > can be set to various values according to embodiments. The number of bits "N" included in the internal address IADD <1: N > may be set to various values according to embodiments. The operation of the control circuit 201 to generate the write signal WT, the read signal RD, and the internal address IADD <1: N > will be described with reference to fig. 3, which will be described below.

The internal clock generation circuit 203 can generate the internal clock ICLK by controlling the phase of the clock CLK. The internal clock generation circuit 203 may control a first delay control amount and a second delay control amount for delaying the clock CLK. The internal clock generation circuit 203 may generate the internal clock ICLK by delaying the clock CLK according to the controlled first delay control amount and second delay control amount. The operation of the internal clock generation circuit 203 in which the internal clock generation circuit 203 controls the first delay control amount and the second delay control amount for delaying the clock CLK will be described with reference to fig. 4 to 11.

The DATA input/output circuit 205 may input/output the DATA in synchronization with the internal clock ICLK. The DATA input/output circuit 205 may receive the DATA output from the controller 110 and generate the internal DATA ID in synchronization with the internal clock ICLK during the write operation. The DATA input/output circuit 205 may receive the internal DATA ID output from the core circuit 207 and generate the DATA in synchronization with the internal clock ICLK during a read operation. The DATA input/output circuit 205 may output the DATA to the controller 110 during a read operation.

The core circuit 207 may be implemented as a plurality of memory cells. The core circuit 207 may store the internal data ID according to the write signal WT and the internal address IADD <1: N > that are enabled during the write operation. The core circuit 207 may output the internal data ID stored therein according to the enabled read signal RD and the internal address IADD <1: N > during a read operation.

Fig. 3 is a block diagram showing the configuration of the control circuit 201 according to one embodiment. As shown in fig. 3, the control circuit 201 may include a command decoder 211 and an internal address generation circuit 212.

The command decoder 211 may generate the write signal WT and the read signal RD that are selectively enabled by decoding the commands CMD <1: L > in synchronization with the clock CLK. The command decoder 211 may generate a write signal WT for performing a write operation by decoding the command CMD <1: L > in synchronization with the clock CLK. The command decoder 211 may generate a read signal RD for performing a read operation by decoding the command CMD <1: L > in synchronization with the clock CLK.

The internal address generation circuit 212 can generate the internal address IADD <1: N > by decoding the address ADD <1: M > in synchronization with the clock CLK. The internal address generation circuit 212 can generate internal addresses IADD <1: N > for performing a write operation and a read operation by decoding the addresses ADD <1: M > in synchronization with the clock CLK.

Fig. 4 is a block diagram showing the configuration of the internal clock generation circuit 203 according to an embodiment. As shown in fig. 4, the internal clock generation circuit 203 may include a frequency divider circuit 221, a delay amount control circuit 222, a target path circuit 223, a reference path circuit 224, and a detection circuit 225.

The frequency divider circuit 221 may generate the divided clock DCLK by dividing the frequency of the clock CLK. The frequency divider circuit 221 may generate a divided clock DCLK having a frequency corresponding to 1/2 of the frequency of the clock CLK in synchronization with the clock CLK.

The delay amount control circuit 222 may generate the first through fourth object codes TCD <1:4> having logic level combinations changed by the phase detection signal PD _ INF in synchronization with the clock CLK. The delay amount control circuit 222 may generate the first to fourth reference codes RCD <1:4> having logic level combinations changed by the phase detection signal PD _ INF in synchronization with the clock CLK. The delay amount control circuit 222 may generate the first to fourth reference codes RCD <1:4> having a logic level combination changed by the phase detection signal PD _ INF after generating the first to fourth object codes TCD <1:4> in synchronization with the clock CLK. The priorities of generating the first through fourth object codes TCD <1:4> and the first through fourth reference codes RCD <1:4> may be set in various ways according to embodiments.

The target path circuit 223 may generate the internal clock ICLK by delaying the divided clock DCLK. The target path circuit 223 may have a first delay variable controlled according to a logic level combination of the first to fourth target codes TCD <1:4 >. The target path circuit 223 may generate the internal clock ICLK by delaying the frequency-divided clock DCLK according to the controlled first delay variable.

The reference path circuit 224 may generate the reference clock RCLK by delaying the divided clock DCLK. The reference path circuit 224 may have a second delay variable controlled according to a logic level combination of the first to fourth reference codes RCD <1:4 >. The reference path circuit 224 may generate the reference clock RCLK by delaying the divided clock DCLK according to the controlled second delay variable.

The detection circuit 225 may generate the phase detection signal PD _ INF according to a phase difference between the internal clock ICLK and the reference clock RCLK. The detection circuit 225 may generate the phase detection signal PD _ INF by comparing the phase of the internal clock ICLK with the phase of the reference clock RCLK. The detection circuit 225 may generate the phase detection signal PD _ INF that is enabled when the internal clock ICLK and the reference clock RCLK are out of phase. The logic level of the enabled phase detection signal PD _ INF may be set to various logic levels according to embodiments. For example, the logic level to which the phase detection signal PD _ INF is enabled may be set to the first logic level (logic high level). The logic level to which the phase detection signal PD _ INF is disabled may be set to the second logic level (logic low level).

Fig. 5 is a block diagram showing the configuration of the delay amount control circuit 222 according to an embodiment. As shown in fig. 5, the delay amount control circuit 222 may include an operation control signal generation circuit 231, an object code generation circuit 232, and a reference code generation circuit 233.

The operation control signal generation circuit 231 may generate the operation control signal LC _ CTR that is disabled by the reset signal RST. The operation control signal generation circuit 231 may generate the operation control signal LC _ CTR enabled based on the phase detection signal PD _ INF in synchronization with the clock CLK.

The object code generating circuit 232 may generate the first to fourth object codes TCD <1:4> having the logic level combination changed according to the logic level of the phase detection signal PD _ INF in synchronization with the clock CLK. The object code generation circuit 232 may generate the first to fourth object codes TCD <1:4> which are counted up (up-count) when the phase detection signal PD _ INF is enabled in synchronization with the clock CLK. The object code generation circuit 232 may generate the first to fourth object codes TCD <1:4> which are counted down (down-count) while the phase detection signal PD _ INF is disabled in synchronization with the clock CLK.

After the operation control signal LC _ CTR is enabled, the reference code generation circuit 233 may generate the first to fourth reference codes RCD <1:4> having a logic level combination that is changed according to the logic level of the phase detection signal PD _ INF in synchronization with the clock CLK. After the operation control signal LC _ CTR is enabled, the reference code generation circuit 233 may generate the first to fourth reference codes RCD <1:4> counted up while the phase detection signal PD _ INF is enabled in synchronization with the clock CLK. After the operation control signal LC _ CTR is enabled, the reference code generation circuit 233 may generate the first to fourth reference codes RCD <1:4> counted down while the phase detection signal PD _ INF is disabled in synchronization with the clock CLK.

Fig. 6 is a diagram showing the configuration of the operation control signal generation circuit 231 according to an embodiment. As shown in fig. 6, the operation control signal generation circuit 231 may include a phase clock generation circuit 231_1, a phase delay signal generation circuit 231_2, and a latch circuit 231_ 3.

The phase clock generation circuit 231_1 may be implemented using counters 241_1 and 241_ 2.

The counter 241_1 may generate the first count signal CNT <1> disabled to a logic low level by the reset signal RST. The counter 241_1 may generate the first count signal CNT <1> that is enabled to a logic high level when the pulse of the clock CLK transitions from a logic high level to a logic low level. The counter 241_2 may generate the phase clock PDCK that is disabled to a logic low level by the reset signal RST. The counter 241_2 may generate the phase clock PDCK that is enabled to a logic high level when the pulse of the first count signal CNT <1> transitions from a logic high level to a logic low level.

The phase clock generation circuit 231_1 may generate the phase clock PDCK that is disabled by the reset signal RST. The phase clock generation circuit 231_1 may generate a phase clock PDCK that is enabled in synchronization with the clock CLK. The phase clock generation circuit 231_1 may generate the phase clock PDCK that is reset by the reset signal RST and then enabled when two pulses of the clock CLK are input after the phase clock PDCK is reset by the reset signal RST.

The phase delay signal generation circuit 231_2 may be implemented using flip-flops 242_1 and 242_ 2.

The flip-flop 242_1 may generate the first phase delay signal PD <1> by shifting the phase detection signal PD _ INF in synchronization with the phase clock PDCK. The flip-flop 242_2 may generate the second phase delay signal PD <2> by shifting the first phase delay signal PD <1> in synchronization with the phase clock PDCK.

The phase delay signal generation circuit 231_2 may generate the first phase delay signal PD <1> and the second phase delay signal PD <2> that are sequentially enabled by shifting the phase detection signal PD _ INF in synchronization with the phase clock PDCK.

The latch circuit 231_3 may include an inverter 243_1, an exclusive or (XOR) gate 243_2, and NAND (NAND) gates 243_3 and 243_ 4.

When the reset signal RST is input at a logic high level, the latch circuit 231_3 may generate the operation control signal LC _ CTR disabled to a logic low level. When the first phase delay signal PD <1> and the second phase delay signal PD <2> are at different logic levels, the latch circuit 231_3 may generate the operation control signal LC _ CTR enabled to a logic high level. When the first phase delay signal PD <1> and the second phase delay signal PD <2> are at the same logic level, the latch circuit 231_3 may generate the operation control signal LC _ CTR disabled to a logic low level. In one embodiment, the latch circuit 231_3 may generate the operation control signal LC _ CTR that is disabled when the reset signal RST is input and enabled when the first phase delay signal PD <1> and the second phase delay signal PD <2> are at different logic level combinations.

Fig. 7 is a diagram showing the configuration of the object code generation circuit 232 according to one embodiment. As shown in fig. 7, the object code generation circuit 232 may include an internal object clock generation circuit 232_1 and an object code control circuit 232_ 2.

The internal target clock generation circuit 232_1 may be implemented using counters 251_1 and 251_ 2.

The counter 251_1 may generate the first transmission signal TS <1> disabled to a logic low level by the reset signal RST. When the pulse of the clock CLK transitions from a logic high level to a logic low level, the counter 251_1 may generate the first transmission signal TS <1> enabled to a logic high level. The counter 251_2 may generate the internal target clock ITCK disabled to a logic low level by the reset signal RST. When the pulse of the first transmission signal TS <1> transitions from a logic high level to a logic low level, the counter 251_2 may generate the internal target clock ITCK that is enabled to a logic high level.

The internal target clock generation circuit 232_1 can generate the internal target clock ITCK that is disabled by the reset signal RST. The internal target clock generation circuit 232_1 may generate an internal target clock ITCK that is enabled in synchronization with the clock CLK. The internal target clock generation circuit 232_1 may generate the internal target clock ITCK that is enabled when two pulses of the clock CLK are input after the internal target clock ITCK is reset by the reset signal RST.

The object code control circuit 232_2 may include a flip-flop 252_1, an inverter 252_2, an adder 252_3, a subtractor 252_4, delay circuits 252_5 to 252_8, a selection transmitter 252_9, and a flip-flop 252_ 10.

The flip-flop 252_1 may output the phase detection signal PD _ INF as the target delay signal TGD in synchronization with the internal target clock ITCK. When the pulse of the internal target clock ITCK is input at a logic high level, the flip-flop 252_1 may output the phase detection signal PD _ INF as the target delay signal TGD.

The inverter 252_2 may invert and buffer the target delay signal TGD and output the buffered signal.

The adder 252_3 may generate the first to fourth target addition codes TCP <1:4> by counting up the first to fourth target codes TCD <1:4> according to a logic level of the target delay signal TGD. The adder 252_3 may generate the first to fourth target addition codes TCP <1:4> by sequentially counting up the first to fourth target codes TCD <1:4> when the target delay signal TGD is at a logic high level.

The subtractor 252_4 may generate the first to fourth target subtraction codes TCM <1:4> by down-counting the first to fourth target codes TCD <1:4> according to the logic level of the output signal of the inverter 252_ 2. The subtractor 252_4 may generate the first to fourth target subtraction codes TCM <1:4> by sequentially counting down the first to fourth target codes TCD <1:4> while the output signal of the inverter 252_2 is at a logic low level. That is, the subtractor 252_4 may generate the first to fourth target subtraction codes TCM <1:4> by sequentially counting down the first to fourth target codes TCD <1:4> when the target delay signal TGD is at a logic high level.

The delay circuits 252_5 to 252_8 may be implemented as inverter chains. The delay circuits 252_5 to 252_8 may generate the target selection signal TSEL by delaying the output signal of the inverter 252_ 2.

The selection transmitter 252_9 may output any one of the first to fourth target addition codes TCP <1:4> and the first to fourth target subtraction codes TCM <1:4> as the first to fourth target selection codes TSC <1:4> according to a logic level of the target selection signal TSEL. When the target select signal TSEL is at a logic low level, the selection transmitter 252_9 may output the first to fourth target addition codes TCP <1:4> as the first to fourth target selection codes TSC <1:4 >. When the target select signal TSEL is at a logic high level, the select transmitter 252_9 may output the first to fourth target subtraction codes TCM <1:4> as the first to fourth target selection codes TSC <1:4 >.

The flip-flop 252_10 may output the first through fourth target selection codes TSC <1:4> as the first through fourth target codes TCD <1:4> in synchronization with the internal target clock ITCK. When the pulses of the internal target clock ITCK are input at a logic high level, the flip-flop 252_10 may output the first to fourth target selection codes TSC <1:4> as the first to fourth target codes TCD <1:4 >. Fig. 7 shows the flip-flop 252_10 as one flip-flop, but the flip-flop 252_10 may be implemented as four flip-flops for generating the first through fourth object codes TCD <1:4 >.

Fig. 8 is a diagram showing the configuration of the reference code generating circuit 233 according to one embodiment. As shown in fig. 8, the reference code generation circuit 233 may include an internal reference clock generation circuit 233_1 and a reference code control circuit 233_ 2.

The internal reference clock generation circuit 233_1 can be implemented using counters 261_1 and 261_ 2.

The counter 261_1 may generate the second transfer signal TS <2> disabled to a logic low level by the operation control signal LC _ CTR. When the pulse of the clock CLK transitions from a logic high level to a logic low level, the counter 261_1 may generate the second transfer signal TS <2> enabled to a logic high level. The counter 261_2 may generate the internal reference clock IRCK disabled to a logic low level by the operation control signal LC _ CTR. When the pulse of the second transfer signal TS <2> transitions from a logic high level to a logic low level, the counter 261_2 may generate the internal reference clock IRCK that is enabled to a logic high level.

The internal reference clock generation circuit 233_1 can generate the internal reference clock IRCK that is disabled by the operation control signal LC _ CTR. The internal reference clock generation circuit 233_1 can generate an internal reference clock IRCK that is enabled in synchronization with the clock CLK. The internal reference clock generation circuit 233_1 may generate the internal reference clock IRCK that is enabled after the internal reference clock IRCK is reset by the operation control signal LC _ CTR and then two pulses of the clock CLK are input after the internal reference clock IRCK is reset by the operation control signal LC _ CTR.

The reference code control circuit 233_2 may include a flip-flop 262_1, an inverter 262_2, an adder 262_3, a subtractor 262_4, delay circuits 262_5 to 262_8, a selection transmitter 262_9, and a flip-flop 262_ 10.

The flip-flop 262_1 may output the phase detection signal PD _ INF as the reference delay signal RFD in synchronization with the internal reference clock IRCK. When the pulse of the internal reference clock IRCK is input at a logic high level, the flip-flop 262_1 may output the phase detection signal PD _ INF as the reference delay signal RFD.

The inverter 262_2 may invert and buffer the reference delayed signal RFD and output the buffered signal.

The adder 262_3 may generate the first to fourth reference-addition codes RCP <1:4> by counting up the first to fourth reference codes RCD <1:4> according to a logic level of the reference delay signal RFD. The adder 262_3 may generate the first to fourth reference-addition codes RCP <1:4> by sequentially counting up the first to fourth reference codes RCD <1:4> when the reference delay signal RFD is at a logic high level.

The subtractor 262_4 may generate the first to fourth reference subtraction codes RCM <1:4> by counting down the first to fourth reference codes RCD <1:4> according to the logic level of the output signal of the inverter 262_ 2. The subtractor 262_4 may generate the first to fourth reference subtraction codes RCM <1:4> by sequentially counting down the first to fourth reference codes RCD <1:4> when the output signal of the inverter 262_2 is at a logic low level. That is, the subtracter 262_4 may generate the first to fourth reference subtraction codes RCM <1:4> by sequentially counting down the first to fourth reference codes RCD <1:4> when the reference delay signal RFD is at a logic high level.

The delay circuits 262_5 to 262_8 may be implemented as inverter chains. The delay circuits 262_5 to 262_8 may generate the reference selection signal RSEL by delaying the output signal of the inverter 262_ 2.

The selection transmitter 262_9 may output any one set of the first to fourth reference addition codes RCP <1:4> and the first to fourth reference subtraction codes RCM <1:4> as the first to fourth reference selection codes RSC <1:4> according to a logic level of the reference selection signal RSEL. When the reference selection signal RSEL is at a logic low level, the selection transmitter 262_9 may output the first to fourth reference addition codes RCP <1:4> as the first to fourth reference selection codes RSC <1:4 >. When the reference selection signal RSEL is at a logic high level, the selection transmitter 262_9 may output the first to fourth reference subtraction codes RCM <1:4> as the first to fourth reference selection codes RSC <1:4 >.

The flip-flop 262_10 may output the first to fourth reference selection codes RSC <1:4> as the first to fourth reference codes RCD <1:4> in synchronization with the internal reference clock IRCK. When the pulse of the internal reference clock IRCK is input at a logic high level, the flip-flop 262_10 may output the first to fourth reference selection codes RSC <1:4> as the first to fourth reference codes RCD <1:4 >. Fig. 8 shows the flip-flop 262_10 as one flip-flop, but the flip-flop 262_10 may be implemented as four flip-flops for generating the first to fourth reference codes RCD <1:4 >.

Fig. 9 is a circuit diagram showing the configuration of the target path circuit 223 according to an embodiment. As shown in fig. 9, the target path circuit 223 may include a target delay path 271, a first charge supply circuit 272, and a second charge supply circuit 273.

The target delay path 271 may include inverters 271_1 to 271_ 6.

The inverters 271_1 and 271_2 may buffer the divided clock DCKL and output the buffered clock to the first node nd 21. The inverters 271_1 and 271_2 may delay the divided clock DCKL and output the delayed clock to the first node nd 21.

The inverters 271_3 and 271_4 may buffer the signal of the first node nd21 and output the buffered signal to the second node nd 22. The inverters 271_3 and 271_4 may delay the signal of the first node nd21 and output the delayed signal to the second node nd 22.

The inverters 271_5 and 271_6 may buffer the signal of the second node nd22 and output the buffered signal as the internal clock ICLK. The inverters 271_5 and 271_6 may delay the signal of the second node nd22 and output the delayed signal as the internal clock ICLK.

The target delay path 271 may generate the internal clock ICLK by delaying the divided clock DCKL.

The first charge supply circuit 272 may be implemented as NMOS transistors 272_1, 272_3, 272_5, and 272_7 and PMOS capacitors 272_2, 272_4, 272_6, and 272_ 8.

The NMOS transistor 272_1 and the PMOS capacitor 272_2 may be coupled in series between the first node nd21 and the supply voltage VDD. When the first target code signal TCD <1> is at a logic high level, the NMOS transistor 272_1 may be turned on. When the NMOS transistor 272_1 is turned on, the PMOS capacitor 272_2 may be coupled to the first node nd21 and supply a charge.

The NMOS transistor 272_3 and the PMOS capacitor 272_4 may be coupled in series between the first node nd21 and the supply voltage VDD. When the second target code signal TCD <2> is at a logic high level, the NMOS transistor 272_3 may be turned on. When the NMOS transistor 272_3 is turned on, the PMOS capacitor 272_4 may be coupled to the first node nd21 and supply a charge.

The NMOS transistor 272_5 and the PMOS capacitor 272_6 may be coupled in series between the second node nd22 and the supply voltage VDD. When the third target code signal TCD <3> is at a logic high level, the NMOS transistor 272_5 may be turned on. When the NMOS transistor 272_1 is turned on, the PMOS capacitor 272_6 may be coupled to the second node nd22 and supply charges.

The NMOS transistor 272_7 and the PMOS capacitor 272_8 may be coupled in series between the second node nd22 and the supply voltage VDD. When the fourth target code signal TCD <4> is at a logic high level, the NMOS transistor 272_7 may be turned on. When the NMOS transistor 272_7 is turned on, the PMOS capacitor 272_8 may be coupled to the second node nd22 and supply a charge.

The first charge supply circuit 272 may include PMOS capacitors 272_2, 272_4, 272_6, and 272_8 coupled to the first node nd21 and the second node nd22 according to a logic level combination of the first through fourth object codes TCD <1:4 >. The first charge supply circuit 272 may control the first delay variable of the first node nd21 and the second node nd22 according to the coupling of the PMOS capacitors 272_2, 272_4, 272_6, and 272_ 8.

The second charge supply circuit 273 may be implemented as NMOS transistors 273_1, 273_3, 273_5, and 273_7 and NMOS capacitors 273_2, 273_4, 273_6, and 273_ 8.

The NMOS transistor 273_1 and the NMOS capacitor 273_2 may be coupled in series between the first node nd21 and the ground voltage VSS. When the first target code signal TCD <1> is at a logic high level, the NMOS transistor 273_1 may be turned on. When the NMOS transistor 273_1 is turned on, the NMOS capacitor 273_2 may be coupled to the first node nd21 and supply charge.

The NMOS transistor 273_3 and the NMOS capacitor 273_4 may be coupled in series between the first node nd21 and the ground voltage VSS. When the second target code signal TCD <2> is at a logic high level, the NMOS transistor 273_3 may be turned on. When the NMOS transistor 273_3 is turned on, the NMOS capacitor 273_4 may be coupled to the first node nd21 and supply charge.

The NMOS transistor 273_5 and the NMOS capacitor 273_6 may be coupled in series between the second node nd22 and the ground voltage VSS. When the third target code signal TCD <3> is at a logic high level, the NMOS transistor 273_5 may be turned on. When the NMOS transistor 273_1 is turned on, the NMOS capacitor 273_6 may be coupled to the second node nd22 and supply charge.

The NMOS transistor 273_7 and the NMOS capacitor 273_8 may be coupled in series between the second node nd22 and the ground voltage VSS. When the fourth target code signal TCD <4> is at a logic high level, the NMOS transistor 273_7 may be turned on. When the NMOS transistor 273_7 is turned on, the NMOS capacitor 273_8 may be coupled to the second node nd22 and supply charge.

The second charge supplying circuit 273 may include NMOS capacitors 273_2, 273_4, 273_6, and 273_8 coupled to the first node nd21 and the second node nd22 according to logic level combinations of the first through fourth object codes TCD <1:4 >. The second charge supplying circuit 273 may control the first delay variable of the first node nd21 and the second node nd22 according to the coupling of the NMOS capacitors 273_2, 273_4, 273_6, and 273_ 8.

The first delay variable may be controlled according to the number of PMOS capacitors 272_2, 272_4, 272_6, and 272_8 and NMOS capacitors 273_2, 273_4, 273_6, and 273_ 8. The first delay variable may be controlled by the amount of charge of the PMOS capacitors 272_2, 272_4, 272_6, and 272_8 and the NMOS capacitors 273_2, 273_4, 273_6, and 273_ 8. The delay variable by which the first delay variable is changed once may be set to 5 ps. For example, when the first through fourth object codes TCD <1:4> are counted down once, the first delay variable may be decreased by 5 ps.

The charge amount of the PMOS capacitors 272_2, 272_4, 272_6, and 272_8 can be determined according to the aspect ratio. The width-to-length ratio of the PMOS capacitors 272_2 and 272_6 may be set to 2/1, and the width-to-length ratio of the PMOS capacitors 272_4 and 272_8 may be set to 2/2. The aspect ratios of the PMOS capacitors 272_2, 272_4, 272_6, and 272_8 may be set to various ratios according to embodiments.

The charge amount of the NMOS capacitors 273_2, 273_4, 273_6, and 273_8 can be determined according to the width-to-length ratio. The width-to-length ratio of the NMOS capacitors 273_2 and 273_6 may be set to 1/1, and the width-to-length ratio of the NMOS capacitors 273_4 and 273_8 may be set to 1/2. The width-to-length ratios of the NMOS capacitors 273_2, 273_4, 273_6, and 273_8 may be set to various ratios according to embodiments.

Fig. 10 is a circuit diagram illustrating a configuration of the reference path circuit 224 according to an embodiment. As shown in fig. 10, the reference path circuit 224 may include a reference delay path 281, a third charge supply circuit 282, and a fourth charge supply circuit 283.

The reference delay path 281 may include inverters 281_1 to 281_ 6.

The inverters 281_1 and 281_2 may buffer the division clock DCKL and output the buffered clock to the third node nd 23. The inverters 281_1 and 281_2 may delay the division clock DCKL and output the delayed clock to the third node nd 23.

The inverters 281_3 and 281_4 may buffer a signal of the third node nd23 and output the buffered signal to the fourth node nd 24. The inverters 281_3 and 281_4 may delay a signal of the third node nd23 and output the delayed signal to the fourth node nd 24.

The inverters 281_5 and 281_6 may buffer a signal of the fourth node nd24 and output the buffered signal as the reference clock RCLK. The inverters 281_5 and 281_6 may delay the signal of the fourth node nd24 and output the delayed signal as the reference clock RCLK.

The reference delay path 281 may generate the reference clock RCLK by delaying the divided clock DCKL.

The third charge supply circuit 282 may be implemented as NMOS transistors 282_1, 282_3, 282_5, and 282_7 and PMOS capacitors 282_2, 282_4, 282_6, and 282_ 8.

The NMOS transistor 282_1 and the PMOS capacitor 282_2 may be coupled in series between the third node nd23 and the supply voltage VDD. When the first reference code signal RCD <1> is at a logic high level, the NMOS transistor 282_1 may be turned on. When the NMOS transistor 282_1 is turned on, the PMOS capacitor 282_2 may be coupled to the third node nd23 and supply a charge.

The NMOS transistor 282_3 and the PMOS capacitor 282_4 may be coupled in series between the third node nd23 and the supply voltage VDD. When the second reference code signal RCD <2> is at a logic high level, the NMOS transistor 282_3 may be turned on. When the NMOS transistor 282_3 is turned on, the PMOS capacitor 282_4 may be coupled to the third node nd23 and supply a charge.

The NMOS transistor 282_5 and the PMOS capacitor 282_6 may be coupled in series between the fourth node nd24 and the supply voltage VDD. When the third reference code signal RCD <3> is at a logic high level, the NMOS transistor 282_5 may be turned on. When the NMOS transistor 282_1 is turned on, the PMOS capacitor 282_6 may be coupled to the fourth node nd24 and supply a charge.

The NMOS transistor 282_7 and the PMOS capacitor 282_8 may be coupled in series between the fourth node nd24 and the supply voltage VDD. When the fourth reference code signal RCD <4> is at a logic high level, the NMOS transistor 282_7 may be turned on. When the NMOS transistor 282_7 is turned on, the PMOS capacitor 282_8 may be coupled to the fourth node nd24 and supply a charge.

The third charge supplying circuit 282 may include PMOS capacitors 282_2, 282_4, 282_6, and 282_8 coupled to the third node nd23 and the fourth node nd24 according to a logic level combination of the first to fourth reference codes RCD <1:4 >. The third charge supply circuit 282 may control the second delay variable of the third node nd23 and the fourth node nd24 according to the coupling of the PMOS capacitors 282_2, 282_4, 282_6, and 282_ 8.

The fourth charge supplying circuit 283 may be implemented as NMOS transistors 283_1, 283_3, 283_5, and 283_7 and NMOS capacitors 283_2, 283_4, 283_6, and 283_ 8.

The NMOS transistor 283_1 and the NMOS capacitor 283_2 may be coupled in series between the third node nd23 and the ground voltage VSS. When the first reference code signal RCD <1> is at a logic high level, the NMOS transistor 283_1 may be turned on. When the NMOS transistor 283_1 is turned on, the NMOS capacitor 283_2 may be coupled to the third node nd23 and supply a charge.

The NMOS transistor 283_3 and the NMOS capacitor 283_4 may be coupled in series between the third node nd23 and the ground voltage VSS. When the second reference code signal RCD <2> is at a logic high level, the NMOS transistor 283_3 may be turned on. When the NMOS transistor 283_3 is turned on, the NMOS capacitor 283_4 may be coupled to the third node nd23 and supply a charge.

The NMOS transistor 283_5 and the NMOS capacitor 283_6 may be coupled in series between the fourth node nd24 and the ground voltage VSS. When the third reference code signal RCD <3> is at a logic high level, the NMOS transistor 283_5 may be turned on. When the NMOS transistor 283_1 is turned on, the NMOS capacitor 283_6 may be coupled to the fourth node nd24 and supply a charge.

The NMOS transistor 283_7 and the NMOS capacitor 283_8 may be coupled in series between the fourth node nd24 and the ground voltage VSS. When the fourth reference code signal RCD <4> is at a logic high level, the NMOS transistor 283_7 may be turned on. When the NMOS transistor 283_7 is turned on, the NMOS capacitor 283_8 may be coupled to the fourth node nd24 and supply a charge.

The fourth charge supplying circuit 283 may include NMOS capacitors 283_2, 283_4, 283_6, and 283_8 coupled to the third node nd23 and the fourth node nd24 according to a logic level combination of the first to fourth reference codes RCD <1:4 >. The fourth charge supplying circuit 283 may control the second delay variable of the third node nd23 and the fourth node nd24 according to the coupling of the NMOS capacitors 283_2, 283_4, 283_6 and 283_ 8.

The second delay variable may be controlled according to the number of PMOS capacitors 282_2, 282_4, 282_6, and 282_8 and NMOS capacitors 283_2, 283_4, 283_6, and 283_ 8. The second delay variable may be controlled according to the amount of charge of the PMOS capacitors 282_2, 282_4, 282_6, and 282_8 and the NMOS capacitors 283_2, 283_4, 283_6, and 283_ 8. The delay variable by which the second delay variable is changed once may be set to 10 ps. For example, when the first to fourth reference codes RCD <1:4> are counted down once, the second delay variable may be decreased by 10 ps.

The amount of charge of the PMOS capacitors 282_2, 282_4, 282_6, and 282_8 can be determined according to the aspect ratio. The width-to-length ratio of the PMOS capacitors 282_2 and 282_6 may be set to 4/1, and the width-to-length ratio of the PMOS capacitors 282_4 and 282_8 may be set to 4/2. The width-to-length ratios of the PMOS capacitors 282_2, 282_4, 282_6, and 282_8 may be set to various ratios according to embodiments.

The charge amount of the NMOS capacitors 283_2, 283_4, 283_6, and 283_8 can be determined according to the aspect ratio. The width-to-length ratio of the NMOS capacitors 283_2 and 283_6 may be set to 1/2, while the width-to-length ratio of the NMOS capacitors 283_4 and 283_8 may be set to 2/2. The width-to-length ratios of the NMOS capacitors 283_2, 283_4, 283_6, and 283_8 may be set to various ratios according to embodiments.

Referring to fig. 11, a phase control operation of the system 1 for performing the phase control operation according to an embodiment will be described. For example, an operation of controlling the internal clock ICLK and the reference clock RCLK to have the same phase by controlling the first delay variable and the second delay variable after the phase difference occurs between the internal clock ICLK and the reference clock RCLK due to PVT variation will be described as follows.

Before the description, the frequency divider circuit 221 generates the divided clock DCKL having a frequency corresponding to 1/2 of the frequency of the clock CLK in synchronization with the clock CLK.

At a time point T1, the internal clock ICLK and the reference clock RCLK are in phase. At this time, since the internal clock ICLK and the reference clock RCLK are in phase, the detection circuit 225 generates the phase detection signal PD _ INF that is inhibited to a logic low level.

At a time point T2, the phases of the internal clock ICLK and the reference clock RCLK are changed due to PVT change, and thus a phase difference P1 occurs. At this time, since the internal clock ICLK and the reference clock RCLK are out of phase, the detection circuit 225 generates the phase detection signal PD _ INF that is enabled to a logic high level.

At a time point T3, the delay amount control circuit 222 generates the first to fourth reference codes RCD <1:4> counted down by the logic-high phase detection signal PD _ INF in synchronization with the clock CLK. The delay amount control circuit 222 generates the first through fourth object codes TCD <1:4> counted down by the logic-high phase detection signal PD _ INF in synchronization with the clock CLK.

The reference path circuit 224 may control the second delay variable a according to a logic level combination of the first to fourth reference codes RCD <1:4 >. The reference path circuit 224 may generate the reference clock RCLK by delaying the divided clock DCKL by the controlled second delay variable a. The second delay variable a is set to 30 ps.

The target path circuit 223 may control the first delay variable B according to a logic level combination of the first to fourth target codes TCD <1:4 >. The target path circuit 223 may generate the internal clock ICLK by delaying the divided clock DCKL by the controlled first delay variable B. The first delay variable B is set to 15 ps.

At a time point T4, the delay amount control circuit 222 generates the first to fourth reference codes RCD <1:4> counted down by the logic-high phase detection signal PD _ INF in synchronization with the clock CLK. The delay amount control circuit 222 generates the first through fourth object codes TCD <1:4> counted down by the logic-high phase detection signal PD _ INF in synchronization with the clock CLK.

The reference path circuit 224 may control the second delay variable C according to a logic level combination of the first to fourth reference codes RCD <1:4 >. The reference path circuit 224 may generate the reference clock RCLK by delaying the divided clock DCKL according to the controlled second delay variable C. The second delay variable C is set to 20 ps.

The target path circuit 223 may control the first delay variable D according to a logic level combination of the first to fourth target codes TCD <1:4 >. The target path circuit 223 may generate the internal clock ICLK by delaying the divided clock DCKL by the controlled first delay variable D. The first delay variable D is set to 10 ps.

At a time point T5, the delay amount control circuit 222 generates the first to fourth reference codes RCD <1:4> counted down by the logic-high phase detection signal PD _ INF in synchronization with the clock CLK. The delay amount control circuit 222 generates the first through fourth object codes TCD <1:4> counted down by the logic-high phase detection signal PD _ INF in synchronization with the clock CLK.

The reference path circuit 224 may control the second delay variable E according to a logic level combination of the first to fourth reference codes RCD <1:4 >. The reference path circuit 224 may generate the reference clock RCLK by delaying the divided clock DCKL by the controlled second delay variable E. The second delay variable E is set to 10 ps.

The target path circuit 223 may control the first delay variable F according to a logic level combination of the first to fourth target codes TCD <1:4 >. The target path circuit 223 may generate the internal clock ICLK by delaying the frequency-divided clock DCKL according to the controlled first delay variable F. The first delay variable D is set to 5 ps.

At a time point T6, since the internal clock ICLK and the reference clock RCLK are in phase, the detection circuit 225 generates the phase detection signal PD _ INF that is disabled to a logic low level.

The delay amount control circuit 222 generates the first to fourth reference codes RCD <1:4> clamped by the logic low phase detection signal PD _ INF in synchronization with the clock CLK. The delay amount control circuit 222 generates the first through fourth target codes TCD <1:4> clamped by the phase detection signal PD _ INF of logic low in synchronization with the clock CLK.

The reference path circuit 224 does not control the second delay variable according to the logic level combination of the first through fourth reference codes RCD <1:4 >.

The target path circuit 223 does not control the first delay variable according to the logic level combination of the first to fourth target codes TCD <1:4 >.

The internal clock generation circuit 203 may control a first delay variable and a second delay variable for delaying the clock CLK, and generate the internal clock ICLK by delaying the clock CLK according to the controlled first delay variable and second delay variable, thereby controlling the phase of the internal clock ICLK according to PVT variations.

The system for performing the phase control operation according to the present embodiment can control the phase of the internal clock by differently controlling the delay variables for different paths according to PVT variations. Further, the system for performing the phase control operation according to the present embodiment can compensate the phase of the internal clock and input/output data according to PVT variation, thereby preventing an operation error.

Fig. 12 is a block diagram illustrating a configuration of an electronic system 1000 according to an embodiment. As shown in fig. 12, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

The host 1100 and the semiconductor system 1200 may transmit/receive signals to/from each other using an interface protocol. Examples of interface protocols used between the host 1100 and the semiconductor system 1200 may include multimedia card (MMC), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), peripheral component interconnect express (PCI-E), enhanced technology attachment (ATA), serial ATA (sata), parallel ATA (pata), serial attached scsi (sas), Universal Serial Bus (USB), and the like.

The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400(K: 1). The controller 1300 may control the semiconductor device 1400(K:1) to perform a phase control operation. Each of the semiconductor devices 1400(K:1) can control the phase of the internal clock by controlling the delay variable for different paths in different ways according to PVT variations. Each of the semiconductor devices 1400(K:1) may compensate for the phase of the internal clock and input/output data according to PVT variation, thereby preventing an operation error.

The controller 1300 may be implemented as the controller 110 shown in fig. 1. Each of the semiconductor devices 1400(K:1) may be implemented as the semiconductor device 120 shown in fig. 1. According to one embodiment, the semiconductor device 120 may be implemented as one of a Dynamic Random Access Memory (DRAM), a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), and a Ferroelectric Random Access Memory (FRAM).

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Thus, the method of operation of the data storage device described herein should not be limited based on the described embodiments.