阅读说明：本技术 多相时钟发生器、存储器装置和生成多相时钟的方法 (Multiphase clock generator, memory device and method for generating multiphase clock ) 是由 崔训对 崔佳滥 于 2021-05-08 设计创作，主要内容包括：提供了多相时钟发生器、存储器装置和生成多相时钟的方法。该多相时钟发生器包括第一可变延迟线和第二可变延迟线；第一分相器,被配置为将从时钟树输出的第一相位延迟时钟进行相位分离,以输出第一分频时钟和第三分频时钟；第二分相器,被配置为将从时钟树输出的第二相位延迟时钟进行相位分离,以输出第二分频时钟和第四分频时钟；第一占空比检测器,被配置为检测第一分频时钟与第三分频时钟之间的第一占空比误差；以及第二占空比检测器,被配置为检测第二分频时钟与第四分频时钟之间的第二占空比误差。第一可变延迟线根据第一占空比误差被控制,并且第二可变延迟线根据第二占空比误差被控制。(A multi-phase clock generator, a memory device and a method of generating multi-phase clocks are provided. The multiphase clock generator includes a first variable delay line and a second variable delay line; a first phase splitter configured to phase-split a first phase-delayed clock output from the clock tree to output a first frequency-divided clock and a third frequency-divided clock; a second phase splitter configured to phase-separate a second phase-delayed clock output from the clock tree to output a second frequency-divided clock and a fourth frequency-divided clock; a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to a first duty cycle error and the second variable delay line is controlled according to a second duty cycle error.)

1. A multiphase clock generator, comprising:

a first variable delay line configured to receive a reference clock and generate a delay clock;

a second variable delay line configured to receive the delay clock and generate a second phase delayed clock;

a fixed delay line configured to receive the delayed clock and generate a first phase delayed clock;

a delay line controller configured to control the first variable delay line according to a first phase difference between the reference clock and a feedback clock;

a phase controller configured to control the second variable delay line according to a second phase difference between the delay clock and the second phase delay clock;

a clock tree configured to receive the first phase-delayed clock and the second phase-delayed clock;

a first phase splitter configured to phase-split the first phase-delayed clock received from the clock tree to output a first divided clock and a third divided clock;

a second phase splitter configured to phase separate the second phase delayed clock received from the clock tree to output a second frequency divided clock and a fourth frequency divided clock;

a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and

a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock,

wherein the first variable delay line is controlled in accordance with the first duty cycle error and the second variable delay line is controlled in accordance with the second duty cycle error.

2. The multiphase clock generator of claim 1, further comprising:

a clock buffer configured to buffer the first phase clock and output the reference clock.

3. The multiphase clock generator of claim 1, further comprising:

a duplicator configured to receive the first phase delayed clock from the fixed delay line and output the feedback clock; and

a phase detector configured to detect a first phase difference between the feedback clock from the duplicator and the reference clock.

4. The multiphase clock generator of claim 3, wherein the first variable delay line comprises:

a first coarse delay line configured to receive the reference clock and delay the reference clock according to a first coarse code value;

a first fine delay line configured to receive a clock output from the first coarse delay line and delay the clock from the first coarse delay line according to a first fine code value; and

a first duty cycle error corrector configured to correct a clock received from the first fine delay line according to the first duty cycle error.

5. The multiphase clock generator of claim 4, wherein said delay line controller comprises:

a coarse delay line controller configured to output the first coarse code value in response to the first phase difference; and

a fine delay line controller configured to output the first fine code value in response to the first phase difference.

6. The multiphase clock generator of claim 3, wherein the second variable delay line comprises:

a second coarse delay line configured to receive the delayed clock and delay the delayed clock according to a second coarse code value;

a second fine delay line configured to receive the clock output from the second coarse delay line and delay the clock output from the second coarse delay line according to a second fine code value; and

a second duty error corrector configured to correct a clock output from the second fine delay line according to the second duty error.

7. The multiphase clock generator of claim 6, wherein the phase controller outputs the second coarse code value and the second fine code value according to a second phase difference between the delayed clock and a clock output from the second fine delay line.

8. The multiphase clock generator of claim 1, wherein the first phase delayed clock has a same phase as the reference clock, and

the phase of the second phase delayed clock is offset by 90 degrees with respect to the phase of the reference clock.

9. The multiphase clock generator of claim 1, wherein the first divided clock has a same phase as the reference clock,

the phase of the second divided clock is shifted by 90 degrees with respect to the phase of the reference clock,

the phase of the third divided clock is shifted by 180 degrees with respect to the phase of the reference clock, and

the phase of the fourth divided clock is shifted by 270 degrees with respect to the phase of the reference clock.

10. The multiphase clock generator of claim 1, further comprising:

an output buffer configured to receive the first, second, third, and fourth divided clocks and output data.

11. A memory device including a multiphase clock generator, the memory device comprising:

a delay locked loop circuit configured to receive a reference clock and output a delayed clock;

a clock tree configured to receive the delayed clock and output the delayed clock;

a fixed delay line configured to receive the delayed clock and output a first phase delayed clock;

a second variable delay line configured to phase shift the delay clock to generate a second phase delayed clock;

a phase controller configured to control the second variable delay line according to a second phase difference between the delay clock and the second phase delay clock;

a first phase splitter configured to phase-split the first phase-delayed clock to output a first frequency-divided clock and a third frequency-divided clock;

a second phase splitter configured to phase-separate the second phase delayed clock to output a second frequency-divided clock and a fourth frequency-divided clock;

a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and

a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock,

wherein the delay locked loop circuit is controlled in accordance with the first duty cycle error, and

the second variable delay line is controlled in accordance with the second duty cycle error.

12. The memory device of claim 11, wherein the delay locked loop circuit comprises:

a first variable delay line configured to receive the reference clock and generate the delay clock;

a duplicator configured to receive the delay clock output from the first variable delay line and output a feedback clock;

a phase detector configured to detect a first phase difference between the reference clock and the feedback clock; and

a delay line controller configured to control the first variable delay line according to the first phase difference.

13. The memory device of claim 12, wherein the first variable delay line comprises:

a first coarse delay line configured to receive the reference clock and delay the reference clock according to a first coarse code value;

a first fine delay line configured to receive a clock output from the first coarse delay line and delay the clock from the first coarse delay line according to a first fine code value; and

a first duty cycle error corrector configured to correct a clock from the first fine delay line according to the first duty cycle error.

14. The memory device of claim 13, wherein the delay line controller comprises:

a coarse delay line controller configured to output the first coarse code value in response to a first phase difference; and

a fine delay line controller configured to output the first fine code value in response to the first phase difference.

15. The memory device of claim 11, wherein the first phase splitter and the second phase splitter separate received clocks to have a phase difference of 180 degrees.

16. A method of generating multi-phase clocks for a memory device, the method comprising:

initiating a delay locked loop operation to receive a reference clock and generate a delay clock;

performing a coarse lock operation on the reference clock;

determining whether the coarse locking operation is complete;

performing a fine locking operation while performing a first duty error correction operation between a first divided clock corresponding to the delayed clock and a third divided clock when the coarse locking operation is completed;

phase separating at least one phase delayed clock generated based on the delayed clock to generate a split phase clock; and

performing a second duty cycle error correction operation between a second divided clock and a fourth divided clock corresponding to the divided phase clock.

17. The method of claim 16, further comprising:

when the coarse locking operation is not complete, the coarse locking operation is re-executed.

18. The method of claim 16, wherein the phase separating comprises:

outputting the delayed clock as a first phase delayed clock through a fixed delay line;

generating a second phase delay clock by passing the delay clock through a variable delay line;

phase separating the first phase-delayed clock to generate the first divided clock and the third divided clock; and

phase separating the second phase delayed clock to generate the second and fourth divided clocks.

19. The method of claim 18, wherein the phase of the first phase delayed clock is the same as the phase of the delayed clock, and

the second phase delayed clock is shifted in phase by 90 degrees with respect to the phase of the delayed clock.

20. The method of claim 18, further comprising:

receiving the first phase delayed clock and the second phase delayed clock through a clock tree; and

outputting the first phase-delayed clock and the second phase-delayed clock through the clock tree.

Technical Field

Exemplary embodiments of the present disclosure relate to a multi-phase clock generator, a memory device including the same, and a method of generating multi-phase clocks of the memory device.

Background

In an input/output (I/O) interface method that synchronizes data to a clock signal and sends the synchronized data between a memory and a memory controller in a system, it is important that the data be correctly synchronized to the clock signal. Since Dynamic Random Access Memory (DRAM) operates at high speed, the DRAM may synchronize data with a clock signal using a Delay Locked Loop (DLL) circuit.

The DLL circuit includes a coarse delay line having a high delay resolution and a fine delay line having a low delay resolution.

Disclosure of Invention

Exemplary embodiments of the inventive concept provide a multi-phase clock generator, a memory device including the same, and a method of generating multi-phase clocks of the memory device.

Exemplary embodiments of the inventive concept provide a multi-phase clock generator that may be implemented in a small area, a memory device including the multi-phase clock generator, and a method of generating multi-phase clocks of the memory device.

According to an exemplary embodiment of the inventive concept, a multiphase clock generator includes: a first variable delay line, a second variable delay line, a fixed delay line, a delay line controller, a phase controller, a clock tree, a first phase splitter, a second phase splitter, a first duty cycle detector, and a second duty cycle detector. The first variable delay line is configured to receive a reference clock and generate a delay clock. The second variable delay line is configured to receive the delay clock and generate a second phase delay clock. The fixed delay line is configured to receive the delayed clock and generate a first phase delayed clock. The delay line controller is configured to control the first variable delay line according to a first phase difference between the reference clock and the feedback clock. The phase controller is configured to control the second variable delay line according to a second phase difference between the delayed clock and the second phase delayed clock. The clock tree is configured to receive a first phase delayed clock and a second phase delayed clock. The first phase splitter is configured to phase-split a first phase-delayed clock output from the clock tree to output a first divided clock and a third divided clock. The second phase splitter is configured to phase-split the second phase-delayed clock output from the clock tree to output a second frequency-divided clock and a fourth frequency-divided clock. The first duty cycle detector is configured to detect a first duty cycle error between the first divided clock and the third divided clock. The second duty cycle detector is configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to a first duty cycle error and the second variable delay line is controlled according to a second duty cycle error.

According to an exemplary embodiment of the inventive concept, a memory device including a multi-phase clock generator includes: a delay locked loop circuit, a clock tree, a fixed delay line, a second variable delay line, a phase controller, a first phase splitter, a second phase splitter, a first duty cycle detector, and a second duty cycle detector. The delay locked loop circuit is configured to receive a reference clock and output a delayed clock. The clock tree is configured to receive the delayed clock and output the delayed clock. The fixed delay line is configured to receive the delayed clock and output a first phase delayed clock. The second variable delay line is configured to phase shift the delay clock to generate a second phase delayed clock. The phase controller is configured to control the second variable delay line according to a second phase difference between the delayed clock and the second phase delayed clock. The first phase splitter is configured to phase-split the first phase-delayed clock to output a first divided clock and a third divided clock. The second phase splitter is configured to phase-separate the second phase delayed clock to output a second frequency-divided clock and a fourth frequency-divided clock. The first duty cycle detector is configured to detect a first duty cycle error between the first divided clock and the third divided clock. The second duty cycle detector is configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The delay locked loop circuit is controlled in accordance with the first duty cycle error and the second variable delay line is controlled in accordance with the second duty cycle error.

According to an exemplary embodiment of the inventive concept, a method of generating a multi-phase clock of a memory device includes: initiating a delay locked loop operation to receive a reference clock and generate a delay clock; performing a coarse lock operation on a reference clock; determining whether the coarse locking operation is complete; performing a fine locking operation while performing a first duty error correction operation between a first divided clock corresponding to the delayed clock and a third divided clock when the coarse locking operation is completed; phase separating at least one phase delayed clock generated based on the delayed clock to generate a split phase clock; and performing a second duty error correction operation between the second divided clock and the fourth divided clock corresponding to the divided phase clock.

Drawings

The present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1 is a schematic block diagram of a multiphase clock generator according to an exemplary embodiment of the inventive concept.

Fig. 2 is a detailed block diagram of the first variable delay line and the second variable delay line shown in fig. 1.

Fig. 3 is a flowchart illustrating an operation method of a multiphase clock generator according to an exemplary embodiment of the inventive concept.

Fig. 4 is a timing diagram illustrating the start of the DLL operation shown in fig. 3.

FIG. 5 is a timing diagram of the coarse lock operation shown in FIG. 3.

Fig. 6 is a timing diagram of a phase shift operation when a duty error correction operation is performed according to an exemplary embodiment of the inventive concept.

Fig. 7 is a block diagram of a multiphase clock generator according to an exemplary embodiment of the inventive concept.

Fig. 8 is a schematic block diagram illustrating a process of generating a multi-phase clock by a multi-phase clock generator according to an exemplary embodiment of the inventive concept.

Fig. 9 is a block diagram of a memory device according to an exemplary embodiment of the inventive concept.

Fig. 10 is a perspective view of a memory chip according to an exemplary embodiment of the inventive concept.

Fig. 11 is a block diagram of a computing system according to an exemplary embodiment of the inventive concept.

Fig. 12 is a block diagram of a vehicle electronic system according to an exemplary embodiment of the inventive concept.

Fig. 13 is a block diagram of a mobile device according to an exemplary embodiment of the inventive concept.

Fig. 14 is a block diagram of a computing system according to an exemplary embodiment of the inventive concept.

Fig. 15 is a block diagram of a data center to which a memory device according to an exemplary embodiment is applied.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

In a multi-phase clock generator, a memory device including the same, and a method of generating multi-phase clocks of the memory device according to exemplary embodiments of the inventive concept, 90-degree phase clocks are generated from an output of a Delay Locked Loop (DLL), a duty ratio of the generated 90-degree phase clocks and a duty ratio of the DLL are compensated, and the multi-phase clocks are generated through phase separation.

Fig. 1 is a schematic block diagram of a multiphase clock generator 100 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1, a multiphase clock generator 100 includes a clock buffer (CLK BUF)110

(e.g., a buffer circuit), a first variable delay line (VDL1)120, a delay line controller (VDL CNTL)124 (e.g., a control circuit), a Phase Detector (PD)127 (e.g., a phase detection circuit), a duplicator 128, a Fixed Delay Line (FDL)130, a second variable delay line (VDL2)140, a phase controller (PHASE CNTL)144 (e.g., a control circuit), a clock TREE (CLK TREE)150, a first phase splitter (PS1)161, a second phase splitter (PS2)162, a first duty cycle detector (DCD1)163 (e.g., a detector circuit), a second duty cycle detector (DCD2)164 (e.g., a detector circuit), and an output buffer (DOUT)170 (e.g., a buffer circuit).

The multiphase clock generator 100 receives an input clock CK (e.g., a clock signal), generates a reference clock DLLIN _ CK from the input clock CK, and divides the frequency of the reference clock DLLIN _ CK to generate first to fourth divided clocks PDLL0, PDLL90, PDLL180, and PDLL270 having a phase difference of 90 degrees from each other.

The clock buffer (CLK BUF)110 may buffer the input clock CK to generate the reference clock DLLIN _ CK.

The first variable delay line (VDL1)120 receives the reference clock DLLIN _ CK from the clock buffer 110 and delays the reference clock DLLIN _ CK according to the first phase difference or the first duty error to output a delayed clock DLL _ CK 0. The first phase difference may include a phase difference between the reference clock DLLIN _ CK and the first phase delayed clock DLL _ CK0D of the fixed delay line 130. The first duty cycle error may be a duty cycle error between first divided clock PDLL0 and third divided clock PDLL 180. However, the first phase difference and the first duty error are not limited thereto.

In an embodiment, the delay line controller (VDL CNTL)124 controls the first variable delay line 120 according to a code value corresponding to the phase difference. For example, the delay line controller 124 may determine on/off of the delay cells constituting the first variable delay line 120 according to the code value to control the delay of the reference clock DLLIN _ CK.

The Phase Detector (PD)127 detects a phase between the feedback clock FBCLK and the reference clock DLLIN _ CK.

The duplicator 128 may have substantially the same amount of delay as the clock path that delays the reference clock DLLIN _ CK. In an embodiment, the replicator 128 delays the signal passing through it by the same amount that the first variable delay line (VDL1)120 delays the reference clock DLLIN _ CK. In an exemplary embodiment, the duplicator 128 is implemented by a delay circuit.

The Fixed Delay Line (FDL)130 receives the delay clock DLL _ CK0 from the first variable delay line 120 and outputs a first phase delay clock DLL _ CK 0D.

The second variable delay line (VDL2)140 receives the delay clock DLL _ CK0 from the first variable delay line 120 and outputs the second phase delay clock DLL _ CK90 according to the phase control code value corresponding to the second phase difference or the second duty error. In an embodiment, the phase control code value is a value corresponding to a phase difference between the delayed clock DLL _ CK0 and the second phase delayed clock DLL _ CK90, and the second duty error is a duty error between the second frequency-divided clock PDLL90 and the fourth frequency-divided clock PDLL 270. However, the second phase difference and the second duty error are not limited thereto.

The phase controller (PHASE CNTL)144 outputs a phase control code value corresponding to a phase difference between the delay clock DLL _ CK0 and the second phase delay clock DLL _ CK 90.

The clock TREE (CLK TREE)150 receives the first phase delayed clock DLL _ CK0D and the second phase delayed clock DLL _ CK 90. The first phase delayed clock DLL _ CK0D and the second phase delayed clock DLL _ CK90 may be transmitted within the semiconductor memory device through an internal path. The clock tree 150 outputs the first phase delayed clock DLL _ CK0D to the first phase splitter (PS1)161 and the second phase delayed clock DLL _ CK90 to the second phase splitter (PS2) 162.

The first phase splitter (PS1)161 receives the first phase delayed clock DLL _ CK0D and performs phase separation on the first phase delayed clock DLL _ CK0D to output a first frequency-divided clock PDLL0 and a third frequency-divided clock PDLL 180.

The second phase splitter (PS2)162 receives the second phase delayed clock DLL _ CK90 and phase-separates the second phase delayed clock DLL _ CK90 to output the second frequency-divided clock PDLL90 and the fourth frequency-divided clock PDLL 270.

The first duty cycle detector (DCD1)163 is configured to detect a first duty cycle error between the first divided clock PDLL0 and the third divided clock PDLL 180.

The second duty cycle detector (DCD2)164 is configured to detect a second duty cycle error between the second frequency-divided clock PDLL90 and the fourth frequency-divided clock PDLL 270.

The output buffer 170 may buffer the first to fourth divided-frequency clocks PDLL0, PDLL90, PDLL180, and PDLL270 having different phases output from the first and second phase splitters 161 and 162, and may output the buffered first to fourth divided-frequency clocks PDLL0, PDLL90, PDLL180, and PDLL270 to the outside.

Multiphase clocks (e.g., 4-phase clocks) are used to address internal bandwidth limitations of memory devices. This offset between the multiphase clocks needs to be corrected. Previous multi-phase clock generators include complex multi-phase detectors that occupy a large area and consume a large amount of power.

The multiphase clock generator 100 according to an exemplary embodiment of the inventive concept is configured to correct a duty ratio of a zero-divided clock to compensate for an offset between 0 degrees and 180 degrees, and correct a phase difference using a Delay Locked Loop (DLL) to compensate for an offset between 0 degrees and 90 degrees. Accordingly, the multiphase clock generator 100 can reduce power consumption and can be implemented with a less complicated structure.

Each of the first and second variable delay lines 120 and 140 according to an exemplary embodiment of the inventive concept includes a coarse delay line and a fine delay line.

Fig. 2 is a detailed block diagram of the first variable delay line 120 and the second variable delay line 140 shown in fig. 1. Referring to fig. 2, the first variable delay line 120 includes a first COARSE delay line (COARSE DL1)121, a first FINE delay line (FINE DL1)122, and a first duty cycle correction circuit (DCC1) 123.

In an embodiment, the first COARSE delay line (COARSE DL1)121 delays the reference clock DLLIN _ CK using a series of first COARSE delay cells. Each of the first coarse delay cells may be turned on/off according to the first coarse code CC 1. For example, the delay cells turned on according to the first coarse code CC1 have a first coarse delay amount. The delay cells opened according to the first coarse code CC1 may be bypassed.

In an embodiment, the first FINE delay line (FINE DL1)122 delays the clock output from the first coarse delay line 121 using a first FINE delay cell. Each of the first fine delay cells may be turned on/off according to the first fine code FC 1. For example, the delay cell turned on according to the first fine code FC1 has a first fine delay amount. The delay cell opened according to the first fine code FC1 may be bypassed.

In an exemplary embodiment, the Phase Detector (PD)127 detects a first phase difference between the reference clock DLLIN _ CK and the feedback clock FBCLK. The delay line controller 124 may include a coarse delay line controller (CDL CNTL)125 and a fine delay line controller (FDL CNTL) 126. The coarse delay line controller 125 generates a first coarse code CC1 corresponding to the first phase difference. The fine delay line controller 126 generates a first fine code PC1 corresponding to the first phase difference.

A first duty cycle correction circuit (DCC1)123 controls the clock output from the first fine delay line 122 according to the first duty cycle error. The first duty cycle error may be output from a first duty cycle detector (DCD1) 163. In an embodiment, the delay clock DLL _ CK0 output from the first duty cycle correction circuit 123 is transmitted to the fixed delay line 130 and the second variable delay line 140.

With continued reference to fig. 2, the second variable delay line 140 includes a second COARSE delay line (COARSE DL2)141, a second FINE delay line (FINE DL2)142, and a second duty cycle correction circuit (DCC2) 143.

In an embodiment, the second COARSE delay line (COARSE DL2)141 delays the delay clock DLL _ CK0 using a second COARSE delay cell in series. In an embodiment, each of the second coarse delay cells is turned on/off according to a second coarse code CC 2.

The second FINE delay line (FINE DL2)142 delays the clock output from the second coarse delay line 141 using a second FINE delay cell. In the embodiment, each of the second fine delay units is turned on/off according to the second fine code FC 2.

In an exemplary embodiment, the phase controller (PHASE CNTL)144 generates a second coarse code CC2 and a second fine code FC2 corresponding to a second phase difference between the delay clock DLL _ CK0 and the clock output from the second fine delay line 142.

A second duty cycle correction circuit (DCC2)143 controls the clock output from the second fine delay line 142 according to the second duty cycle error. The second duty cycle error may be output from the second duty cycle detector (DCD2) 164. In the embodiment, the second phase delayed clock DLL _ CK90 output from the second duty correction circuit 143 is transmitted to the clock tree 150 (see fig. 1).

Fig. 3 is a flowchart illustrating an operation method of the multiphase clock generator 100 according to an exemplary embodiment of the inventive concept. Referring to fig. 1 to 3, the operation of the multiphase clock generator 100 will be described below.

For convenience of description, it will be assumed that the multiphase clock generator 100 is installed in a memory device. During power-up of the memory device, the multi-phase clock generator 100 starts operating (S110).

The multiphase clock generator 100 receives the input clock CK and starts a Delay Locked Loop (DLL) operation using the input clock CK (S120). The DLL operation may be performed by: the first variable delay line (VDL1)120 delays the reference clock DLLIN _ CK; the variable delay line controller (VDL CNTL)124 determines a delay amount of the first variable delay line 120 according to the first phase difference; the Phase Detector (PD)127 detects a first phase difference between the reference clock DLLIN _ CK and the feedback clock FBCLK; and the duplicator 128 delays the first phase delayed clock DLL _ CK0D by a predetermined value to output the feedback clock FBCLK. DLL operations may include coarse lock operations and fine lock operations.

A coarse locking operation is performed according to the first phase difference (S130). Then, it is determined whether the coarse locking operation is completed (S140). When the coarse locking operation is not completed, the flow proceeds to S130.

When the coarse locking operation is completed, a first duty error correction operation (e.g., DCC0) and a fine locking operation are performed on the delay path of the reference clock DLLIN _ CK (S150). Phase separation is then performed by the corresponding phase splitter (S160). The phase separation may be performed simultaneously with the first duty error correction operation or the fine locking operation. For example, the reference clock DLLIN _ CK, the delayed clock DLL _ CK0 of the reference clock DLLIN _ CK, or the first phase delayed clock DLL _ CK0D and the second phase delayed clock DLL _ CK90 of the delayed clock DLL _ CK0 may be phase-separated by their phase splitters, respectively. A second duty cycle error correction operation (e.g., DCC90) is performed between the split phase divided clocks (e.g., PDLLs 90 and PDLLs 270) having phases (S170).

In an exemplary embodiment, the phase separation may further include: the delay clock DLL _ CK0 is output as a first phase delay clock DLL _ CK0D through a Fixed Delay Line (FDL)130 (see fig. 1), a second phase delay clock DLL _ CK90 is generated from the delay clock DLL _ CK0 through a variable delay line (VDL2)140 (see fig. 1), the first phase delay clock DLL _ CK0D is phase-separated to generate a first frequency-divided clock PDLL0 and a third frequency-divided clock PDLL180, and the second phase delay clock DLL _ CK90 is phase-separated to generate a second frequency-divided clock PDLL90 and a fourth frequency-divided clock PDLL 270. In an exemplary embodiment, the first phase delayed clock DLL _ CK0D has the same phase as the delayed clock DLL _ CK0, and the second phase delayed clock DLL _ CK90 is obtained by phase-shifting the delayed clock DLL _ CK0 by 90 degrees.

In an exemplary embodiment, the steps of receiving the first and second phase delayed clocks DLL _ CK0D and DLL _ CK90 from the clock tree 150 (see fig. 1) and outputting the first and second phase delayed clocks DLL _ CK0D and DLL _ CK90 from the clock tree 150 may also be included in the method of fig. 3.

Fig. 4 is a timing diagram illustrating the start of the DLL operation shown in fig. 3.

The initial timing of the start of the DLL operation will be described with reference to fig. 4. As shown in fig. 4, the reference clock DLLIN _ CK and the feedback clock FBCLK are in an unlocked state. The DLL operation may be started to lock the feedback clock FBCLK to the reference clock DLLIN _ CK.

In an exemplary embodiment, the delay clock DLL _ CK0, the first phase delay clock DLL _ CK0D, and the second phase delay clock DLL _ CK90 are the same in the initial state. For example, the initial transitions from logic low to logic high of the delayed clock DLL _ CK0, the first phase delayed clock DLL _ CK0D, and the second phase delayed clock DLL _ CK90 may occur substantially simultaneously.

In an exemplary embodiment, the first frequency-divided clock PDLL0 and the third frequency-divided clock PDLL180 are phase-separated by a phase splitter to have phases opposite to each other. Similarly, the second frequency-divided clock PDLL90 and the fourth frequency-divided clock PDLL270 are phase-separated by a phase splitter to have phases opposite to each other.

FIG. 5 is a timing diagram of the coarse lock operation shown in FIG. 3. Referring to fig. 5, after a predetermined time, the first to fourth divided clocks PDLL0, PDLL90, PDLL180, and PDLL270 are output while the first to fourth divided clocks PDLL0, PDLL90, PDLL180, and PDLL270 have different phases at the same point in time through a coarse locking operation.

Fig. 6 is a timing diagram of a phase shift operation when a duty error correction operation is performed according to an exemplary embodiment of the inventive concept. Referring to fig. 6, a duty error is detected between 0 and 180 degrees, and a duty error correction operation may be performed according to the detected duty error. The 90-degree phase shift operation may be performed simultaneously with the duty error correction operation.

As shown in fig. 6, the second phase delayed clock DLL _ CK90 may be generated by performing a 90-degree phase shift operation on the first phase delayed clock DLL _ CKD 0. Additionally, the first frequency-divided clock PDLL0 may be phase-shifted by 90 degrees to generate a second frequency-divided clock PDLL 90.

In fig. 1 to 6, the duplicator 128 (e.g., a circuit) feeds back the first phase delay clock DLL _ CK0D output from the Fixed Delay Line (FDL)130 to perform a DLL operation. However, embodiments of the present disclosure are not limited thereto. The duplicator according to an embodiment feeds back an output clock of the first variable delay line 120 to perform a DLL operation.

Fig. 7 is a block diagram of a multi-phase clock generator 100a according to an exemplary embodiment of the inventive concept. Referring to fig. 7, the multiphase clock generator 100a includes a clock buffer 110, a first variable delay line 120, a delay line controller 124, a phase detector 127, a duplicator 128a (e.g., a circuit), a fixed delay line 130a, a second variable delay line 140a, a phase controller 144a, a clock tree 150a, a first phase splitter 161a, a second phase splitter 162a, a first duty ratio detector 163, a second duty ratio detector 164, and an output buffer 170.

As shown in fig. 7, in comparison with the multiphase clock generator 100 shown in fig. 1, the multiphase clock generator 100a includes: a duplicator 128a receiving feedback from the first variable delay line 120, a clock tree 150a connected to the first variable delay line 120, a fixed delay line 130a delaying the delay clock DLL _ CK0 of the clock tree 150a, a second variable delay line 140a controlling the phase of the delay clock DLL _ CK0 of the clock tree 150a, and a phase controller 144a controlling the second variable delay line 140 a.

Fig. 8 is a schematic block diagram illustrating a process of generating a multi-phase clock by a multi-phase clock generator according to an exemplary embodiment of the inventive concept. Referring to fig. 8, while the DLL operation is performed, the reference clock REF CLK may be divided into four phase clocks having different phases by phase shifting and phase separation. The externally received single phase clock may be divided into four phase clocks by a DLL operation, a phase shift operation, or a phase separation operation.

In an exemplary embodiment, in the phase shift period, the first phase clock (e.g., DLL _ CK0D of fig. 1) and the second phase clock (e.g., DLL _ CK90 of fig. 1) may be separated from the DLL clock (e.g., DLL _ CK0 of fig. 1). The DLL clock may be a clock output by performing a DLL operation on a clock path of the reference clock REF CLK.

In an example embodiment, in the phase separation period, the first phase clock (e.g., PDLL0 of fig. 1) and the third phase clock (e.g., PDLL180 of fig. 1) are phase separated from the first phase clock, and the second phase clock (e.g., PDLL90 of fig. 1) and the fourth phase clock (e.g., PDLL270 of fig. 1) are phase separated from the second phase clock.

In an exemplary embodiment, duty error correction corresponding to the duty error is performed between the first phase clock and the third phase clock. In an exemplary embodiment, duty error correction corresponding to the duty error is performed between the second phase clock and the fourth phase clock.

The multiphase clock generator according to the exemplary embodiment can be applied to a memory device.

Fig. 9 is a block diagram of a memory device 200 according to an exemplary embodiment of the inventive concept. Referring to FIG. 9, memory device 200 includes an array of memory cells 210, a row decoder 220, a column decoder 230, sense amplifier circuitry 240, an address register 250, bank control logic 252, a refresh counter 254, a row address multiplexer (RA MUX)256, a column address LATCH (CA LATCH)258, control logic 260, repair control circuitry 266, timing control circuitry 264, input/output (I/O) gating circuitry 270, error correction circuitry 280, a data input/output (I/O) buffer 282, and PBT circuitry 290.

The memory cell array 210 may include first through eighth banks 211 through 218. However, the number of banks of the memory cell array 210 is not limited thereto.

The row decoder 220 may include first to eighth bank row decoders 221 to 228 connected to the first to eighth banks 211 to 218, respectively.

Column decoder 230 may include first bank column decoder 231 through eighth bank column decoder 238 connected to first bank 211 through eighth bank 218, respectively.

The sense amplifier circuit 240 may include first to eighth bank sense amplifiers 241 to 248 connected to the first to eighth banks 211 to 218, respectively.

The first to eighth banks 211 to 218, the first to eighth bank row decoders 221 to 228, the first to eighth bank column decoders 231 to 238, and the first to eighth bank sense amplifiers 241 to 248 may respectively constitute first to eighth banks. Each of the first through eighth banks 211 through 218 may include a plurality of memory cells MC formed at intersections of word lines WL and bit lines BL.

The address register 250 may receive and store an address ADDR having a BANK address BANK _ ADDR, a ROW address ROW _ ADDR, and a column address COL _ ADDR from an external memory controller. Address register 250 may provide a received BANK address BANK ADDR to BANK control logic 252, a received ROW address ROW ADDR to ROW address multiplexer 256, and a received column address COL ADDR to column address latch 258.

The BANK control logic 252 may generate a BANK control signal in response to the BANK address BANK ADDR. Among the first to eighth BANK row decoders 221 to 228, a BANK row decoder corresponding to a BANK address BANK _ ADDR may be activated in response to a BANK control signal. Among the first to eighth BANK column decoders 231 to 238, a BANK column decoder corresponding to a BANK address BANK _ ADDR may be activated in response to a BANK control signal.

The ROW address multiplexer 256 may receive a ROW address ROW _ ADDR from the address register 250 and a refresh ROW address REF _ ADDR from the refresh counter 254. The ROW address multiplexer 256 may selectively output a ROW address ROW _ ADDR or a refresh ROW address REF _ ADDR as the ROW address RA. The row address RA output from the row address multiplexer 256 may be applied to each of the first to eighth bank row decoders 221 to 228.

Among the first to eighth bank row decoders 221 to 228, the bank row decoder activated by the bank control logic 252 may decode a row address RA output from the row address multiplexer 256 to activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address. In addition, the activated bank row decoder may activate a word line corresponding to a row address, and may simultaneously activate a redundant word line corresponding to a redundant row address output from the repair control circuit 266.

The column address latch 258 may receive a column address COL _ ADDR from the address register 250 and may temporarily store the received column address COL _ ADDR. In addition, the column address latch 158 may incrementally increase the received column address COL _ ADDR in the burst mode. The column address latch 258 may apply a temporarily stored or incrementally increased column address COL _ ADDR to each of the first through eighth bank column decoders 231 through 238.

Among the first to eighth BANK column decoders 231 to 238, the BANK column decoder activated by the BANK control logic 252 may activate sense amplifiers corresponding to the BANK address BANK _ ADDR and the column address COL _ ADDR through the input/output gate circuit 270. In addition, the activated bank column decoder may perform a column repair operation in response to the column repair signal CRP output from the repair control circuit 266.

Control logic 260 may control the operation of memory device 200. For example, control logic 260 may generate control signals that cause memory device 200 to perform a write operation or a read operation. The control logic 260 may include a command decoder 261 to decode a command CMD received from the memory controller, and a mode register set 262 to set an operation mode of the memory device 200.

For example, the command decoder 261 may decode the write enable signal/WE, the row address strobe signal/RAS, the column address strobe signal/CAS, and the chip select signal/CS to generate operation control signals ACT, PCH, WE, and RD corresponding to the command CMD. The control logic 260 may provide operation control signals ACT, PCH, WE, and RD to the timing control circuit 264. The operation control signals ACT, PCH, WR, and RD may include an active signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD. The timing control circuit 264 may generate a first control signal CTL1 for controlling a voltage level of the word line WL and a second control signal CTL2 for controlling a voltage level of the bit line BL in response to the operation control signals ACT, PCH, WR, and RD, and may supply the first control signal CTL1 and the second control signal CTL2 to the memory cell array 210.

The repair control circuit 266 may generate repair control signals CRP and SRP for controlling a repair operation of the first cell region and the second cell region of at least one memory bank among the memory banks according to the ROW address ROW _ ADDR and the column address COL _ ADDR of the address ADDR (or access address) and the fuse information of each of the word lines. The repair control circuit 266 may provide redundant row addresses to corresponding bank row decoders, may provide column repair signals CRP to corresponding bank column decoders, and may provide select signals and enable signals SRA to block control circuits associated with corresponding redundant array blocks. In addition, the repair control circuit 266 may generate an hPPR wordline activation signal in response to the address ADDR in the hPPR mode stored in the mode register group 262. Further, the repair control circuit 266 may generate an sPPR wordline activation signal sPPR _ WL _ EN in response to the address ADDR in the sPPR mode stored in the mode register set 1262. In addition, the repair control circuit 266 may turn OFF the sPPR logic in the sPPR _ OFF mode and may generate a normal wordline activation signal to access the previous data. In an exemplary embodiment, repair control circuit 266 changes the repair unit according to address ADDR and fuse information. For example, the repair control circuit 266 may change the type and amount of the address ADDR and the fuse information.

The input/output gating circuit 270 may include a plurality of input/output gates. Each of the plurality of input/output gate circuits may include a circuit for gating input/output data, and may further include input data mask logic, a data latch for storing data output from the first through eighth banks 211 through 218, and a write driver for writing data to the first through eighth banks 211 through 218.

The error correction circuit 280 may generate parity bits from data bits of the data DQ supplied from the data input/output buffer 282 in a write operation, and may supply a codeword CW including the data DQ and the parity bits to the input/output gating circuit 270, and the input/output gating circuit 270 may write the codeword CW to a bank. Also, error correction circuit 280 may receive codewords CW read from a single bank from input/output gating circuit 270 in a read operation. In an embodiment, the error correction circuit 280 performs ECC decoding on the data DQ using the parity bits included in the read codeword CW to correct at least one error bit included in the data DQ, and supplies the at least one corrected error bit to the data input/output buffer 282.

In an exemplary embodiment, a codeword CW to be read in one of the first through eighth banks 211 through 218 is read out by a sense amplifier corresponding to the one bank and stored in a data latch. After ECC decoding is performed by the error correction circuit 280, the codeword CW stored in the data latch may be provided to the memory controller through the data input/output buffer 282. After the ECC encoding is performed by the error correction circuit 280, data DQ to be written to one of the first to eighth banks 211 to 218 may be written to the one bank through a write driver.

The data input/output buffer 282 may supply the data DQ to the error correction circuit 280 according to a clock CLK supplied from the memory controller in a write operation, and may supply the data DQ supplied from the error correction circuit 280 to the memory controller in a read operation.

In an exemplary embodiment, the data input/output buffer 282 includes the multi-phase clock generator (MPC)100 (see fig. 1) described in fig. 1-8. The externally received clock may be divided into multiphase clocks. These divided clocks can be used to perform data output operations.

The PBT circuit 290 can perform a parallel test operation on each of externally received test data and memory banks, can perform a repair operation when an error is correctable, and can output a result value according to the result. In addition, the PBT circuitry 290 may qualify a bank in response to the test pass signal PBTPASS regardless of the resulting value of the test operation of the corresponding bank. In an exemplary embodiment, in the parallel bit test operation, a test pass signal PBTPASS is output from the mode register set 262.

A memory device (e.g., DRAM) may divide an external clock and use the divided clock to overcome internal frequency limitations. For example, the divided clock may include four phases. The data output terminal of the memory device may restore the divided clock to the same frequency as the received external clock. However, when the memory device uses a multi-phase clock, an offset may occur between multiple phases. This offset may cause a duty cycle error when the divided clock is restored to the same frequency as the external clock.

The memory device 200 according to an exemplary embodiment of the inventive concept includes a multi-phase clock generator MPC to precisely match a phase relationship between a plurality of phases to 90 degrees. The multiphase clock generator MPC of the present disclosure may correct the duty cycle error of the divided clock by inputting the divided clock to the duty cycle detector DCC to compensate for the offset between 0 degrees and 180 degrees (or the offset between 90 degrees and 270 degrees). In addition, the multi-phase clock generator MPC according to an embodiment of the present disclosure may use a 90-degree phase shift to generate a multi-phase clock to correct the offset between 0 and 90 degrees. In this case, a ring oscillator may be used to perform the phase shift operation.

The memory device according to example embodiments may be implemented as a stacked memory device.

Fig. 10 is a perspective view of a memory chip according to an exemplary embodiment of the inventive concept. Referring to fig. 10, the memory chip 1000 includes first to third memory wafers 1100 to 1300 stacked in a direction perpendicular to a substrate, and Through Silicon Vias (TSVs). The number of stacked memory dies is not limited to the number shown in fig. 10. For example, the first memory die 1100 and the second memory die 1200 may be slave dies, and the third memory die 1300 may be a master die or a buffer die.

The first memory die 1100 may include a first memory cell array 1110 and a first through electrode region 1120 for accessing the first memory cell array 1110. The second memory wafer 1200 may include a second memory cell array 1210 and a second through electrode region 1220 for accessing the second memory cell array 1210. The first through electrode region 1120 may refer to a region in which through electrodes for communication between the first memory wafer 1100 and the third memory wafer 1300 are disposed in the first memory wafer 1100. Similarly, the second through electrode region 1220 may refer to a region in which through electrodes for communication between the second memory wafer 1200 and the third memory wafer 1300 are disposed in the second memory wafer 1200. The through-electrodes may provide electrical paths between the first memory wafer 1100 to the third memory wafer 1300.

The first to third memory wafers 1100 to 1300 may be electrically connected to each other through the through electrode. For example, the number of the through electrodes may be hundreds to thousands, and the through electrodes may be arranged in a matrix form. The third memory die 1300 includes a first peripheral circuit 1310 and a second peripheral circuit 1320. The first peripheral circuitry 1310 may include circuitry for accessing the first memory die 1100, and the second peripheral circuitry 1320 may include circuitry for accessing the second memory die 1200. In an exemplary embodiment, each of the first peripheral circuit 1310 and the second peripheral circuit 1320 may be implemented by the method of generating a multiphase clock and the memory device described in fig. 1 to 9.

The memory device according to the exemplary embodiment can be applied to a computing system.

Fig. 11 is a block diagram of a computing system 2000, according to an example embodiment of the inventive concepts. Referring to fig. 11, the computing system 2000 includes at least one volatile memory module (DIMM)2100, at least one non-volatile memory module (NVDIMM)2200, and at least one Central Processing Unit (CPU) 2300.

The computing system 2000 may serve as one of a number of devices, such as a computer, portable computer, Ultra Mobile Personal Computer (UMPC), workstation, data server, netbook, Personal Data Assistant (PDA), web tablet, wireless phone, mobile phone, smart phone, electronic book, Portable Multimedia Player (PMP), digital camera, a digital recorder/player, a digital picture/video recorder/player, a portable game machine, a navigation system, a black box, a 3D television, a device capable of wirelessly transmitting and receiving information, a wearable device, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a Radio Frequency Identification (RFID) device, or one of various electronic devices constituting a computing system.

The at least one non-volatile memory module 2200 may include at least one non-volatile memory. In an exemplary embodiment, the at least one non-volatile memory may include a NAND flash memory, a vertical NAND flash memory (VNAND), a NOR flash memory, a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a spin transfer torque random access memory (STT-RAM), or a Thyristor Random Access Memory (TRAM).

In an exemplary embodiment of the inventive concept, at least one of the volatile memory module 2100 and the non-volatile memory module 2200 is implemented to perform the multi-phase clock generation operation described in fig. 1 to 9.

In an embodiment, the volatile memory module 2100 and the non-volatile memory module 2200 may be connected to the central processing unit 2300 according to a DDRx interface (where x is an integer of 1 or more).

The at least one central processing unit 2300 may be implemented to control the volatile memory module 2100 and the non-volatile memory module 2200. In an exemplary embodiment, the central processing unit 2300 may include a general purpose microprocessor, a multi-core processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or a combination thereof.

The memory device according to the exemplary embodiment may be applied to an automobile system.

Fig. 12 is a block diagram of a vehicle electronic system 3000 according to an exemplary embodiment of the inventive concept. Referring to fig. 12, the vehicle electronic system 3000 includes at least one Electronic Control Unit (ECU)3100, a memory device 3200, a dynamic range sensor (DVS)3300, a display device 3400, and a communication processor 3500.

An Electronic Control Unit (ECU)3100 may be implemented to control the overall operation. The ECU 3100 may process image data received from the DVS 3300. The ECU 3100 may include a Neural Processing Unit (NPU). The NPU may compare the image received from the DVS 3300 with the learning model to quickly derive an optimal image for driving.

Memory device 3200 may be implemented to store a learning model associated with the operation of the NPU. Memory device 3200 may comprise a volatile or non-volatile memory device. For example, memory device 3200 may comprise DRAM or PRAM. In particular, memory device 3200 may perform the multi-phase clock generation operations described with reference to fig. 1-9.

A dynamic range sensor (DVS)3300 may be implemented to sense an environment external to the vehicle. DVS 3300 may output an event signal in response to a change in the relative intensity of light. DVS 3300 may include a pixel array including a plurality of DVS pixels and an address event handler.

The display device 3400 may be implemented to display an image processed by the ECU 3100 or an image transmitted by the communication processor 3500.

The communication processor 3500 may be implemented to transmit the processed image to an external device (e.g., an external vehicle) or receive the image from the external vehicle. For example, the communication processor 3500 may be implemented to perform wired communication or wireless communication with an external device.

Furthermore, at least one embodiment of the present disclosure may be applied to a mobile device.

Fig. 13 is a block diagram of a mobile device 4000 according to an exemplary embodiment of the inventive concept. Referring to fig. 13, a mobile device 4000 includes an application processor 4100, at least one DRAM (e.g., 4210, 4220, etc.), at least one storage device 4300, at least one sensor 4400, a display device 4500, an audio device 4600, a network processor 4700, and at least one input/output (I/O) device 4800. For example, mobile device 4000 may be implemented as a laptop computer, mobile phone, smart phone, tablet Personal Computer (PC), or wearable computer.

The application processor 4100 may be implemented to control the overall operation of the mobile device 4000. The application processor 4100 may execute applications that provide internet browsers, games, and videos. In an exemplary embodiment, the application processors 4100 may include a single core or multiple cores. For example, the application processor 4100 may include multiple cores, such as dual, quad, or quad cores. In an exemplary embodiment, the application processor 4100 may further include a cache memory provided therein or externally.

The application processor 4100 may include a Controller (CNTL)4110, a Neural Processing Unit (NPU)4120, and an Interface (IF) 4130. In an exemplary embodiment, the NPU 4120 is optional and may be omitted.

In an exemplary embodiment, the application processor 4100 is implemented as a system on chip (SoC). A core of an operating system driven on a system on a chip (SoC) may include an input/output (I/O) scheduler and a device driver for controlling the memory device 4300. The device driver may control access performance of the memory device 4300 with reference to the number of synchronization queues managed by the input/output scheduler, or may control a CPU mode or a Dynamic Voltage Frequency Scaling (DVFS) level inside the SoC.

The DRAM 4210 may be connected to the controller 4110. The DRAM 4210 may store data required for the operation of the application processor 4100. For example, the DRAM 4210 may temporarily store an Operating System (OS) and application data, or may be used as an execution space of various software codes. DRAM4220 may be connected to NPU 4120. DRAM4220 may store data associated with Artificial Intelligence (AI) operations.

DRAM 4210 has relatively high latency and Bandwidth (BW) compared to I/O devices or flash memory. DRAM 4210 may be initialized at power-up time of mobile device 4000. When the operating system and application data are loaded, the DRAM 4210 may be used as a place to temporarily store the operating system and application data, or as a space to execute various software codes. The mobile system may perform multitasking operations to load multiple applications simultaneously, and the switching between applications and the execution speed may be used as performance indicators or metrics for the mobile system.

DRAMs 4210 and 4220 may include a multiphase clock generator as described in fig. 1-9 that receives a single phase clock to generate a multiphase clock.

The storage device 4300 may be connected to an interface 4130. In an exemplary embodiment, the interface 4130 may operate using at least one communication protocol among: double Data Rate (DDR), DDR2, DDR3, DDR4, low power DDR (lpddr), Universal Serial Bus (USB), multi-media card (MMC), embedded MMC, Peripheral Component Interconnect (PCI), non-volatile memory express (NVMe), PCI express (PCIe), attached Serial (SATA), Small Computer Small Interface (SCSI), serial attached SCSI (sas), USB attached SCSI (uas), internet SCSI (iscsi), fibre channel, and fibre channel over ethernet (FCoE). In an exemplary embodiment, any one of the storage devices 4300 is included in the mobile device 4000 in an embedded form. In an exemplary embodiment, any one of the storage devices 4300 is removably included in the mobile device 4000.

The storage 4300 may be implemented to store user data. For example, the storage device 4300 may store data or network data collected from the sensor 4400, Augmented Reality (AR)/Virtual Reality (VR) data, and High Definition (HD)4K content. The storage device 4300 may include at least one nonvolatile memory device. For example, the storage 4300 may include a Solid State Drive (SSD) or an embedded multimedia card (eMMC).

In exemplary embodiments, the storage 4300 may be implemented as an additional chip in the application processor 4100, or may be formed as a single package with the application processor 4100. In exemplary embodiments, the storage device 4300 may be mounted using various types of packages. For example, the storage device 4300 may be mounted using an enclosure such as: package on package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), plastic dual in-line package (PDIP), die-in-wafer package (die-in-wafer pack), die-in-wafer form, Chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), small integrated circuit (SOIC), shrink small package (SSOP), thin small package (TSOP), Thin Quad Flat Package (TQFP), System In Package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed package on package (WSP).

Sensor 4400 may be implemented to sense an environment external to mobile device 4000. In an exemplary embodiment, the sensor 4400 includes an image sensor sensing an image. In this case, the sensor 4400 may transmit the generated image information to the application processor 4100. In an exemplary embodiment, the sensor 4400 includes a biosensor that detects biological information. For example, the sensor 4400 may detect a fingerprint, an iris pattern, a blood vessel pattern, a heart rate, or blood glucose, and may generate sensed data corresponding to the sensed information. However, the sensor 4400 is not limited to image sensors and biosensors. For example, the sensor 4400 according to the exemplary embodiment of the present disclosure may include any sensor, such as an illuminance sensor, an acoustic sensor, or an acceleration sensor.

The display device 4500 can be implemented to output data. For example, the display device 4500 may output image data sensed using the sensor 4400, or may output data calculated using the application processor 4100. Audio device 4600 may be implemented to output voice data to an external entity or to sense external voice. The network processor 4700 may be implemented to communicate with an external device through a wired or wireless communication method. Input/output device 4800 can be implemented to input data to mobile device 4000 or to output data from mobile device 4000. The input/output device 4800 may include a device providing digital input and output functions such as a Universal Serial Bus (USB), a storage device, a digital camera, an SD card, a touch screen, a DVD, a modem, or a network adapter.

At least one embodiment of the present disclosure may be applied to various types of computing systems (e.g., CPU/GPU/NPU platforms).

Fig. 14 is a block diagram of a computing system 5000 according to an exemplary embodiment of the inventive concept. Referring to fig. 14, the computing system 5000 includes a Central Processing Unit (CPU)5110, a Graphics Processing Unit (GPU)5120 (e.g., an accelerator), a Neural Processing Unit (NPU), a dedicated processing unit connected to the system bus 5001, a memory device 5210 or a storage device 5220 connected to the system bus 5001, and an input/output (I/O) device 5310, a modem 5320, a network device 5330, or a storage device 5340 connected to the expansion bus 5002. The expansion bus 5002 may be connected to the system bus 5001 through an expansion bus interface 5003.

In an exemplary embodiment, the CPU 5110 includes an on-chip cache 5111, and the GPU5120 includes an on-chip cache 5121. The NPU may also include an on-chip cache. In an exemplary embodiment, the CPU 5110 includes an off-chip cache 5112 and the GPU5120 includes an off-chip cache 5122. Although not shown in FIG. 14, the NPU may also include an off-chip cache. In an exemplary embodiment, the off-chip cache 5112 may be internally connected to the CPU 5110, GPU5120, and NPU through different buses. In an exemplary embodiment, the on-chip cache/off-chip cache includes volatile memories such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), or non-volatile memories such as NAND flash, Phase Random Access Memory (PRAM), and Resistive Random Access Memory (RRAM).

In an exemplary embodiment, the main memory 5114 and the main memory 5124 are connected to the CPU 5110 and the GPU5120 through the respective memory controllers 5113 and 5123. In an embodiment, the main memory may be connected to the NPU through a memory controller. In an exemplary embodiment, the memory 5116 and the memory 5126 may be connected to the CPU 5110 and the GPU5120 through the respective bridge 5115 and the bridge 5125. In an embodiment, the memory may be connected to the NPU through a bridge. The bridge 5115 and the bridge 5125 (or bridges of NPUs) may include memory controllers that control the respective memories 5116 and 5126. In an exemplary embodiment, each of the bridge 5115 and the bridge 5125 (or the bridge of the NPU) may be implemented as a network device, a wireless network device, a switch, a bus, a cloud, or an optical channel.

In an exemplary embodiment, the memories 5124, 5126 include GPU memories. The GPU memory may hold commands and data that interact with the GPU. Commands and data may be copied from main memory or storage. The GPU memory may store image data and have a higher bandwidth than the memory. The GPU memory may separate the clock from the CPU. The GPU may write the image data to the GPU memory after reading the image data from the GPU memory and processing the read image data. The GPU memory may be configured to accelerate graphics processing.

In the exemplary embodiment, memory 5124 and memory 5126 include NPU memory. The NPU memory may be a main memory for storing commands and data that interact with the NPU. Commands and data may be copied from main memory or storage. The NPU memory may hold weight data for the neural network. The bandwidth of the NPU memory may be higher than the memory. The NPU memory may separate the clock from the CPU. During training, the NPU may write the weight data to the NPU memory after reading the weight data from the NPU memory and updating the read weight data. The NPU memory may be configured to accelerate machine learning, such as neural network training and reasoning.

In an exemplary embodiment, each of the memories 5114, 5116, 5124, 5126, and 5210 may be implemented as a memory chip that performs the multiphase clock generation operation described in fig. 1 through 9.

In an exemplary embodiment, the main memory includes a volatile memory such as a DRAM and an SRAM, or a non-volatile memory such as a NAND flash memory, a PRAM, and a RRAM. The main memory has lower latency and lower capacity than each of the memory 5210 and the storage 5220.

The CPU 5110, GPU5120, or NPU may access the memory 5210 and storage 5220 through the system bus 5001. The memory 5210 may be controlled by a memory controller 5211. A memory controller 5211 may be connected to the system bus 5001. The memory device 5220 may be controlled by a memory controller 5221. A memory controller 5221 may be connected to the system bus 5001.

The storage 5220 may be implemented to store data. The memory controller 5221 may be implemented to read data from the memory devices 5220 and transmit the read data to a host. The storage controller 5221 may be implemented to store transmitted data in the storage 5220 in response to host requests. Each of the storage 5220 and the memory controller 5221 may include a buffer that stores metadata, reads a cache to store frequently accessed data, or stores a cache to improve write efficiency. For example, a write cache may receive and process a particular number of write requests. The storage 5220 may include volatile memory such as a Hard Disk Drive (HDD) or non-volatile memory such as NVRAM, SSD, SCM, and new memory.

At least one embodiment of the present disclosure may be applied to a data server system.

Fig. 15 is a block diagram of a data center 7000 to which a memory device according to an exemplary embodiment is applied. Referring to fig. 15, a data center 7000 is a facility for collecting various types of data and providing services, and may also be referred to as a data storage center. Data center 7000 may be a system for managing search engines and databases, and may be a computing system used in a company such as a bank or an organization such as a government agency. Data center 7000 includes application servers 7100 through 7100n and storage servers 7200 through 7200 m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m may vary according to example embodiments, and the number of application servers 7100 to 7100n and storage servers 7200 to 7200m may be different from each other.

The application server 7100 comprises at least one processor 7110 and at least one memory (MEM) 7120. The storage server 7200 includes at least one processor 7210 and at least one memory 7220. By way of example, the processor 7210 can control the overall operation of the storage server 7200 and can access the memory 7220 to execute commands and/or data stored in the memory 7220. The memory 7220 may be a double data rate synchronous dram (ddr sdram), a High Bandwidth Memory (HBM), a hybrid memory multidimensional dataset (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (nvmdimm).

The number of processors 7210 and memory 7220 included in storage server 7200 can vary. In the exemplary embodiment, processor 7210 and memory 7220 provide a processor-memory pair. In an exemplary embodiment, the number of processors 7210 and the number of memories 7220 are different from each other. Processor 7210 may include a single core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. In an exemplary embodiment, the application server 7100 does not include the storage device 7150. Storage server 7200 can include at least one storage device 7250. According to an exemplary embodiment, the number of storage devices 7250 included in storage server 7200 may vary. At least one of the memory devices 7150, 7250, 7150n, and 7150m may be implemented to divide the reference clock and use the divided reference clock as a multi-phase clock, as shown in fig. 1 through 8.

The application servers 7100 to 7100n and the storage servers 7200 to 7200m may communicate with each other through a network 7300. Network 7300 may be implemented using Fibre Channel (FC) or ethernet. The FC may be a medium for relatively high-speed data transmission, and an optical switch may be employed to provide high performance and/or high availability. Storage servers 7200 to 7200m may be provided as file storage, block storage, or object storage, depending on the access method of network 7300.

In an exemplary embodiment, the network 7300 is a Storage Area Network (SAN). For example, the SAN may be a FC-SAN implemented according to a FC protocol (FCP) using a FC network. As another example, the SAN may be an IP-SAN implemented using a TCP/IP network and according to the SCSI over TCP/IP or SCSI over Internet (iSCSI) protocol. In an exemplary embodiment, network 7300 is a general purpose network such as a TCP/IP network. For example, the network 7300 may be implemented according to a protocol such as fc over ethernet (fcoe), Network Attached Storage (NAS), or NVMe over fabric (NVMe-af).

Hereinafter, a description will be given while focusing on the application server 7100 and the storage server 7200. The description of application server 7100 can apply to another application server 7100n, and the description of storage server 7200 can apply to another storage server 7200 m.

The application server 7100 may store data requested to be stored by a user or a client in one of the storage servers 7200 to 7200m through the network 7300. In addition, the application server 7100 can acquire data requested to be read by a user or a client from one of the storage servers 7200 to 7200m through the network 7300. For example, application server 7100 may be implemented as a Web server or a database management system (DBMS).

The application server 7100 can access the memory 7120n or the storage device 7150n included in another application server 7100n through the network 7300, or can access the memories 7220 to 7220m or the storage devices 7250 to 7250m included in the storage servers 7200 to 7200m through the network 7300. Accordingly, application server 7100 may perform various operations on data stored in application servers 7100 through 7100n and/or storage servers 7200 through 7200 m. For example, application server 7100 can run commands to move or copy data between application servers 7100 through 7100n and/or storage servers 7200 through 7200 m. In this case, data may be moved from the storage servers 7200 to 7200m to the storage devices 7250 to 7250m through the memories 7220 to 7220m, or data may be directly moved to the memories 7120 to 7120n of the application servers 7100 to 7100 n. Data moving through the network 7300 may be data encrypted for security or privacy.

In the storage server 7200, an interface (NIC)7254 may provide a physical connection between the processor 7210 and the Controller (CTRL)7251, as well as a physical connection between the NIC 7240 and the controller 7251. For example, interface 7254 may be implemented by a direct attached storage Device (DAS) method in which storage device 7250 is directly connected to a dedicated cable. In addition, for example, the interface 7254 may be implemented in various interface ways, such as Advanced Technology Attachment (ATA), serial ATA (SATA), external SATA (e-SATA), Small Computer System Interface (SCSI), serial attached SCSI (sas), peripheral PCI component interconnect (PCI Express), pcie (nv Express), nvme (nvm Express), IEEE1394, Universal Serial Bus (USB), Secure Digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), universal flash memory (UFS), embedded universal flash memory (ewfs), or Compact Flash (CF) card interfaces.

Storage server 7200 may also include switch 7230 and NIC 7240. The switch 7230 may selectively connect the processor 7210 and the storage device 7250 to each other or may selectively connect the NIC 7240 and the storage device 7250 to each other, under the control of the processor 7210.

In an exemplary embodiment, NIC 7240 may comprise a network interface card or network adapter. The NIC 7240 can be connected to the network 7300 via a wired interface, a wireless interface, a bluetooth interface, or an optical interface. NIC 7240 may include an internal memory, a DSP, or a host bus interface, and may be connected to processor 7210 and/or switch 7230 via the host bus interface. The host bus interface may be implemented as one of the above examples of interface 7254. In an exemplary embodiment, the NIC 7240 can be integrated with at least one of the processor 7210, the switch 7230, and the storage device 7250.

In the storage servers 7200 to 7200m or the application servers 7100 to 7100n, the processor may transmit data to the storage devices 7150 to 7150n and 7250 to 7250m, or transmit a command to the memories 7120 to 7120n and 7220 to 7220m to program or read the data. In this case, the data may be error-corrected by an Error Correction Code (ECC) engine. The data is subject to Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted for security or privacy.

The memory devices 7150 to 7150m and 7250 to 7250m may transmit control signals and command/address signals to the NAND flash memory devices 7252 to 7252m in response to a read command received from the processor. Accordingly, when data is read from the NAND flash memory devices 7252 to 7252m, the read enable signal RE may be input as a data output control signal for outputting the data to the DQ bus. The read enable signal RE may be used to generate the data strobe DQS. The command and address signals may be latched in the page buffer according to a rising edge or a falling edge of the write enable signal WE.

The controller 7251 may control the overall operation of the storage device 7250. In an exemplary embodiment, the controller 7251 includes a Static Random Access Memory (SRAM). The controller 7251 can write data to the NAND flash memory device 7252 in response to a write command, or can read data from the NAND flash memory device 7252 in response to a read command. For example, write commands and/or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100 n. The DRAM 7253 may temporarily store (buffer) data to be written to the NAND flash memory device 7252 or data read from the NAND flash memory device 7252. In addition, DRAM 7253 may store metadata. The metadata is user data or data generated by the controller 7251 to manage the NAND flash memory device 7252. The storage 7250 may include a Secure Element (SE) for security or privacy.

The external clock is divided to generate a divided clock, and the divided clock can be used to overcome the internal frequency limitation of the high-speed DRAM. The divided clock may include four phases that are recovered to the same frequency as the external clock on the output terminals. When a multi-phase clock is used, an offset occurs between the phases. When the divided clock is restored to the same frequency as the external clock, a duty error occurs. Therefore, it is necessary to operate to precisely match the phase relationship between the plurality of phases by 90 degrees. In at least one embodiment of the present disclosure, the duty error of the divided clock is corrected by inputting the divided clock to the duty detector to compensate for the offset between 0 degrees and 180 degrees (or the offset between 90 degrees and 270 degrees). The offset between 0 degrees and 90 degrees can be corrected by a 90 degree phase shift using a ring oscillator for generating a multiphase clock.

A multiphase clock generator according to an exemplary embodiment of the inventive concept includes two duty cycle detectors, a duty cycle corrector, a clock tree, a timing controller, a half phase shift corrector, and a 90-degree phase shifter. In an exemplary embodiment, the 90 degree phase clock is generated using the DLL output signal. In an exemplary embodiment, an offset between 0 degrees and 180 degrees is corrected by adjusting an offset rate of a duty error of a frequency-divided clock, and a 90-degree clock and a 270-degree clock are generated using a 90-degree phase shift of the 0-degree clock. In an exemplary embodiment, the fixed delay line is a minimum delay replicator prior to the variable delay line operation. In an exemplary embodiment, after the DLL is locked (including the first duty cycle error correction DCC0), a 90 degree phase clock is generated and a falling only DCC90 (second duty cycle error correction) may be additionally performed.

In the multi-phase clock generator, the memory device including the same, and the method of generating multi-phase clocks of the memory device according to the exemplary embodiments described above, it is possible to control the duty ratio between multi-phase frequency-divided clocks while performing a DLL operation on a single-phase clock, and thus, it is possible to generate reliable multi-phase clocks even in a small area.

While exemplary embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made to these embodiments without departing from the scope of the inventive concept.