阅读说明：本技术 一种防电流回流的io架构 (IO architecture for preventing current backflow ) 是由 陈冠旭 饶科 韩智毅 张琢 吴明显 满爱宝 于 2021-09-24 设计创作，主要内容包括：本发明涉及一种防电流回流的IO架构,包括了数字输入通道、数字输出通道、第一PMOS管、第一NMOS管和第二NMOS管。数字输入信号通过数字输入通道驱动第一PMOS管和第一NMOS管,第一通道控制信号交替开启数字输入通道和数字输出通道。在PAD输出端存在外界输入信号时,第一PMOS管的衬底电压为PAD输出端电压,在电源电压端与PAD输出端之间不存在可以导通的等效二极管,即电源电压端与PAD输出端之间不存在回流电流。基于此,在数字输入通道和数字输出通道交替开启以满足IO功能的同时,防止回流电流的产生,保证IO电路的正常运行。(The invention relates to an IO (input/output) architecture for preventing current from flowing back, which comprises a digital input channel, a digital output channel, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube. The digital input signal drives the first PMOS tube and the first NMOS tube through the digital input channel, and the first channel control signal alternately opens the digital input channel and the digital output channel. When an external input signal exists at the PAD output end, the substrate voltage of the first PMOS tube is the PAD output end voltage, and an equivalent diode which can be conducted does not exist between the power supply voltage end and the PAD output end, namely, no reflux current exists between the power supply voltage end and the PAD output end. Based on this, when the digital input channel and the digital output channel are alternately opened to satisfy the IO function, the generation of the backflow current is prevented, and the normal operation of the IO circuit is ensured.)

1. An IO architecture that is current backflow resistant, comprising:

the digital input channel is used for respectively accessing a digital input signal and a first channel control signal;

a digital output channel for accessing the first channel control signal;

the grid electrode of the first PMOS tube is used for accessing the digital input signal through the digital input channel, the source electrode of the first PMOS tube is used for connecting a power supply voltage end, the drain electrode of the first PMOS tube is used as a PAD output end, and the substrate of the first PMOS tube is connected with the PAD output end;

the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the first NMOS tube is connected with the PAD output end, and the source electrode of the first NMOS tube is grounded;

a grid electrode of the second NMOS tube is used for being connected with the power supply voltage end, a drain electrode of the second NMOS tube is used for outputting a digital output signal through the digital output channel, a source electrode of the second NMOS tube is connected with the PAD output end, and a substrate of the second NMOS tube is used for being connected with the power supply voltage end;

when the first channel control signal turns on the digital input channel, the digital output channel is turned off; when the first channel control signal turns on the digital output channel, the digital input channel is turned off.

2. The current flow resistant IO architecture of claim 1, further comprising:

the analog signal channel is used for accessing a second channel control signal and transmitting an analog signal to the PAD output end;

wherein the second channel control signal is used to open or close the analog signal channel.

3. The current flow resistant IO architecture of claim 2, wherein the digital input channel and the digital output channel are turned off when the second channel control signal turns on the analog signal channel.

4. The current-backflow-resistant IO architecture of claim 1, wherein the digital input channel comprises:

a grid electrode of the third NMOS tube is used for being connected with the power supply voltage end, a drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, a source electrode of the third NMOS tube is connected with the grid electrode of the first PMOS tube, and the substrate of the third NMOS tube is used for being grounded;

a source electrode of the second PMOS tube is connected with a drain electrode of the third NMOS tube, a drain electrode of the second PMOS tube is connected with a source electrode of the third NMOS tube, a grid electrode of the second PMOS tube is used for accessing the first channel control signal, and a substrate of the second PMOS tube is used for connecting the PAD output end;

and the source electrode of the third PMOS tube is connected with the source electrode of the third NMOS tube, the grid electrode of the third PMOS tube is connected with the power supply voltage end, and the substrate and the drain electrode of the third PMOS tube are connected with the PAD output end.

5. The current flow resistant IO architecture of claim 1, wherein the digital output channel comprises:

a drain electrode of the fourth PMOS tube is connected with a source electrode of the second NMOS tube, a grid electrode of the fourth PMOS tube is used for connecting the power supply voltage end, a substrate of the fourth PMOS tube is used for connecting the PAD output end, and the source electrode of the fourth PMOS tube is used for accessing the first channel control signal;

a grid electrode of the fifth PMOS tube is connected with a source electrode of the fourth PMOS tube, the source electrode is used for being connected with the power supply voltage end, and a drain electrode and the substrate are used for being connected with the PAD output end;

and the grid electrode of the sixth PMOS tube is connected with the power supply voltage end, and the source electrode, the drain electrode and the substrate are connected with the PAD output end.

6. The current flow resistant IO architecture of claim 2, wherein the analog signal path comprises:

a grid electrode of the fourth NMOS tube is used for being connected with the power supply voltage end, and a drain electrode of the fourth NMOS tube is used for being accessed into the second channel control signal;

a gate of the seventh PMOS tube is used for accessing the first channel control signal, a source of the seventh PMOS tube is connected with a drain of the fourth NMOS tube, a drain of the seventh PMOS tube is connected with a source of the fourth NMOS tube, and the substrate is used for connecting the PAD output end;

a grid electrode of the fifth NMOS tube is used for being connected with the power supply voltage end, a source electrode of the fifth NMOS tube is used for being connected with the PAD output end, and the substrate of the fifth NMOS tube is used for being grounded;

a grid electrode of the eighth PMOS tube is connected with the source electrode of the fourth NMOS tube, a source electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube, and a drain electrode of the eighth PMOS tube is connected with the source electrode of the fifth NMOS tube;

and the source electrode of the ninth PMOS tube is connected with the grid electrode of the eighth PMOS tube, the grid electrode of the ninth PMOS tube is used for being connected with the power supply voltage end, and the drain electrode and the substrate of the ninth PMOS tube are used for being connected with the PAD output end.

7. The current backflow prevention IO architecture of claim 4, wherein the digital input channel further comprises:

and the drain electrode of the third NMOS tube is used for forming a signal transmission channel through the first buffer unit.

8. The current backflow prevention IO architecture of claim 4, wherein the digital input channel further comprises:

and the drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube through the second buffer unit.

9. The current flow resistant IO architecture of claim 5 wherein said digital output channel further comprises:

and the drain electrode of the second NMOS tube is used for forming a signal transmission channel through the third buffer unit.

10. The current-backflow-preventing IO architecture of any one of claims 4 to 6, further comprising:

and the fourth buffer unit is used for carrying out buffer processing on the first channel control signal.

Technical Field

The invention relates to the technical field of chip power supplies, in particular to an IO (input/output) framework capable of preventing current from flowing back.

Background

IO (Input/Output) refers to Input and Output, such as IO devices, IO circuits, or IO interfaces. In a usage scenario of a chip, an IO circuit is one of the common circuits. Fig. 1 is a schematic structural diagram of a conventional IO circuit, and as shown in fig. 1, in the conventional IO circuit, a PAD is used as a pin connection portion of a chip, and various electric signals such as current are transmitted through the PAD. As shown in fig. 1, when the chip is not powered on or in the high-voltage input mode, VCC1> VCC, the forward voltage of the parasitic diode of the PMOS transistor is greater than the reverse voltage, when the voltage exceeds a diode voltage threshold, the diode is turned on, the current flows back from VCC1 to VCC, and the current path is as shown in fig. 1. When the return current is large, the chip is hot or misoperation is caused.

Therefore, the traditional IO circuit has the problem of current backflow, and the normal operation of the relevant part of the IO circuit is influenced.

Disclosure of Invention

In view of this, it is necessary to provide an IO architecture for preventing current backflow in order to solve the current backflow problem of the conventional IO circuit.

An IO architecture to prevent current backflow, comprising:

the digital input channel is used for respectively accessing a digital input signal and a first channel control signal;

a digital output channel for accessing the first channel control signal;

the grid electrode of the first PMOS tube is used for accessing the digital input signal through the digital input channel, the source electrode of the first PMOS tube is used for connecting a power supply voltage end, the drain electrode of the first PMOS tube is used as a PAD output end, and the substrate of the first PMOS tube is connected with the PAD output end;

the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the first NMOS tube is connected with the PAD output end, and the source electrode of the first NMOS tube is grounded;

a grid electrode of the second NMOS tube is used for being connected with the power supply voltage end, a drain electrode of the second NMOS tube is used for outputting a digital output signal through the digital output channel, a source electrode of the second NMOS tube is connected with the PAD output end, and a substrate of the second NMOS tube is used for being connected with the power supply voltage end;

when the first channel control signal turns on the digital input channel, the digital output channel is turned off; when the first channel control signal turns on the digital output channel, the digital input channel is turned off.

The IO architecture for preventing current backflow comprises a digital input channel, a digital output channel, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube. The digital input signal drives the first PMOS tube and the first NMOS tube through the digital input channel, and the first channel control signal alternately opens the digital input channel and the digital output channel. When an external input signal exists at the PAD output end, the substrate voltage of the first PMOS tube is the PAD output end voltage, and an equivalent diode which can be conducted does not exist between the power supply voltage end and the PAD output end, namely, no reflux current exists between the power supply voltage end and the PAD output end. Based on this, when the digital input channel and the digital output channel are alternately opened to satisfy the IO function, the generation of the backflow current is prevented, and the normal operation of the IO circuit is ensured.

In one embodiment, the method further comprises the following steps:

the analog signal channel is used for accessing a second channel control signal and transmitting an analog signal to the PAD output end;

wherein the second channel control signal is used to open or close the analog signal channel.

In one embodiment, the digital input channel and the digital output channel are turned off when the second channel control signal turns on the analog signal channel.

In one embodiment, the digital input channel comprises:

a grid electrode of the third NMOS tube is used for being connected with the power supply voltage end, a drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, a source electrode of the third NMOS tube is connected with the grid electrode of the first PMOS tube, and the substrate of the third NMOS tube is used for being grounded;

a source electrode of the second PMOS tube is connected with a drain electrode of the third NMOS tube, a drain electrode of the second PMOS tube is connected with a source electrode of the third NMOS tube, a grid electrode of the second PMOS tube is used for accessing the first channel control signal, and a substrate of the second PMOS tube is used for connecting the PAD output end;

and the source electrode of the third PMOS tube is connected with the source electrode of the third NMOS tube, the grid electrode of the third PMOS tube is connected with the power supply voltage end, and the substrate and the drain electrode of the third PMOS tube are connected with the PAD output end.

In one embodiment, the digital output channel comprises:

a drain electrode of the fourth PMOS tube is connected with a source electrode of the second NMOS tube, a grid electrode of the fourth PMOS tube is used for connecting the power supply voltage end, a substrate of the fourth PMOS tube is used for connecting the PAD output end, and the source electrode of the fourth PMOS tube is used for accessing the first channel control signal;

a grid electrode of the fifth PMOS tube is connected with a source electrode of the fourth PMOS tube, the source electrode is used for being connected with the power supply voltage end, and a drain electrode and the substrate are used for being connected with the PAD output end;

and the grid electrode of the sixth PMOS tube is connected with the power supply voltage end, and the source electrode, the drain electrode and the substrate are connected with the PAD output end.

In one embodiment, the analog signal path includes:

a grid electrode of the fourth NMOS tube is used for being connected with the power supply voltage end, and a drain electrode of the fourth NMOS tube is used for being accessed into the second channel control signal;

a gate of the seventh PMOS tube is used for accessing the first channel control signal, a source of the seventh PMOS tube is connected with a drain of the fourth NMOS tube, a drain of the seventh PMOS tube is connected with a source of the fourth NMOS tube, and the substrate is used for connecting the PAD output end;

a grid electrode of the fifth NMOS tube is used for being connected with the power supply voltage end, a source electrode of the fifth NMOS tube is used for being connected with the PAD output end, and the substrate of the fifth NMOS tube is used for being grounded;

a grid electrode of the eighth PMOS tube is connected with the source electrode of the fourth NMOS tube, a source electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube, and a drain electrode of the eighth PMOS tube is connected with the source electrode of the fifth NMOS tube;

and the source electrode of the ninth PMOS tube is connected with the grid electrode of the eighth PMOS tube, the grid electrode of the ninth PMOS tube is used for being connected with the power supply voltage end, and the drain electrode and the substrate of the ninth PMOS tube are used for being connected with the PAD output end.

In one embodiment, the digital input channel further comprises:

and the drain electrode of the third NMOS tube is used for forming a signal transmission channel through the first buffer unit.

In one embodiment, the digital input channel further comprises:

and the drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube through the second buffer unit.

In one embodiment, the digital output channel further comprises:

and the drain electrode of the second NMOS tube is used for forming a signal transmission channel through the third buffer unit.

In one embodiment, the method further comprises the following steps:

and the fourth buffer unit is used for carrying out buffer processing on the first channel control signal.

Drawings

FIG. 1 is a schematic diagram of a conventional IO circuit;

FIG. 2 is a block diagram of an IO architecture module for preventing current backflow according to an embodiment;

FIG. 3 is a block diagram of an IO architecture module for preventing current backflow according to another embodiment;

fig. 4 is a schematic circuit diagram of an IO architecture for preventing current backflow according to an embodiment.

Detailed Description

For better understanding of the objects, technical solutions and effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and examples. Meanwhile, the following described examples are only for explaining the present invention, and are not intended to limit the present invention.

The embodiment of the invention provides an IO (input/output) framework for preventing current backflow.

Fig. 2 is a block diagram of an IO architecture module for preventing current backflow according to an embodiment, and as shown in fig. 2, an IO architecture for preventing current backflow according to an embodiment includes:

a digital Input channel for respectively accessing a digital Input signal Input _ from _ digital and a first channel control signal Output _ Input _ ctrl;

a digital Output channel, configured to access the first channel control signal Output _ input _ ctrl;

a first PMOS transistor MP1, having a gate connected to the digital Input signal Input _ from _ digital through the digital Input channel, a source connected to a power supply voltage terminal VCC, a drain serving as a PAD output terminal, and a substrate connected to the PAD output terminal;

a first NMOS transistor MN1, the grid of which is connected with the grid of the first PMOS transistor MP1, the drain of which is connected with the PAD output end, and the source of which is grounded VSS;

a second NMOS transistor MN2, having a gate connected to the power supply voltage terminal VCC, a drain for outputting a digital Output signal Output _ to _ digital through the digital Output channel, a source connected to the PAD Output terminal, and a substrate connected to the power supply voltage terminal VCC;

when the first channel control signal Output _ input _ ctrl opens the digital input channel, the digital Output channel is closed; when the first channel control signal Output _ input _ ctrl opens the digital Output channel, the digital input channel is closed.

As shown in fig. 2, the first channel control signal Output _ input _ ctrl is a logic level signal. When the first channel control signal Output _ input _ ctrl is at different logic levels, the digital input channel and the digital Output channel have different on or off states. Taking fig. 2 as an example, the digital Input signal Input _ from _ digital at one side performs channel transmission when the digital Input channel is turned on, and the digital Output channel outputs the digital Output signal Output _ to _ digital at one side when turned on.

In one embodiment, when the first channel control signal Output _ input _ ctrl is at a logic high level, the digital input channel is turned on, and the digital Output channel is turned off. When the first channel control signal Output _ input _ ctrl is at a logic low level, the digital input channel is turned off, and the digital Output channel is turned on.

When the digital Input channel is turned on, the digital Input signal Input _ from _ digital drives the first NMOS transistor MN1 and the first PMOS transistor MP 1. Wherein the PAD output is used for connecting an external electrical device, such as a chip or the like. When the digital Output channel is opened, the external signal is Output as a digital Output signal Output _ to _ digital through the digital Output channel.

The substrate voltage of the first PMOS transistor MP1 is the same as the PAD output terminal voltage, so that there is no equivalent diode capable of conducting forward between the power supply voltage terminal VCC and the PAD output terminal. When the PAD output terminal has external signal backflow, backflow current cannot be formed between the power supply voltage terminal VCC and the PAD output terminal.

In one embodiment, fig. 3 is a block diagram of an IO architecture module for preventing current backflow according to another embodiment, and as shown in fig. 3, the block diagram further includes:

the Analog signal channel is used for accessing a second channel control signal Analog _ sel and transmitting an Analog signal to the PAD output end;

wherein the second channel control signal Analog _ sel is used for turning on or off the Analog signal channel.

And the analog signal channel is used for providing an analog signal path for the PAD output end. Meanwhile, a second channel control signal Analog _ sel is used for turning on or off the Analog signal channel.

In one embodiment, the Analog signal channel further receives a first channel control signal Output _ input _ ctrl, and the first channel control signal Output _ input _ ctrl and the second channel control signal Analog _ sel are implemented according to: when the digital input channel or the digital output channel is opened, the analog signal channel is closed, so that the mutual interference of the analog signal and the digital signal is prevented.

In one embodiment, the digital input channel and the digital output channel are turned off when the Analog signal channel is turned on by the second channel control signal Analog _ sel. And respectively configuring the logic levels of the first channel control signal Output _ input _ ctrl and the second channel control signal Analog _ sel to realize that the digital input channel and the digital Output channel are both in a closed state when the Analog signal channel is opened.

In one embodiment, controlled switches are disposed in the digital input channel, the digital Output channel and the Analog signal channel, and the controlled switches perform turning on or off the channels according to the first channel control signal Output _ input _ ctrl and/or the second channel control signal Analog _ sel. As a preferred embodiment, the controlled switch comprises a semiconductor switching device or an electronic switching device.

Based on this, in one embodiment, fig. 4 is a circuit diagram of an IO architecture for preventing current backflow according to an embodiment, as shown in fig. 4, a digital input channel includes:

a third NMOS transistor MN3, having a gate connected to the power supply voltage terminal VCC, a drain connected to the gate of the first NMOS transistor MN1, a source connected to the gate of the first PMOS transistor MP1, and a substrate for grounding VSS;

a source of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3, a drain of the second PMOS transistor MP2 is connected to the source of the third NMOS transistor MN3, a gate of the second PMOS transistor MP2 is used for receiving the first channel control signal Output _ input _ ctrl, and a substrate of the second PMOS transistor MP2 is used for connecting the PAD Output terminal;

and a source electrode of the third PMOS pipe MP3 is connected with a source electrode of the third NMOS pipe MN3, a grid electrode of the third PMOS pipe MP3 is connected with the power supply voltage terminal VCC, and a substrate and a drain electrode of the third PMOS pipe MP3 are connected with the PAD output end.

In one embodiment, as shown in FIG. 4, the digital output channels include:

a fourth PMOS transistor MP4, having a drain connected to the source of the second NMOS transistor MN2, a gate connected to the power supply voltage terminal VCC, a substrate connected to the PAD Output terminal, and a source connected to the first channel control signal Output _ input _ ctrl;

a gate of the fifth PMOS transistor MP5 is connected to the source of the fourth PMOS transistor MP4, a source of the fifth PMOS transistor MP5 is connected to the power supply voltage terminal VCC, and a drain and a substrate of the fifth PMOS transistor MP5 are connected to the PAD output terminal;

and the grid electrode of the sixth PMOS pipe MP6 is connected with the power supply voltage terminal VCC, and the source electrode, the drain electrode and the substrate are connected with the PAD output end.

In one embodiment, as shown in FIG. 4, the analog signal path includes:

a fourth NMOS transistor MN4, having a gate connected to the supply voltage terminal VCC and a drain connected to the second channel control signal Analog _ sel;

a seventh PMOS transistor MP7, having a gate connected to the first channel control signal Output _ input _ ctrl, a source connected to the drain of the fourth NMOS transistor MN4, a drain connected to the source of the fourth NMOS transistor MN4, and a substrate connected to the PAD Output terminal;

a fifth NMOS transistor MN5, having a gate connected to the power supply voltage terminal VCC, a source connected to the PAD output terminal, and a substrate connected to the ground VSS;

a gate of the eighth PMOS transistor MP8 is connected to the source of the fourth NMOS transistor MN4, a source of the eighth PMOS transistor MP8 is connected to the drain of the fifth NMOS transistor MN5, and a drain of the eighth PMOS transistor MP8 is connected to the source of the fifth NMOS transistor MN 5;

and the source electrode of the ninth PMOS tube MP9 is connected with the grid electrode of the eighth PMOS tube MP8, the grid electrode is used for being connected with the power supply voltage terminal VCC, and the drain electrode and the substrate are used for being connected with the PAD output end.

As shown in fig. 4, the switch control of the digital input channel is shifted back to the gate of the first NMOS transistor MN 1. It should be noted that the digital input channel, the digital output channel and the analog signal channel are all used to establish a controllable signal transmission path, and the positions in an embodiment are all convenient for explaining the signal direction of the path, and do not represent the position limitation of the path control component.

As shown in fig. 4, the first PMOS transistor MP1 and the first NMOS transistor MN1 form a bias circuit, and provide a bias voltage to the base terminal of the PMOS transistor substrate connected to the PAD output terminal. The substrate of each PMOS tube is connected with the PAD output end, namely VSUB is connected with the PAD output end. When the voltage of the PAD output end is higher than the voltage of a power supply voltage end VCC, the sixth PMOS tube MP6 is conducted, and VSUB is equal to the voltage of the PAD output end; when the PAD output terminal voltage is lower than the power supply voltage terminal VCC voltage, the fifth PMOS transistor MP5 is turned on, and VSUB is equal to the power supply voltage terminal VCC voltage.

In one embodiment, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the ninth PMOS transistor MP9 are boost switching transistors, and when the PAD output voltage is higher than the power supply voltage VCC, the gate voltage boost of the PMOS transistor connected to the PAD output is applied to the PAD output voltage.

In one embodiment, when the voltage of the PAD output terminal is higher than the voltage of the power supply voltage terminal VCC, the gate of each PMOS transistor connected with the PAD output terminal and the substrate base terminal are all at the highest level, so as to avoid breakdown of each PMOS transistor.

In one embodiment, when the chip connected to the PAD output terminal is not powered on, but the PAD output terminal receives an external input signal, since the substrate VSUB voltage of each PMOS transistor is the PAD output terminal voltage, no diode capable of conducting in the forward direction exists between the power supply voltage terminal VCC and the PAD output terminal, no backflow current exists between the PAD and the VCC, and no misoperation of the chip occurs.

In one embodiment, as shown in fig. 4, the digital input channel further comprises:

the drain electrode of the third NMOS transistor MN3 is configured to form a signal transmission channel through the first buffer unit.

The first buffer unit may be a buffer or a buffer circuit, and provides a buffering process for the digital Input signal Input _ from _ digital in the path.

In one embodiment, as shown in fig. 4, the digital input channel further comprises:

the drain electrode of the third NMOS transistor MN3 is connected with the gate electrode of the first NMOS transistor MN1 through the second buffer unit.

The second buffer unit may be a buffer or a buffer circuit, and provides a buffering process for the gate signal of the first NMOS transistor MN 1.

In one embodiment, as shown in fig. 4, the digital output channel further comprises:

and the drain electrode of the second NMOS transistor MN2 is used for forming a signal transmission channel through the third buffer unit.

The third buffer unit may be a buffer or a buffer circuit, and provides a buffering process for the digital Output signal Output _ to _ digital in the channel.

In one embodiment, as shown in fig. 4, the method further includes:

and a fourth buffering unit, configured to buffer the first channel control signal Output _ input _ ctrl.

The fourth buffer unit may be a buffer or a buffer circuit.

The IO architecture for preventing current backflow in any of the embodiments above includes a digital input channel, a digital output channel, a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN 2. The digital Input signal Input _ from _ digital drives the first PMOS transistor MP1 and the first NMOS transistor MN1 through the digital Input channel, and the first channel control signal Output _ Input _ ctrl alternately turns on the digital Input channel and the digital Output channel. When an external input signal exists at the PAD output end, the substrate voltage of the first PMOS tube MP1 is the PAD output end voltage, and an equivalent diode which can be conducted does not exist between the power supply voltage end VCC and the PAD output end, namely, no reflux current exists between the power supply voltage end VCC and the PAD output end. Based on this, when the digital input channel and the digital output channel are alternately opened to satisfy the IO function, the generation of the backflow current is prevented, and the normal operation of the IO circuit is ensured.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.