阅读说明：本技术 多栅极晶体管 (Multi-gate transistor ) 是由 拉杜·亚历山德鲁·斯波雷亚 伊娃·拜斯特林克 于 2019-11-29 设计创作，主要内容包括：公开了一种多栅极晶体管,包括源极、与源极间隔开的漏极、设置在源极和漏极之间的半导体区域以及设置在半导体区域之上的绝缘区域。多栅极晶体管还包括：电流控制栅极,用于根据施加到电流控制栅极的第一电场来控制通过半导体区域在源极和漏极之间流动的电流的大小,电流控制栅极通过半导体区域和绝缘区域与源极分离；以及开关栅极,用于根据施加到开关栅极的第二电场来允许电流通过半导体区域在源极和漏极之间流动。可以通过改变施加到开关栅极的第二电场来控制晶体管的导电状态(即导通/关断),而可以通过改变施加到电流控制栅极的第一电场来设置通过多栅极晶体管的电流的大小。(A multi-gate transistor is disclosed that includes a source, a drain spaced apart from the source, a semiconductor region disposed between the source and the drain, and an insulating region disposed over the semiconductor region. The multi-gate transistor further includes: a current control gate for controlling a magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switching gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switching gate. The conduction state (i.e., on/off) of the transistor can be controlled by varying the second electric field applied to the switch gate, while the magnitude of the current through the multi-gate transistor can be set by varying the first electric field applied to the current control gate.)

1. A multi-gate transistor, comprising:

a source electrode;

a drain spaced from the source;

a semiconductor region disposed between the source and the drain;

an insulating region disposed over the semiconductor region;

a current control gate for controlling the magnitude of a current flowing between the source and the drain through the semiconductor region in accordance with a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and

a switching gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switching gate.

2. The multi-gate transistor of claim 1, wherein the drain is laterally spaced from the source, the semiconductor region is disposed over the source and the drain, and the current control gate and the switch gate are disposed on an opposite side of the semiconductor region from the source and the drain.

3. The multi-gate transistor of claim 2, wherein the current control gate and the switch gate are disposed at the same height above the source and drain, wherein the current control gate or the switch gate further comprises a portion that extends over a gap separating the current control gate from the switch gate.

4. The multi-gate transistor of claim 3, wherein the current control gate or the portion of the switch gate extends at least to the same lateral position as an adjacent edge of the other of the current control gate and the switch gate, and

wherein the portion of the current control gate or the switch gate is longitudinally separated from the edge of the other of the current control gate and the switch gate.

5. The multi-gate transistor of claim 2, wherein the current control gate is longitudinally offset from the switch gate.

6. The multi-gate transistor of claim 5, wherein the current control gate extends laterally at least to an edge of the switch gate, the current control gate being separated longitudinally from the switch gate by an electrically insulating region.

7. The multi-gate transistor of any preceding claim, wherein the switching gate is arranged to cause a conductive layer to be created in a portion of the semiconductor region between the source and drain when the second electric field is applied to the switching gate.

8. The multi-gate transistor of claim 1, further comprising:

a gate terminal disposed over at least a portion of the current control gate and at least a portion of the switch gate,

wherein a third electric field sufficient to generate the first and second electric fields is applied to the gate terminal, and wherein the current control gate and the switch gate act as floating gates.

9. The multi-gate transistor of claim 8, wherein the gate terminal extends across a length of the current control gate and the switch gate.

10. The multi-gate transistor of any of the preceding claims, comprising:

a plurality of switching gates including the switching gate,

wherein each of the plurality of switch gates is electrically isolated from others of the plurality of switch gates such that current is allowed to flow between the source and drain through the semiconductor region only when a voltage applied to each of the plurality of switch gates is equal to or greater than a respective switch threshold voltage of that one of the plurality of switch gates.

11. The multi-gate transistor of claim 10, further comprising:

a plurality of inputs, each input connected to a respective switch gate of the plurality of switch gates; and

an output connected to the drain such that the multi-gate transistor is configured to perform an AND function by allowing current to flow at the output only if the voltage at all of the plurality of inputs is equal to or greater than a switching threshold voltage.

12. The multi-gate transistor of any of claims 1 to 9, comprising:

a plurality of current control gates including the current control gate,

wherein the plurality of current control gates are spaced apart from one another in a direction parallel to an edge of the source adjacent to a channel between the source and the drain, and are each configured to receive a respective one of a plurality of input voltages such that a magnitude of a current flowing between the source and the drain is dependent on the plurality of input voltages.

13. The multi-gate transistor of claim 12, wherein each of the plurality of current control gates is configured to receive a respective digit of an input digital codeword comprising a plurality of digits such that the multi-gate transistor is configured to convert the input digital codeword into an analog output current at the drain.

14. The multi-gate transistor of claim 13, wherein the plurality of digits of the input digital codeword comprises n bits, and the multi-gate transistor comprises n current control gates, each current control gate having a different overlap area with the source, and

wherein the overlapping area of the current control gates increases following a geometric progression of a common ratio r-2 from the first current control gate to the nth current control gate.

15. The multi-gate transistor of any preceding claim, wherein the semiconductor region comprises:

a first doped region between the source and the first gate; and

a second doped region disposed in a channel between the source and the drain.

16. The multi-gate transistor of claim 15, wherein the first doped region is configured to operate in a normally-on mode and the second doped region is configured to operate in a normally-off mode, or

Wherein the first doped region is configured to operate in a normally off mode and the second doped region is configured to operate in a normally on mode.

17. The multi-gate transistor of any of the preceding claims, comprising:

an auxiliary gate disposed on an opposite side of the semiconductor region from the switching gate, wherein a threshold electric field of the switching gate that allows current to flow between the source and the drain depends on an electric field applied to the auxiliary gate.

18. The multi-gate transistor of any of the preceding claims, comprising:

a field mitigation element configured to extend beyond an edge of the source closest to the drain in a direction towards the drain so as to at least partially shield the source from an electric field in a channel between the source and the drain.

19. The multi-gate transistor of any one of the preceding claims, wherein the first and/or second electric field is an applied voltage, or an electric field generated via the photovoltaic effect by incident electromagnetic radiation, or an electric field generated by chemisorption.

20. A method of operating a multi-gate transistor, the multi-gate transistor comprising: a source electrode; a drain spaced apart from the source; a semiconductor region disposed between the source and the drain; an insulating region disposed over the semiconductor region; a current control gate for controlling a magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied thereto, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switching gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switching gate, the method comprising:

applying the second electric field to the switching gate to allow current to flow in the semiconductor region between the source and the drain; and

controlling a magnitude of a current flowing in the semiconductor region between the source and the drain using the current control gate.

21. The method of claim 20, wherein the second electric field applied is greater than or equal to a threshold switching electric field.

22. The method of claim 21, wherein controlling the magnitude of the current using the current control gate comprises: applying the first electric field to the current control gate, and

wherein the multi-gate transistor is subsequently turned on by increasing the second electric field applied to the switching gate to at least the threshold switching electric field.

23. The method of claim 20, 21 or 22, wherein the multi-gate transistor comprises a plurality of switch gates including the switch gate, each of the plurality of switch gates being electrically isolated from others of the plurality of switch gates such that current is allowed to flow between the source and the drain through the semiconductor region only when a respective second electric field applied to each of the plurality of switch gates is equal to or greater than a respective switch electric field of that of the plurality of switch gates, the method further comprising:

applying a respective second electric field to each of the plurality of switching gates that is greater than or equal to a respective threshold switching electric field.

24. The method of claim 23, wherein each input of a plurality of inputs is connected to a respective switching gate of the plurality of switching gates and an output is connected to the drain, such that the multi-gate transistor is configured to perform an and function by allowing current to flow at the output only if the respective second electric field at all of the plurality of inputs is equal to or greater than the respective switching electric field.

25. The method of any one of claims 20 to 24, wherein the first and/or second electric field is an applied voltage, or an electric field generated via the photovoltaic effect by incident electromagnetic radiation, or an electric field generated by chemisorption.

Technical Field

The present invention relates to semiconductor transistor technology. More particularly, the present invention relates to a transistor including a source, a drain, and a plurality of gates.

Background

Printing electronic devices on flexible substrates has received increasing attention, particularly for large area electronic devices such as display technology, sensors, wearable devices, and other applications where roll-to-roll manufacturing would allow for fast, cost-effective manufacturing. However, several limitations have been encountered, most notably poor device performance under electrical stress, which typically limits circuit speed to hundreds of kilohertz (kHz).

Transistors have been developed in which the source contact contains a potential barrier, such as a schottky contact, the gate overlaps the source, and the semiconductor is thin enough to allow a voltage applied to the drain contact to fully deplete free carriers at the source edge of the semiconductor. Such transistors are commonly referred to as Source-gated transistors (SGTs). Compared to conventional field effect thin film transistors (FET TFTs), SGTs offer several advantages, including lower operating voltages, reduced power consumption, and high gain due to low output conductance.

These advantages make SGTs particularly well suited for use in large area flexible electronics where current uniformity is required. However, one significant drawback of the SGT design is its speed. Since its drain current is lower compared to a FET or other type of TFT, the transconductance decreases, which in turn affects the operating frequency and limits the SGT to switching speeds much lower than those of TFTs of the same geometry. Therefore, SGTs are not suitable for Radio Frequency (RF) and other high speed applications. Therefore, there is a need in the art for a transistor that provides the benefits of an SGT with faster switching speeds.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a multi-gate transistor comprising: a source electrode; a drain spaced apart from the source; a semiconductor region disposed between the source and the drain; an insulating region disposed over the semiconductor region; a current control gate for controlling a magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switching gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switching gate.

In some embodiments according to the first aspect, the drain is laterally spaced from the source, the semiconductor region is disposed over the source and the drain, and the current control gate and the switching gate are disposed on an opposite side of the semiconductor region from the source and the drain.

In some embodiments according to the first aspect, the current control gate and the switch gate are disposed at the same height above the source and the drain, wherein the current control gate or the switch gate further comprises a portion extending above a gap separating the current control gate from the switch gate.

In some embodiments according to the first aspect, the portion of the current control gate or the switch gate extends at least to the same lateral position as an adjacent edge of the other of the current control gate and the switch gate, and the portion of the current control gate or the switch gate is longitudinally separated from the edge of the other of the current control gate and the switch gate.

In some embodiments according to the first aspect, the current control gate is longitudinally offset from the switch gate.

In some embodiments according to the first aspect, the current control gate extends laterally at least to an edge of the switching gate, the current control gate being longitudinally separated from the switching gate by an electrically insulating region.

In some embodiments according to the first aspect, the switching gate is arranged to cause a conductive layer to be created in a portion of the semiconductor region between the source and drain when the second electric field is applied to the switching gate.

In some embodiments according to the first aspect, the multi-gate transistor further comprises a gate terminal disposed over at least a portion of the current control gate and at least a portion of the switch gate, wherein a third electric field sufficient to generate the first and second electric fields is applied to the gate terminal, and wherein the current control gate and the switch gate act as floating gates.

In some embodiments according to the first aspect, the gate terminal extends across the length of the current control gate and the switch gate.

In some embodiments according to the first aspect, the multi-gate transistor comprises a plurality of switching gates including the switching gate, wherein each switching gate of the plurality of switching gates is electrically isolated from other switching gates of the plurality of switching gates such that current is allowed to flow between the source and the drain through the semiconductor region only when a voltage applied to each switching gate of the plurality of switching gates is equal to or greater than a respective switching threshold voltage of the switching gate of the plurality of switching gates.

In some embodiments according to the first aspect, the multi-gate transistor further comprises: a plurality of inputs, each input connected to a respective switch gate of the plurality of switch gates; and an output connected to the drain such that the multi-gate transistor is configured to perform an and function by allowing current to flow at the output only if the voltage at all of the plurality of inputs is equal to or greater than the switching threshold voltage.

In some embodiments according to the first aspect, the multi-gate transistor comprises a plurality of current control gates including the current control gate, wherein the plurality of current control gates are spaced apart from each other in a direction parallel to an edge of the source adjacent to a channel between the source and the drain, and are each configured to receive a respective input voltage of a plurality of input voltages such that a magnitude of a current flowing between the source and the drain depends on the plurality of input voltages.

In some embodiments according to the first aspect, each of the plurality of current control gates is configured to receive a respective digit of an input digital codeword comprising a plurality of digits, such that the multi-gate transistor is configured to convert the input digital codeword into an analog output current at the drain.

In some embodiments according to the first aspect, the plurality of digits of the input digital codeword comprises n bits, and the multi-gate transistor comprises n current control gates, each having a different area of overlap with the source, and wherein the area of overlap of the current control gates increases from the first current control gate to the nth current control gate following a geometric progression having a common ratio r-2.

In some embodiments according to the first aspect, the semiconductor region comprises: a first doped region between the source and the first gate; and a second doped region disposed in the channel between the source and the drain.

In some embodiments according to the first aspect, the first doped region is configured to operate in a normally-on mode and the second doped region is configured to operate in a normally-off mode, or the first doped region is configured to operate in a normally-off mode and the second doped region is configured to operate in a normally-on mode.

In some embodiments according to the first aspect, the multi-gate transistor comprises an auxiliary gate disposed on an opposite side of the semiconductor region from the switching gate, wherein a threshold voltage at which the switching gate allows current to flow between the source and the drain is dependent on a voltage applied to the auxiliary gate.

In some embodiments according to the first aspect, the multi-gate transistor comprises a field mitigation element configured to extend beyond an edge of the source closest to the drain in a direction towards the drain, so as to at least partially shield the source from an electric field in a channel between the source and the drain.

In some embodiments according to the first aspect, the first electric field and/or the second electric field is an applied voltage, or an electric field generated via the photovoltaic effect by incident electromagnetic radiation, or an electric field generated by chemisorption.

According to a second aspect of the present invention, there is provided a method of operating a multi-gate transistor, the multi-gate transistor comprising: a source electrode; a drain spaced apart from the source; a semiconductor region disposed between the source and the drain; an insulating region disposed over the semiconductor region; a current control gate for controlling a magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switching gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switching gate, the method comprising: applying a second electric field to the switching gate to allow current to flow in the semiconductor region between the source and the drain; and controlling a magnitude of a current flowing in the semiconductor region between the source and the drain using the current control gate.

In some embodiments according to the second aspect, the applied second electric field is greater than or equal to the threshold switching electric field.

In some embodiments according to the second aspect, controlling the magnitude of the current using the current control gate comprises: a first electric field is applied to the current control gate and the multi-gate transistor is subsequently turned on by increasing a second electric field applied to the switching gate to at least the threshold switching electric field.

In some embodiments according to the second aspect, the multi-gate transistor comprises a plurality of switching gates including the switching gate, each of the plurality of switching gates being electrically isolated from others of the plurality of switching gates such that current is allowed to flow between the source and the drain through the semiconductor region only when the respective second electric field applied to each of the plurality of switching gates is equal to or greater than the respective switching electric field of the switching gate of the plurality of switching gates, the method further comprising: a respective second electric field greater than or equal to a respective threshold switching electric field is applied to each of the plurality of switching gates.

In some embodiments according to the second aspect, each of the plurality of inputs is connected to a respective switch gate of the plurality of switch gates and the output is connected to the drain, such that the multi-gate transistor is configured to perform the and function by allowing current to flow at the output only if the respective second electric field at all of the plurality of inputs is equal to or greater than the respective switch electric field. In addition, the magnitude of the output current can be controlled by varying the first electric field applied to the current control gate.

In some embodiments according to the second aspect, the first electric field and/or the second electric field is an applied voltage, or an electric field generated via the photovoltaic effect by incident electromagnetic radiation, or an electric field generated by chemisorption.

Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 illustrates a multi-gate transistor including a current control gate and a switch gate according to an embodiment of the present invention;

FIG. 2 shows examples of mode I and mode II currents in a multi-gate transistor operating in a mode similar to a Source Gated Transistor (SGT) according to embodiments of the present invention;

FIG. 3 illustrates a multi-gate transistor including a current control gate longitudinally offset from a switch gate in accordance with an embodiment of the present invention;

FIG. 4 shows a timing diagram illustrating the voltage ramp on the current control gate of a multi-gate transistor before switching the transistor abruptly by increasing the voltage on the switching gate, in accordance with an embodiment of the present invention;

FIG. 5 is a graph comparing the transient response of a multi-gate transistor according to an embodiment of the invention with the transient response of an SGT and a Field Effect Transistor (FET) having similar device geometries;

FIG. 6 shows a multi-floating gate transistor including two floating gates, according to an embodiment of the present invention;

FIG. 7 shows an example of a Floating Gate (FG) SGT;

fig. 8 is a diagram showing an example of output characteristics of an SGT and an FG SGT according to an embodiment of the present invention;

fig. 9 is a graph comparing output characteristics of a floating gate multi-gate transistor (FG MGT) with examples of SGT and FG SGT according to an embodiment of the present invention;

FIG. 10 shows a multi-gate transistor including multiple switch gates, according to an embodiment of the invention;

FIG. 11 shows a multi-gate transistor including multiple switch gates, according to an embodiment of the invention;

FIG. 12 illustrates a multi-gate transistor including multiple switch gates disposed at different heights above a source-drain gap, according to an embodiment of the invention;

fig. 13 shows a multi-gate transistor according to an embodiment of the invention comprising a first doped region and a second doped region extending across the entire thickness of the semiconductor region;

FIG. 14 shows a multi-gate transistor according to an embodiment of the invention comprising a first doped region and a second doped region extending partially across a semiconductor region;

figure 15 shows a multi-gate transistor according to an embodiment of the invention comprising doped regions extending across the source and channel and extending across the entire thickness of the semiconductor region;

figure 16 shows a multi-gate transistor according to an embodiment of the invention comprising a doped region extending across the source and channel and extending partially across the semiconductor region;

FIG. 17 shows a multi-gate transistor according to an embodiment of the invention, including an auxiliary gate electrode disposed on an opposite side of the channel from the switch gate;

FIG. 18 illustrates a multi-gate transistor including field relief structures in the source and drain, according to an embodiment of the invention;

FIG. 19 shows a multi-gate transistor including field-relief electrodes according to an embodiment of the invention;

FIG. 20 illustrates a multi-gate transistor including a tunnel layer disposed between a source and a semiconductor region, according to an embodiment of the present invention;

FIG. 21 illustrates a multi-gate transistor including a potential barrier formed by doping a semiconductor region over a source, according to an embodiment of the invention;

figure 22 shows a multi-gate transistor according to an embodiment of the invention comprising a heterostructure barrier formed of a second semiconductor material disposed between the source and the semiconductor region;

FIG. 23 shows a multi-gate transistor including a switching gate electrode and a floating current control gate, according to an embodiment of the invention;

FIG. 24 shows a multi-gate transistor including multiple input terminals disposed over a floating current control gate, according to an embodiment of the invention;

FIG. 25 illustrates a multi-gate transistor including multiple current control gates having different overlap areas with a source, according to an embodiment of the invention;

fig. 26 shows a multi-gate transistor according to an embodiment of the invention, in which the drain is provided on the opposite side of the semiconductor region to the source;

fig. 27 shows a multi-gate transistor according to an example, wherein the current control gate and the switching gate are disposed on the same side of the semiconductor region as the source and drain; and is

Fig. 28 shows a multi-gate transistor according to an example, which includes a semiconductor region in the form of a nanowire.

Detailed Description

In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As will be realized by those skilled in the art, the described embodiments can be modified in various different ways, all without departing from the scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. Like reference numerals designate like elements throughout the specification.

For convenience, in the following description, various device geometries according to embodiments of the present invention are described with respect to the devices in the orientations shown in the figures. Where terms such as "above," "over," "lateral," "vertical," and the like are used in the description, these should not be construed as implying that such embodiments are limited to the particular orientations shown in the figures. It should be readily understood that the devices described herein will function properly regardless of the physical orientation of the device or the physical orientation of the apparatus in which the device is included, and the following description should be construed accordingly. In addition, transistors according to embodiments of the present invention include a semiconductor region, which may include a semiconductor, a semi-metal or a degenerately doped semiconductor, or a combination thereof. Accordingly, reference herein to "semiconductor regions" should be construed accordingly.

Referring now to fig. 1, a multi-gate transistor including a current control gate and a switch gate is shown, according to an embodiment of the present invention. The multi-gate transistor 100 includes a source 101, a drain 102, a first gate 103, and a second gate 104. The source 101 and drain 102 are spaced apart from each other and separated by a semiconductor region 105. In other words, the source 101 and the drain 102 are separated by the semiconductor region 105. The contact between the source 101 and the semiconductor 105 comprises a potential barrier. The potential barrier between the source 101 and the semiconductor 105 may be provided, for example, by selecting suitable materials for the source 101 and the semiconductor region 105, by doping the material of the source 101 and/or the semiconductor region 105, or by forming a heterojunction contact between two or more semiconductor materials.

The source 101, drain 102, first gate 103, second gate 104, and semiconductor region 105 may each be formed of any suitable material or combination of materials. Examples of materials that may be used for the source 101, drain 102, first gate 103, and/or second gate 104 include, but are not limited to: a metal; a conductive or semiconductive metal oxide; a conductive or semiconductive polymer; doping the semiconductor; graphene; and two-dimensional (2D) semiconductors. Examples of materials that may be used for the semiconductor region 105 include, but are not limited to: crystalline or amorphous silicon; a semiconductor metal oxide; a transition metal chalcogenide compound; graphene; a carbon nanotube; a semiconductor nanowire; an organic semiconductor; and 2D semiconductors.

The first gate 103 is disposed over at least a portion of the source 101 and is separated from the source 101 by a semiconductor region 105 and by an electrical insulator 106 disposed over the semiconductor region 105. Electrical insulator 106 may be generally referred to as an "isolation region" and may comprise the same material throughout the device or may comprise different insulating materials in different portions of the device. The region of semiconductor material 105 above source 101 may be referred to as a "source region" of semiconductor 105. When a potential difference larger than a certain threshold is applied to the first gate 103, an accumulation layer is formed in the source region at the interface between the semiconductor 105 and the insulator 106. Similarly, the second gate 104 is disposed over the gap 107 between the source 101 and drain 102 and is separated from the source 101 and drain 102 by the semiconductor region 105 and by the electrical insulator 106. The second gate 104 may or may not vertically overlap the drain 102, depending on the embodiment. When a potential difference greater than a certain threshold is applied to the second gate 104, an accumulation layer is formed in a gap 107 (also referred to as a "source-drain gap" or "channel" 107) between the source 101 and the drain 102 at the interface between the semiconductor 105 and the insulator 106.

In this embodiment, the applied electric field on the second gate 104 is an applied voltage. However, in another embodiment, the applied electric field on the second gate 104 may be an electric field generated by incident electromagnetic radiation via the photovoltaic effect. Thus, the transistor can operate as a phototransistor. Similarly, the electric field applied to the first gate 103 may be either an applied voltage or an electric field generated via the photovoltaic effect by incident electromagnetic radiation.

As another alternative, in some embodiments, the electric field applied to the first gate 103 and/or the second gate 104 may be generated via a chemical reaction (such as adsorption of molecules on the surface of the first gate 103 or the second gate 104). Such embodiments may be used in sensor applications, as the absence/presence of an output current or its magnitude may indicate the presence or absence of a particular chemical species that can be adsorbed onto the surface of the first gate 103 or the second gate 104. When using chemisorption to generate an electric field in a floating gate embodiment, such as those described below with reference to fig. 6 and 23, chemisorption may occur at the control gate over the floating first and/or second gates, resulting in an electric field being generated across the floating first and/or second gates.

In some embodiments, the multi-gate transistor 100 may include an interfacial layer between the source 101 and the semiconductor region 105 for controlling the characteristics of the barrier. For example, the interfacial layer may be formed by depositing a different material over the source 101 prior to depositing the semiconductor region 105, or by doping a surface region of the source 101. As another example, in some embodiments, the interfacial layer may be formed by processing the source material prior to depositing the semiconductor region 105 (e.g., by oxidizing the surface of the source 101 prior to depositing the semiconductor region 105, or applying a suitable chemical process to alter the surface chemistry of the source material).

In some embodiments, the source 101 may not directly overlap the first gate 103, but rather a region of the semiconductor 105 on one side of the source 101 may be doped to provide a region that overlaps the first gate 103. As another alternative, in some embodiments, a different material (e.g., another metal) may be deposited to one side of the source metallization 101 in the direction of the drain 102, and the first gate 103 may be formed over and overlap this region of the other material adjacent to the source 101.

In the present embodiment, the source electrode 101 and the drain electrode 102 are arranged such that when a potential difference larger than a certain threshold value is applied across the source electrode 101 and the drain electrode 102, a depletion layer is formed in the semiconductor region 105 adjacent to the source electrode 101 across the entire cross section of the semiconductor layer 105 at the edge of the source electrode 101 closest to the drain electrode 102. In the present embodiment, the source 101 comprises a single continuous layer, but in other embodiments the source 101 may comprise a plurality of separate portions electrically connected in parallel with the semiconductor region 105. In some embodiments, a depletion layer may not be formed across the entire cross-section of semiconductor layer 105, although device performance may be compromised as a result of the increase in saturation voltage and the reduction in intrinsic gain. In contrast to embodiments of the present invention, which function in a manner similar to an SGT by forming a depletion region at the edge of the source 101, which allows for source pinch-off, field effect transistors use the field effect to modulate the current and a depletion region can be formed at the drain edge so that pinch-off occurs at the drain. In general, a transistor according to embodiments of the invention may be configured to allow source pinch-off by forming a depletion region at the edge of the source 101 closest to the drain 102.

The first gate 103 and the second gate 104 together are configured such that a continuous conductive layer is created at the interface between the semiconductor region 105 and the insulator 106. In the present embodiment, the conductive layer is an accumulation layer, but in other embodiments, an inversion layer may be formed as the conductive layer. In this context, "continuous" means that the conductive layer extends from the drain electrode 102, across the gap 107 between the source and drain electrodes 101, 102, and over at least a portion of the source electrode 101. The conductive layer thus provides a path for current to flow between the source 101 and drain 102 in the semiconductor region 105. In this way, the multi-gate transistor 100 functions in a similar manner as a conventional SGT when the correct voltages are applied to both the first gate 103 and the second gate 104.

The operation of the multi-gate transistor 100 of fig. 1 may be understood with reference to the mode I current and the mode II current shown in fig. 2. The diagram in fig. 2 shows an example of a multi-gate transistor 100 according to an embodiment of the present invention when operating in a similar mode as the SGT. This mode of operation of the multi-gate transistor 100 may be referred to as a "SGT-like" mode. In the SGT-like mode of operation, there are two different current modes due to the source pinch-off effect. Mode I Current I₁Determined by the electric field in the depletion region 205a at the tip of the source 101. This may be referred to as a high field mode. Mode I current has a high temperature coefficient and a high electric field dependence.

Mode II Current I₂Implanted along the remaining length of the source 101 (i.e., away from the source-drain gap) and encounters resistance in the horizontal accumulation layer 205b as it travels through the semiconductor 105 along the length of the source 101. It will be appreciated that in practice, charge is injected along the source 101 and the movement of these charges is referred to as the mode II current I₂. Therefore, reference to current "injection" should be construed accordingly. When a mode II current is injected from the source contact 101 and passes through the semiconductor 105, it also encounters resistance vertically, so the mode II current is essentially that ofMeasured in ohms. Thus, subject to proper device design in terms of selection of materials and layer thicknesses, the mode II current scales linearly with the voltage applied to the first gate 103. The total current I flowing into the drain 102_DEqual to the sum of the mode I and mode II currents, i.e. I_D＝(I₁+I₂)。

As described above, in the present embodiment, the multi-gate transistor 100 functions in a similar manner to the conventional SGT when the correct voltages are applied to both the first gate 103 and the second gate 104. Unlike a conventional SGT, however, the multi-gate transistor 100 of the present embodiment includes a plurality of gates 103, 104. The magnitude of the mode I and mode II currents can be controlled by varying the electric field applied to the first gate 103 (e.g., by varying the voltage applied to the first gate 103). By providing a first gate 103 and a second gate 104 as shown in fig. 1 and 2, the first gate 103 may be used to control the injection from the source electrode 101, while the second gate 104 may be used to control the conducting channel between the source 101 and the drain 102. Therefore, the first gate 103 is hereinafter referred to as a "current control gate", and the second gate 104 is hereinafter referred to as a "switching gate".

Furthermore, by properly designing the current control gate 103 to shield the source 101 from the electric field generated by the switching gate 104, the coupling of the switching gate 104 to the source 101 can be reduced. For example, in the present embodiment, the current control gate 103 includes an extension portion 103a, and the extension portion 103a overhangs the gap between the current control gate 103 and the switch gate 104. The extension 103a is used to keep the source 101 away from the influence 104 of the switching gate. Since the current control gate 103 is separated from the switching gate 104 by the insulator 106, different voltages can be applied to the current control gate 103 and the switching gate 104, and the current control gate 103 can electrically shield the source 101 from a potential difference applied to the switching gate 104. In this way, device operation may be improved since the drain 102 voltage and the switch gate 104 voltage will not affect the amount of current injected. When a voltage is applied to the switching gate 104, current is allowed to flow in the semiconductor region 105 in the gap 107 between the source 101 and the drain 102. This may be considered as switching the transistor from "off" to "on" and thus the second gate 104 may be referred to as a "switching gate". Meanwhile, the magnitude of the current flowing between the source 101 and the drain 102 is determined by the potential applied to the current control gate 103.

Since the current flowing between the source 101 and drain 102 is linearly proportional to the current control gate 103 voltage, the multi-gate transistor 100 can be considered to behave as a linear variable resistor or a linear voltage controlled current source with integrated switches in a single device. If the switching gate 104 is "on", meaning that the voltage applied to the switching gate 104 is above a certain threshold and the voltage on the current control gate 103 is also below the corresponding threshold of the current control gate 103, then the device remains "off" and no current will flow between the source 101 and drain 102. Thus, the switch gate 104 controls the on/off behavior, and the current control gate 103 controls the device as a linear current source when the transistor 100 is in the "on" state.

Thus, by providing separate current control gate 103 and switch gate 104, the conduction state (on/off) of the device can be controlled in one portion of the device (i.e., by varying the voltage applied to switch gate 104), while the magnitude of the current through the multi-gate transistor 100 can be set in a separate portion of the device (i.e., by varying the voltage applied to current control gate 103).

In some embodiments, the transistor 100 may operate in a "sub-threshold" state in which the voltage applied to the switch gate 104 is less than a threshold voltage. Although transistor 100 may not be considered "fully on" in this state, some current may still flow between source 101 and drain 102 at voltages near the threshold voltage. In this region of the I-V curve of the transistor 100, the drain current I_DVaries exponentially with the voltage applied to the switching gate 104.

In the embodiment shown in fig. 1, the drain 102 is laterally spaced from the source 101, the semiconductor region 105 is disposed over the source 101 and drain 102, and the current control gate 103 and switch gate 104 are disposed on an opposite side of the semiconductor region 105 from the source 101 and drain 102. However, in other embodiments, different device geometries are possible. For example, in some embodiments, the drain may be disposed above the source, and the control gate and the switching gate may be disposed to one side of the source and the drain.

In the present embodiment, the current control gate 103 and the switching gate 104 are disposed at the same height above the source 101 and the drain 102. To keep the two gates separated, the current control gate 103 and the switch gate 104 are spaced apart from each other and separated by an electrical insulator 106. In addition, to achieve a continuous electric field across the source 101 and source-drain gap 107, the current control gate 103 includes a portion 103a, the portion 103a extending over the gap separating the current control gate 103 from the switch gate 104. In other embodiments, a similar extension may be formed by the switch gate 104 instead of the current control gate 103. However, it may be advantageous to form extension 103a as part of current control gate 103 (rather than switch gate 104), because extension 103a formed by current control gate 103 may help keep source 101 clear of switch gate 104, as explained above.

As shown in fig. 1, portions of the current control gate 103 or the switch gate 104 may extend at least to the same lateral position as the adjacent edge of the other of the current control gate 103 and the switch gate 104, such that a continuous electric field may be maintained over the source 101 and the source-drain gap 107. In some embodiments, the extension 103a may overlap the switch gate 104, meaning that a portion of the extension 103a is directly over a portion of the switch gate 104. In addition, the extension portion 103a is longitudinally separated from an edge of the other of the current control gate 103 and the switching gate 104 to ensure that the current control gate 103 and the switching gate 104 are electrically isolated from each other within the device.

In another embodiment, the current control gate and the switching gate may be longitudinally offset from each other, as shown in FIG. 3. The multi-gate transistor 300 shown in fig. 3 is similar to the multi-gate transistor 100 of fig. 1 and comprises a source 301, a drain 302, a current control gate 303. A switching gate 304, a semiconductor region 305, and an insulator 306. However, the multi-gate transistor 300 of the present embodiment differs from the multi-gate transistor 100 of fig. 1 in that the current control gate 303 is longitudinally offset from the switch gate 304. In other words, if the source 301 and the drain 302 are provided at the same height within the layer structure of the multi-gate transistor 300, the vertical distance d between the source 301 and the current control gate 303₁May be different from the vertical distance d between the source-drain gap 307 and the switching gate 304₂. In addition, the upper edge of the switching gate 304 is spaced apart from the lower edge of the current control gate 303 by a distance d₃So that the current control gate 303 and the switching gate 304 do not contact each other. It will be readily appreciated that the opposite arrangement may be used in other embodiments, that is, the current control gate 303 may be provided at a lower height than the switching gate 304.

By positioning the current control gate 303 and the switching gate 304 at different heights, the current control gate 303 may extend in a lateral direction at least to the edge of the switching gate 304 without contacting the switching gate 304. This arrangement may thus also provide a continuous electric field across the source 301 and source-drain gap 307, while keeping the current control gate 303 and the switching gate 304 separated. This arrangement may also enable a simplified manufacturing process compared to the device geometry shown in fig. 1, since the current control gate 303 and the switching gate 304 may each be formed as a single planar layer within the multi-gate transistor 300.

However, in some embodiments, the current control gate 103, 103a, 303 and the switching gate 104, 304 may together not completely cover the entire length of the gap 107, 307 between the source 101, 301 and the drain 102, 302. In other words, in the device orientation shown in fig. 1-3, the rightmost edge of the current control gate 103, 303 and any extension 103a may be laterally spaced from the leftmost edge of the switching gate 104, 304 such that a portion of the source-drain gap 107, 307 is covered by neither the current control gate 103, 103a, 303 nor the switching gate 104, 304. For example, the rightmost edge of the current control gate 103, 303 and any extension 103a may be laterally spaced from the leftmost edge of the switch gate 104, 304 by a relatively small gap on the order of one micron or less. It will be appreciated that such gaps may naturally occur due to manufacturing tolerances, depending on the manufacturing process used. In general, such gaps should be minimized or avoided because device linearity and energy efficiency may be negatively impacted as the gap size between the current control gate 103, 103a, 303 and the switching gate 104, 304 increases.

In the embodiments of fig. 1 and 3, the sources 101, 301 and the current control gates 103, 303 are arranged at opposite sides of the semiconductor regions 105, 305. However, in some embodiments, the current control gate metallization 103, 303 may in principle be on the same side as the source 101, 301, with a doped or semiconductor heterostructure being used to create an effective barrier in the source region, which is effectively located on the opposite side of the semiconductor region 105, 305 from the current control gate 103, 303.

Referring now to fig. 4, a timing diagram for a multi-gate transistor similar to that shown in fig. 1 is shown, in accordance with an embodiment of the present invention. In the graph shown in fig. 4, a plot of voltage versus time is shown when a multi-gate transistor is placed in a common-source amplifier configuration. FIG. 4a shows the quasi-DC response and shows the voltage drop (V) in the resistor connected to the drain due to the drain current when_R): when the current controls the voltage (V) on the gate_CCG) Ramping from 0V to 10V while applying a voltage of 10V (V) across the source and drain_DD10V) and is switched by the switching gate V_SGAfter the transistor has been switched to the "on" state by applying a voltage of 10V.

FIG. 4b shows the voltage V across the gate of the pass switch over a period of 1 nanosecond (1ns)_SGBy making the voltage V on the current control gate voltage before suddenly switching the transistor from 0V to 10V_CCGA timing diagram obtained by ramping up. The transient response of the multi-gate transistor in this case (which is shown in fig. 5) indicates that the multi-gate transistor can operate faster than the SGT and also provides an improvement over conventional Thin Film Transistor (TFT) performance. The graph in FIG. 5 compares multiple gate crystalsThe corresponding recovery time of the transistor (MGT) relative to conventional SGT and FET is expressed as a percentage of the final drain voltage. As shown in fig. 5, the multi-gate transistor recovers to the final drain voltage faster than a conventional SGT or FET.

Without wishing to be bound by any particular theory, it is hypothesized that the increased operating speed of the multi-gate transistor according to embodiments of the present invention relative to conventional SGTs and FETs arises from the decoupling of the current injection and device on-off switching mechanisms (which are controlled by the current control gate and the switching gate, respectively). In contrast to conventional SGTs, even the voltage V on the current control gate_CCGAfter ramping up to the steady state value, the multi-gate transistor is still in the "off" state until a sufficient switching voltage is applied to the switching gate V_SGUntil now.

Referring now to FIG. 6, a multi-floating gate transistor including two floating gates is shown, according to an embodiment of the present invention. As with the multi-gate transistor of the previous embodiment, the multi-floating gate transistor includes a source 601, a drain 602, a current control gate 603, a switch gate 604, a semiconductor region 605, and an insulator 606.

However, in the present embodiment, a voltage is not directly applied to the current control gate 603 or the switching gate 604. Rather, the transistor further includes a gate terminal 608 disposed over at least a portion of the current control gate 603 and at least a portion of the switch gate 604. In the present embodiment, an applied voltage for allowing a current to flow between the source 601 and the drain 602 through the semiconductor region 605 is applied to the gate terminal 608, and the current control gate 603 and the switch gate 604 function as floating gates. The control gate 608 over the source-drain gap 607 thus provides the necessary electric field for the transistor to operate. For comparison purposes, an example of an SGT including a floating gate (hereinafter "FG SGT") is shown in fig. 7, which includes a source 701, a drain 702, a floating gate 703, a semiconductor region 705, an insulator 706, and a control gate 708.

Fig. 8 is a diagram showing an example of output characteristics of an FG SGT and an FG SGT similar to that shown in fig. 7. The data plotted in fig. 8 were obtained from a series of experiments in which voltages of 2.5V, 5V, 7.5V, and 10V were applied to the gate of the SGT, and voltages of 4V, 8V, 12V, and 16V were applied to the gate 708 of the FG SGT. A higher voltage is used for FG SGT to obtain a similar current level to enable direct comparison.

As shown in fig. 8, incorporating FG into the SGT negatively impacts device performance and causes the SGT to lose its flat output characteristics, which in a normal (i.e., non-FG) SGT is responsible for the high gain of the device. Fig. 8 shows that the inclusion of FG results in two saturation points. At a first saturation point 801, the FG SGT initially saturates due to pinch-off at the source, and at a second saturation point 802, the FG SGT eventually saturates due to pinch-off at the drain, similar to a conventional TFT. Similar behavior is also observed in standard SGTs, whose sources have been poorly protected from varying drain voltages. Between the two saturation points 801, 802 there is a large gain loss (slope >0), which occurs due to capacitive coupling with the channel potential and drain potential of the FG 703, causing the FG 703 potential to increase, which in turn generates more mode I and mode II currents. Due to this double saturation behavior, FG SGTs do not provide the high gain advantage of normal SGTs.

Referring now to fig. 9, a graph comparing output characteristics of a multi-floating gate transistor to examples of SGT and FG SGT is shown, in accordance with an embodiment of the present invention. In contrast to FG SGT, dividing the floating gate 703 into multiple floating gates 603, 604 as in the floating gate multi-gate transistor (FG-MGT) shown in FIG. 6 results in the switch gate 704 being coupled to the channel potential and effectively keeping the current control gate 703 from capacitive coupling. Thus, a multi-floating gate transistor according to an embodiment of the present invention can achieve performance similar to an SGT in terms of gain. Furthermore, in a multi-floating gate transistor such as that shown in fig. 6, as long as the voltage on the drain 602 is of sufficient magnitude (as compared to a conventional FET which is quadratic in relation), the mode II current is linearly proportional to the voltage applied to the gate terminal 608.

In the embodiment shown in fig. 6, the gate terminal 608 extends at least across the full length of each of the current control gate 603 and the switch gate 604 such that the gate terminal 608 completely overlaps each of the current control gate 603 and the switch gate 604. However, in other embodiments, the gate terminal 608 may only partially overlap with one or both of the current control gate 603 and the switch gate 604.

Additionally, in some embodiments, a multi-floating gate transistor may include a plurality of switch gates 604 disposed over the gap 607 between the source 601 and drain 602. In such an embodiment, the gate terminal 608 may extend across, i.e., overlap, all of the plurality of switch gates 604 such that each of the plurality of switch gates 604 appears as a floating gate.

Alternatively, in some embodiments, the gate terminal 608 may only extend across, i.e., overlap, one or more of the switch gates 604, and may not overlap one or more other of the switch gates 604. In such embodiments, one or more of the switch gates 604 that overlap with the gate terminal 608 may behave as a floating gate, while one or more of the switch gates 604 that do not overlap with the gate terminal 608 may behave similarly to the switch gates 104, 304 described above with reference to the embodiments of fig. 1 and 3, or may behave as a floating gate if a voltage is not directly applied to each switch gate. The device can then be turned "on" by applying a threshold switching voltage directly to each of the one or more switching gates 604 that do not overlap the gate terminal 608.

Referring now to fig. 10, a multi-gate transistor including multiple switching gates is shown, according to an embodiment of the present invention. The multi-gate transistor includes a source 1001, a drain 1002, a current control gate 1003, a semiconductor region 1005, and an insulator 1006. Further, in the present embodiment, the multi-gate transistor includes a plurality of switching gates 1004a, 1004b, 1004c, 1004d disposed above the source-drain gap 1007. Each of the plurality of switching gates 1004a, 1004b, 1004c, 1004d is electrically isolated from the other of the plurality of switching gates 1004a, 1004b, 1004c, 1004d, and thus current is allowed to flow between the source 1001 and the drain 1002 through the semiconductor region 1005 only when a voltage applied to each of the plurality of switching gates 1004a, 1004b, 1004c, 1004d is equal to or greater than a respective switching threshold voltage of that of the plurality of switching gates.

In some embodiments, one or more of the plurality of switch gates may include an extension portion similar to current control gate 103 in the embodiment shown in fig. 1. An example of such an embodiment is shown in fig. 11, where four switching gates 1104a, 1104b, 1104c, 1104d are disposed at the same height with respect to the source-drain gap 1107. Three of the switch gates 1104a, 1104b, 1104c include a portion that projects vertically from the edge of the switch gate and then extends horizontally across the gap between the switch gate and the adjacent one of the switch gates. As another alternative, in some embodiments, as shown in fig. 12, adjacent ones of the plurality of switch gates 1204a, 1204b, 1204c, 1204d may be disposed at different heights above the source-drain gap 1207.

By connecting each of the plurality of switch gates 1004a, 1004b, 1004c, 1004d to a respective input and using the drain as the output of an and gate, transistors such as those shown in fig. 10, 11 and 12 can be used as multiple-input analog and gates. The multi-gate transistor can then operate as an and gate by allowing current to flow at the output only if the voltage at all of the multiple inputs is equal to or greater than the switching threshold voltage. The switching threshold voltage may be the same for all switching gates 1004a, 1004b, 1004c, 1004d, or may be different for different gates 1004a, 1004b, 1004c, 1004d, depending on various factors including, but not limited to: the materials used, the distance from each gate 1004a, 1004b, 1004c, 1004d to the semiconductor region 1005, and the local characteristics of the semiconductor region 1005 in the gap 1007 between the source 1001 and drain 1002.

When all of the switching gates 1004a, 1004b, 1004c, 1004d are applied with respective threshold voltages, a continuous electric field is provided along the channel and current is allowed to flow between the source 1001 and drain 1002. Using transistors in this manner, the and function provided by the switching gates 1004a, 1004b, 1004c, 1004d is combined with the ability to pass a current of a magnitude controlled by the potential on 1003. This may be advantageous for space applications or other harsh environments where the device is exposed to radiation, as the decoupling between the magnitude of the signal (i.e., the signal applied to the current control gate 1003) and the switching behavior may create a robust electronic platform. In addition, by enabling the AND function to be implemented in the analog domain, a digital control system may no longer be required.

In the embodiments of fig. 10, 11 and 12, the multi-gate transistor includes a plurality of switching gates. In other embodiments, the current control gate in a multi-gate transistor may be divided into a plurality of current control gates separated from each other by insulators, in a similar manner to the division of the switch gate into a plurality of switch gates in the embodiments of fig. 10, 11 and 12. In addition to including multiple current control gates, the multi-gate transistor may include one switching gate or multiple switching gates, depending on the embodiment.

Referring now to fig. 13 and 14, a multi-gate transistor including a first doped region and a second doped region in a semiconductor region will now be described, in accordance with an embodiment of the present invention. As with the embodiment described above with reference to fig. 1, the multi-gate transistors 1300, 1400 shown in fig. 13 and 14 include sources 1301, 1401, drains 1302, 1402, current control gates 1303, 1403, and switching gates 1304, 1404. For the sake of brevity, a detailed description of features common to the embodiments of fig. 1, 13 and 14 will not be repeated here. It will be appreciated that first and second doped regions, such as those described herein with reference to fig. 13 and 14, may also be used in any of the other embodiments described herein, and thus may be combined with features of other embodiments not shown in fig. 1, 13 and 14.

In the embodiment shown in fig. 13, the multi-gate transistor 1300 includes a first doped region 1305a and a second doped region 1305b, the first doped region 1305a and the second doped region 1305b extending across the entire thickness of the semiconductor region. In other words, the first doped region 1305a and the second doped region 1305b each extend from the side of the semiconductor region where the source 1301 and the drain 1302 are provided to the side where the insulator 1306 is provided. In other embodiments, one or both of the first and second doped regions 1305a, 1305b may extend only partially across the thickness of the semiconductor region. For example, in the embodiment shown in fig. 14, the first doped region 1405a and the second doped region 1405b each extend only partially across the thickness of the semiconductor region.

In both embodiments shown in fig. 13 and 14, the first doped region 1305a, 1405a and the second doped region 1305a, 1405a are separated by an undoped semiconductor region 1305c, 1405 c. However, in other embodiments, the first and second doped regions 1305a, 1405a may be immediately adjacent, that is, may contact each other. In some embodiments, the first doped regions 1305a, 1405a and the second doped regions 1305a, 1405a may overlap each other.

In both embodiments shown in fig. 13 and 14, a first doped region 1305a, 1405a is provided between the source 1301, 1401 and the current control gate 1303, 1403. The behavior of the transistors 1300, 1400 in response to voltages applied to the current control gates 1303, 1403 may be controlled by selecting an appropriate dopant species and concentration in the first doped regions 1305a, 1405 a. For example, the first doped regions 1305a, 1405a may be operated in enhancement mode or depletion mode by selecting the appropriate dopants. The enhancement mode may also be referred to as a "normally off" mode, and the depletion mode may be referred to as a "normally on" mode. In this manner, the type of doping used in the first doped regions 1305a, 1405a may determine whether the magnitude of the current flowing between the sources 1301, 1401 and the drains 1302, 1402 increases with increasing voltage applied to the current control gates 1303, 1403 or decreases with increasing voltage applied to the current control gates 1303, 1403.

In addition, in both embodiments shown in fig. 13 and 14, the second doped regions 1305b, 1405b are disposed in the channels 1307, 1407. The behavior of the transistor 1300, 1400 in response to a voltage applied to the switching gate 1304, 1404 can be controlled by selecting an appropriate dopant species and concentration in the second doped region 1305b, 1405 b. For example, the second doped regions 1305b, 1405b may be operated in enhancement mode or depletion mode by selecting the appropriate dopants. In this manner, the second doped regions 1305b, 1405b may determine whether the transistors 1300, 1400 are normally on or normally off when no voltage is applied to the switching gates 1304, 1404.

Depending on the embodiment, the first doped region 1305a, 1405a and the second doped region 1305b, 1405b may operate in the same mode or may operate in different modes. For example, in one embodiment, the first doped regions 1305a, 1405a may operate in enhancement mode and the second doped regions 1305b, 1405b may operate in depletion mode, or vice versa.

By providing separate first and second doped regions 1305a, 1405a, 1305b, 1405b as shown in fig. 13 and 14, and by appropriate selection of dopant species and concentrations, many different combinations of device behavior can be achieved. This provides greater flexibility for the circuit designer. For example, when a dopant is selected for the second doped regions 1305b, 1405b that causes the semiconductor regions in the channels 1307, 1407 to operate in a "normally on" mode, applying a negative voltage to the switching gates 1304, 1404 that exceeds the threshold switching voltage will cause the transistors 1300, 1400 to turn off. This type of behavior may be desirable in circuits where it is desirable to shut off current flow when the control voltage applied to the switching gates 1304, 1404 goes negative. As another example, in embodiments where multiple current control gates and/or multiple switching gates are provided, different doped regions may be provided for different ones of the multiple gates (e.g., using different dopant species and/or different dopant concentrations).

Additionally, in some embodiments, the first doped regions 1305a, 1405a may be omitted and the multi-gate transistor may include only the doped regions 1305b, 1405b in the channels 1307, 1407. Doping the semiconductor in the channel 1307, 1407 can be used to control the threshold voltage of the switching gate 1304, 1404, in other words the voltage at which the transistor 1300, 1400 turns on or off. As another alternative, in some embodiments, the second doped regions 1305b, 1405b may be omitted, and the multi-gate transistor may include only the first doped regions 1305a, 1405a over the source. The first doped region 1305a, 1405a above the source may have the effect of changing the energy barrier height to provide a barrier of a suitable height for a desired result, such as increased charge injection, linearity or temperature dependence, depending on the desired application.

In other embodiments as shown in fig. 15 and 16, a single doped region 1505a, 1605a may be provided which extends across the source 1501, 1601 and channel 1507, 1607 as shown in the embodiments of fig. 15 and 16. Using only a single doped region may provide a simplified manufacturing process compared to embodiments using more than one doped region, such as those shown in fig. 13 and 14. In some embodiments, the doped region may extend across the entire thickness of the semiconductor region, as shown in fig. 15, while in other embodiments, the doped region may extend only partially across the thickness of the semiconductor region, as shown in fig. 16.

Like the embodiments of fig. 1, 13 and 14, the embodiments of fig. 15 and 16 include source electrodes 1501, 1601, drain electrodes 1502, 1602, current control gate electrodes 1503, 1603, switching gates 1504, 1604, and insulating layers 1506, 1606. For the sake of brevity, a detailed description of features common to the embodiments of fig. 1 and 13-16 will not be repeated here. It will be appreciated that a single doped region such as those described herein with reference to fig. 15 and 16 may also be used in any of the other embodiments described herein, and may therefore be combined with features of other embodiments not shown in fig. 1, 15 and 16.

Referring now to fig. 17, a multi-gate transistor is shown, according to an embodiment of the present invention. As with the embodiment of fig. 1, the multi-gate transistor 1700 of fig. 17 includes a source 1701, a drain 1702, a current control gate 1703, a switch gate 1704a, a semiconductor region 1705, and an insulating layer 1706a, and a detailed description of similar features will not be repeated here. It will be appreciated that the features described herein with respect to fig. 17 may also be used in combination with the features of any of the other described embodiments. In some embodiments, the multi-gate transistor may include a plurality of auxiliary gates, in a similar manner to the plurality of switch gates in the embodiments of fig. 10-12.

In the embodiment of fig. 17, transistor 1700 also includes an auxiliary gate 1704b disposed on an opposite side of channel 1707 from switch gate 1704 a. In this embodiment, the auxiliary gate 1704b is separated from the semiconductor material in the channel 1707 by an insulator 1706 b. The threshold voltage of switching gate 1704a, which may also be referred to as the switching voltage, may be adjusted by changing the voltage applied to auxiliary gate electrode 1704 b. In other words, the threshold voltage at which the switching gate 1704a allows current to flow between the source 1701 and the drain 1702 depends on the voltage applied to the auxiliary gate 1704 b. In another embodiment, the auxiliary gate may be in direct contact with the semiconductor between the source and drain. In such embodiments, the energy barrier at the interface between the auxiliary gate and the semiconductor may ensure that no current flows from the gate to the semiconductor in a similar manner to a MESFET, while still allowing the conductance of the semiconductor between the source and drain to be modulated by applying a potential to the auxiliary gate.

In this way, the auxiliary gate electrode 1704b may perform a function similar to that of the second doping regions 1305b, 1405b described above with reference to fig. 13 and 14. However, using auxiliary gate electrode 1704b instead of semiconductor doping to control the switching voltage of switching gate 1704a has the additional advantage that the switching voltage can be dynamically adjusted, rather than fixed for any given device. In some embodiments, an auxiliary gate electrode 1704b may be used in combination with the second doped regions 1305b, 1405 b.

Referring now to fig. 18, a multi-gate transistor including field relief structures in the source and drain is shown, according to an embodiment of the present invention. As with the embodiment of fig. 1, the multi-gate transistor 1800 of fig. 18 includes a source 1801, a drain 1802, a current control gate 1803, a switch gate 1804, a semiconductor region 1805, and a first insulating layer 1806a, and a detailed description of similar features will not be repeated here. It will be appreciated that the features described herein with respect to fig. 18 may also be used in combination with the features of any of the other described embodiments.

In the embodiment of fig. 18, the transistor 1800 includes a second insulating layer 1806b disposed between the substrate and the source 1801 and drain 1802. Further, the source 1801 and drain 1802 each include a respective field relief structure 1801a, 1802a, the field relief structures 1801a, 1802a extending partially under the channel. An insulator 1806c (which is referred to herein as a "field relief insulator") is disposed between the field relief structures 1801a, 1802a and the semiconductor region to isolate the field relief structures 1801a, 1802a from the semiconductor region in the channel. The first insulating layer 1806a, the second insulating layer 1806b, and the field relief insulator 1806c may be formed of the same insulating material or of different materials.

In some embodiments, the transistor 1800 may include only the field relief structure 1801a on the source 1801, and the field relief structure 1802a on the drain 1802 may be omitted. However, it may be easier to fabricate both field relief structures 1801a, 1802a together, as additional processing steps may be required to form the field relief structure 1801a only on the source 1801. For example, to have only the source field relief structure 1801a without the corresponding structure 1802a on the drain, it may be necessary to mask the source 1801, drain 1802, and source field relief structure 1801a and then etch away the drain field relief structure 1802 a.

The source field relief structure 1801a extends beyond the edge of the source 1801 closest to the drain 1802 in a direction toward the drain 1802. In this manner, the source field relief structure 1801a serves to at least partially shield the source 1801 from the lateral electric field in the channel created by the presence of the drain 1802, so that the behavior of the source 1801 is not affected by the field from the drain 1802.

As an alternative to the source field mitigation structure 1801 in fig. 18, in another embodiment, separate field mitigation electrodes may be provided to perform a similar function, as will now be described with reference to fig. 19. Like the embodiment of fig. 1, the multi-gate transistor 1900 of fig. 19 includes a source 1901, a drain 1902, a current control gate 1903, a switching gate 1904, a semiconductor region 1905, and an insulating layer 1906a, and a detailed description of similar features will not be repeated here. It will be appreciated that the features described herein with respect to fig. 19 may also be used in combination with the features of any of the other described embodiments.

The field-relief electrode 1901a is disposed below an end of the source 1901 adjacent to the channel 1907. As shown in fig. 19, the field-relief electrode 1901a partially overlaps the source 1901 and also partially overlaps the channel 1907. In addition, the field-relief electrode 1901a is separated from the source 1901 and the channel 1907 by insulating material 1706 b. As with the source field relief structure 1801a of fig. 18, the field relief electrode 1901a of fig. 19 extends beyond the edge of the source 1901 closest to the drain 1902 in a direction toward the drain 1902. In this manner, the field-relief electrode 1901a serves to at least partially shield the source 1901 from the lateral electric field in the channel 1907 created by the presence of the drain 1902, so that the behavior of the source 1901 is not affected by the field from the drain 1902.

As described above with reference to fig. 1, the potential barrier between the source and the semiconductor region may be provided by a suitable choice of materials, either by doping the source and/or the semiconductor or by forming a heterojunction. An embodiment of the invention comprising a physical barrier between the source and the semiconductor region will now be described with reference to fig. 20 to 22. Depending on the embodiment, a physical barrier may be used alone or in combination with a suitable form of potential barrier such as those described above. The various forms of physical and potential barriers described herein all act as energy barriers between the source and the semiconductor region and therefore can prevent current flow between the source and the semiconductor at low source-gate voltages.

Fig. 20 shows a multi-gate transistor 2000 comprising a tunnel layer 2005a provided between a source 2001 and a semiconductor region 2005. The tunnel layer 2005a comprises a layer of material that is sufficiently thin to allow electrons or holes to "tunnel" from one side of the layer to the other when a sufficiently high electric field is applied across the tunnel layer 2005 a. The tunnel layer 2005a may include an electrically insulating material, or may include a material having an energy band structure that provides a suitable energy barrier. In this way, the tunnel layer 2005a performs a function similar to that of a potential barrier by preventing a current from flowing from the source 2001 into the semiconductor region 2005 at a low source-gate voltage. In this embodiment, the tunnel layer 2005a also extends across the source 2005, substrate in the channel 2007 and the drain 2002. However, in another embodiment, the tunnel layer 2005a may be disposed only over the source 2001 and may not extend across the channel 2007 or the drain 2002.

Fig. 21 shows a multi-gate transistor 2100 that includes an energy barrier formed by doping a region 2105a of semiconductor 2105 above the source 2101. In this embodiment, the doped region 2105a is separated from the source 2101 by a region of undoped semiconductor material 2105. In another embodiment, the doped region 2105a may be immediately adjacent to the source 2101.

In this embodiment, doped region 2105a extends beyond the end of source 2101 closest to drain 2102 such that doped region 2105a extends partially into channel 2107. In this manner, the portion of doped region 2105a that extends beyond the edge of source 2101 may perform a similar function as source field mitigation structure 1801a of fig. 18 and field mitigation electrode 1901a of fig. 19 by ensuring that the behavior of source 2101 is not affected by the field above channel 2107. However, in another embodiment, the doped region 2105a may extend only to the edge of the source 2101 and may not extend into the channel 2107.

Figure 22 shows a multi-gate transistor 2200 including a heterostructure energy barrier according to an embodiment of the present invention. In this embodiment, the energy barrier is provided in the form of a heterostructure comprising two different semiconductor materials. The semiconductor region separating the source 2201 from the current control gate 2203 comprises a first semiconductor material 2205, and a second semiconductor material 2205a is disposed over the source 2201 between the source 2201 and the first semiconductor 2205. In this way, the interface between the two different semiconductors forms a heterojunction and acts as an energy barrier to current flowing between the source 2201 and the first semiconductor 2205.

Referring now to fig. 23, a multi-gate transistor 2300 is shown that includes a switching gate electrode and a floating current control gate, according to an embodiment of the invention. This embodiment differs from the floating gate transistor shown in fig. 6 in that only one of the two gates is a floating gate. In this embodiment, current control gate 2303 is a floating gate, and transistor 2300 includes a gate terminal 2308 disposed over at least a portion of current control gate 2303. Unlike the embodiment of fig. 6, the gate terminal 2308 does not extend above the switch gate 2304. Instead, the voltage is applied directly to the switching gate 2304.

In this embodiment, only the current control gate is embodied as a floating gate, allowing the floating gate function of the source to be separated from the switching function. In another embodiment, the gate terminal 2308 may be disposed only above the switch gate 2304 and may not extend above the current control gate 2303. In this case, the switch gate 2304 behaves as a floating gate, and a voltage can be applied directly to the current control gate 2303. Using a floating switch gate in this manner may enable the transistor to be latched in an "on" or "off" state.

Although a single gate terminal 2308 is shown in fig. 23, in some embodiments, the gate terminal 2308 may be divided into multiple gate terminals that are spaced apart from each other and separated by an insulator. For example, in one embodiment, the gate terminal 2308 can be divided into a plurality of individual terminals spaced apart from each other in the horizontal direction in fig. 23.

Alternatively, the gate terminal 2308 may be divided into a plurality of individual terminals spaced apart in a direction perpendicular to the plane of the drawing in fig. 23. An example of such an embodiment is shown in fig. 24, where a multi-gate transistor 2400 is shown, the multi-gate transistor 2400 comprising a plurality of input terminals 2408a, 2408b arranged above a floating current control gate 2403. Like the transistors of the other embodiments described above, the transistor 2400 shown in fig. 24 also includes a source 2401, a drain 2402, a switching gate 2404, a semiconductor region 2405, and an insulating layer 2406, and a detailed description of similar features will not be repeated here.

The transistor 2400 of the present embodiment can be made to perform various functions by applying different voltages to each of the input terminals 2408a, 2408 b. For example, the transistor 2400 can be used to sum multiple analog input voltages by applying each input voltage to a different one of the multiple input terminals 2408a, 2408 b. Although only two input terminals 2408a, 2408b are shown in fig. 24, it will be understood that in other embodiments, any number of input terminals 2408a, 2408b may be provided depending on the requirements of a particular application. In this embodiment, each input terminal 2408a, 2408b has the same area and overlaps the floating current control gate 2403 by the same amount so that each input terminal 2408a, 2408b has the same degree of influence on the output current. In this way, the output current produced by the transistor is related to the linear sum of the input voltage.

In embodiments such as the embodiment shown in fig. 24, each of the plurality of gate terminals 2408a, 2408b may extend across the entire width of the current control gate 2403, or may extend across only a portion of the width of the current control gate 2403. By changing the overlapping area between one of the gate terminals 2408a, 2408b and the current control gate 2403, the influence of the gate terminals 2408a, 2408b on the magnitude of current flowing between the source 2401 and the drain 2402 can be controlled.

A related embodiment will now be described with reference to fig. 25. Although not floating gate transistors, the multi-gate transistor 2500 shown in fig. 25 is similar to that shown in fig. 24 in that the transistor 2500 includes a plurality of input terminals in the form of current control gates 2503a, 2503b, 2503c spaced apart from one another in a direction perpendicular to the plane of the drawing in fig. 1. In other words, the plurality of current control gates 2503a, 2503b, 2503c are spaced apart in a direction parallel to an edge of the source electrode 2501 adjacent to the channel between the source electrode 2501 and the drain electrode 2502. The transistor 2500 shown in fig. 25 also includes a switching gate 2504, a semiconductor region 2505, and an insulating layer 2506 as in the transistors of the other embodiments described above, and a detailed description of similar features will not be repeated here.

In the present embodiment, the transistor 2500 is configured to function as a digital-to-analog converter. In the present embodiment, a total of three current control gates 2503a, 2503b, 2503c are shown, each of which has a different overlapping area with the source electrode 2501, as shown in fig. 25. Specifically, the overlapping area of the second current control gate 2503b and the source 2501 is twice as large as the overlapping area of the first current control gate 2503a and the source 2501, and the overlapping area of the third current control gate 2503c and the source 2501 is twice as large as the overlapping area of the second current control gate 2503b and the source 2501. In this manner, each bit of the 3-bit input digital codeword may be applied to a respective one of the current control gates 2503a, 2503b, 2503 c. The least significant bit is applied to the first current control gate 2503a, the middle bit is applied to the second current control gate 2503b, and the most significant bit is applied to the third current control gate 2503 c. Because the overlap area of each current control gate is different, the input codewords '011', '101' and '110' will produce different analog output voltages.

It will be appreciated that the 3-bit input codeword is described purely as an example, and that additional current control gates may be added following a similar pattern depending on the number of input bits required. In general, if an input digital codeword includes n bits and a multi-gate transistor includes n current control gates each having a different overlap area with a source, the overlap area of the current control gates increases from a first current control gate to an nth current control gate and follows a geometric progression having a common ratio r of 2. In this embodiment, the common ratio of 2 is used to determine the relative area of the n current control gates, since the input number is a bit (binary number). In other embodiments, the digits of the input numeric codeword may be represented in a base other than 2, and the appropriate common ratio may be selected accordingly. For example, when an octal number (base 8) is used, the overlapping area of the current control gates may follow a geometric progression with a common ratio r of 8. Similarly, when hexadecimal numbers (base 16) are used, the overlapping area of the current control gates may follow a geometric progression with a common ratio r of 16.

In the above embodiments, a planar transistor structure is shown, which may be manufactured by depositing a series of layers on top of each other. In some embodiments of the invention, the same principles disclosed above may be applied to circular or concentric transistor structures, examples of which will now be described with reference to fig. 26 to 28.

Fig. 26 shows the transistor structure 2600 in cross-section similar to the embodiment of fig. 1, including a source 2601, a drain 2602, a current control gate 2603, a switching gate 2604, a semiconductor region 2605, and an insulating layer 2606. However, unlike the embodiment of fig. 1, in the present embodiment, the source 2601 and the drain 2602 are disposed on opposite sides of the semiconductor region 2605, wherein the drain 2602 is disposed on the same side of the semiconductor region 2605 as the current control gate 2603 and the switching gate 2604.

In some embodiments, transistors may be fabricated with concentric circular structures, similar to Corbino devices. The structure of this embodiment can be understood as being equivalent to the cross-section shown in fig. 26 rotated 360 about the y-axis. Alternatively, in another embodiment, the transistor may be fabricated, for example, based on semiconductor nanowires, with a structure equivalent to a 360 ° rotation of the cross-section shown in fig. 26 about the x-axis.

Referring now to fig. 27 and 28, according to one example, a nanowire-based multi-gate transistor 2700 is shown in which a current control gate 2703 and a switching gate 2704 are disposed on the same side of a semiconductor region 2705 as a source 2701 and a drain 2702. Fig. 28 shows a cross section through transistor 2700 from a to a'. For example, the transistor 2700 can be manufactured by: a source 2701 and a drain 2702 are deposited on the surface of the semiconductor nanowire 2705, then an insulating layer 2706 is deposited around the nanowire 2705, the source 2701 and the drain 2702, and then a current control gate 2703 and a switching gate 2704 are deposited around the insulating layer 2706. It will also be understood that a circular transistor structure can be obtained by rotating the cross-section shown in fig. 27 about either of the axes labeled a and a'.

Although certain embodiments of the present invention have been described herein with reference to the accompanying drawings, it will be understood that many variations and modifications will be possible without departing from the scope of the invention as defined in the appended claims.