阅读说明：本技术 一种存储阵列电路结构及大型存储阵列电路结构 (Storage array circuit structure and large-scale storage array circuit structure ) 是由 谢成民 崔千红 杨靓 李海松 李立 马蕊 朱吉喆 于 2021-08-27 设计创作，主要内容包括：本发明一种存储阵列电路结构及大型存储阵列电路结构,在存储阵列分为上存储列阵和下存储列阵,同时在其端部均分别连接灵敏放大器、读写驱动模块和列地址译码电路,上存储列阵的存储单元将由上面的灵敏放大器读出,下存储列阵将由下面的灵敏放大器读出,这样不仅会减小分块设计的级数,避免引入多余的外围电路,进而减小存储器的版图面积,增加版图密度,实现静态存储器存取速度的提升以及功耗的降低。本发明相比较传统分块设计的结构,减小了位线放电幅度进而负载,降低了最坏路径延迟和存储器的功耗,达到提高整体存储器读取速度的目的；最后,本发明所提出的方法适用于各种存储器的电路架构设计,具有良好的应用前景和经济效益。(The invention relates to a memory array circuit structure and a large-scale memory array circuit structure.A memory array is divided into an upper memory array and a lower memory array, and meanwhile, the end parts of the upper memory array and the lower memory array are respectively connected with a sensitive amplifier, a read-write driving module and a column address decoding circuit, a memory unit of the upper memory array is read by the upper sensitive amplifier, and the lower memory array is read by the lower sensitive amplifier, so that the stage number of block design is reduced, the introduction of redundant peripheral circuits is avoided, the layout area of a memory is further reduced, the layout density is increased, and the improvement of the access speed of a static memory and the reduction of power consumption are realized. Compared with the structure of the traditional block design, the structure reduces the bit line discharge amplitude and the load, reduces the worst path delay and the power consumption of the memory, and achieves the aim of improving the reading speed of the whole memory; finally, the method provided by the invention is suitable for the circuit architecture design of various memories, and has good application prospect and economic benefit.)

1. A memory array circuit structure is characterized by comprising an upper memory array (1) and a lower memory array (2);

the two ends of the upper storage array (1) and the lower storage array (2) which are relatively far away are respectively provided with a sensitive amplifier (3), a read-write driving module (4) and an array address decoding circuit (5) in sequence, the sensitive amplifiers are used for meeting the signal SA logical operation of the upper storage array (1) and the lower storage array (2) respectively, and the read-write driving module (4) is connected with a data unit (6);

the same side of the upper storage array (1) and the lower storage array (2) is respectively connected with a row address decoding circuit (7).

2. A memory array circuit arrangement as claimed in claim 1, wherein the row address decoding circuit (7) is arranged to decode an input row address signal and to select either the upper memory array (1) or the lower memory array (2) for input.

3. A memory array circuit arrangement as claimed in claim 1, characterized in that the intersections of the bit lines and word lines of the upper (1) and lower (2) memory arrays, respectively, form memory cells (9).

4. A memory array circuit arrangement as claimed in claim 1, characterized in that the upper memory array (1) and the lower memory array (2) have an array height equal to their respective bitline length.

5. A memory array circuit arrangement as claimed in claim 1, characterized in that the row address decoding circuit (7) comprises a high-order address signal of the one-order address signal (8).

6. A memory array circuit arrangement as claimed in claim 5, characterized in that the one-bit address signal (8) is connected via an inverter to the sense amplifiers (3) on both sides of the upper (1) or lower (2) memory array.

7. A large memory array fast read circuit structure comprising a plurality of memory array circuit structures of any of claims 1-6 above;

the plurality of memory array fast reading circuit structures are connected through a hierarchical word line structure and a multi-path selection bit line technology.

8. The large scale memory array circuit structure of claim 7, further comprising a pre-selected read operation module, a timing control module, an X address buffer, a Y address buffer, and an IO buffer;

the output end of the X address buffer is respectively connected with a time sequence control module and a pre-decoding circuit of a pre-selection reading operation module;

the input end of the Y address buffer is connected with a column address decoding circuit (5) of the preselection reading operation module, and the output end of the Y address buffer is connected with the time sequence control module;

the output end of the time sequence control module is connected with a sensitive amplifier (3) of a preselection reading operation module;

the IO buffer is connected with all the sensitive amplifiers (3) in a bidirectional mode.

Technical Field

The invention belongs to the field of high-speed low-power-consumption data storage in the microelectronic technical direction, and particularly relates to a storage array circuit structure and a large-scale storage array circuit structure.

Background

With the demand of high speed and low power consumption of memory design and the development of manufacturing technology, the existing memory is difficult to meet the market index demand of integrated circuits.

Various methods are currently explored to balance speed and power consumption, including memory cell development, timing control module development, and so on. The conventional circuit structure is shown in fig. 1, and the memory includes a memory cell array module, a row-column decoder module, a sense amplifier, a read-write driving module, a timing control circuit, and an output circuit. The memory array is designed into four blocks, namely an upper block, a lower block, a left block and a right block, wherein each upper block and the lower block share one column decoding circuit, one sensitive amplifier and one write driving circuit, and the middle of the whole memory is provided with a row decoding address circuit and a time sequence control module circuit. The address signal of the memory is divided into a row address and a column address, when the row decoder receives the row address signal, a word line is selected to trigger a row of the memory array, and simultaneously the column decoder receives the column address signal, a required word circuit schematic diagram in the selected row can be found out as shown in fig. 2.

However, as the memory capacity increases, the area of the decoder and the memory array also increases, and the length of the bit line and the corresponding load capacitance on the bit line also increase. When a row-column decoder selects a memory address to be accessed and performs read-write operation, the reading speed of a memory cell close to a sense amplifier is greatly different from that of a memory cell far from the sense amplifier, the path for accessing the memory cell close to the sense amplifier is short and is 1 memory cell at the shortest, the path for accessing the memory cell far from the sense amplifier is long, for example, one memory array has 2m rows and 2n columns, the path is up to 2m/2 memory cells at the longest, the metal wire capacitance on a bit line and the memory cell load capacitance are heavy, and the access time is long. The access time of the memory can only be the same as the access time of the memory address at the farthest distance, and the data reading of the memory cell at the farther distance is an important reason for influencing the reading speed of the memory. Meanwhile, due to the influence of the access speed, the voltage drop on the bit line is also large, which leads to the increase of the power consumption of the memory, and therefore, the read-write time and the power consumption of the memory are greatly influenced by the fact that the word line and the bit line are too long.

In order to solve the problem, in the structural design of a large-capacity memory, a method of a more-level block design can be adopted, so that the delay under the worst path is reduced, the speed of the SRAM is increased, and the power consumption is reduced, as shown in fig. 3, the memory is divided into P small blocks, the composition architecture of each small block is the same as that of fig. 2, each block is provided with a memory array, a local row decoding and a local column decoding, the selection of a memory unit is also based on the row address and the column address corresponding to each block, and in addition, a block address is mainly responsible for selecting one block needing reading and writing from the P small blocks. By means of the hierarchical word line structure and the multi-path bit line selection technology, after the address is valid, decoding is carried out by the block address, 1 of the P small blocks is selected to carry out read-write operation, and then the read-write operation described in the figure 2 is carried out. Therefore, only individual blocks are selected when the circuit works, and the row-column decoding and the sensitive amplifier in the unselected blocks do not work, so that the power consumption is not greatly influenced; the disadvantage is that if it is necessary to ensure that the lengths of the word lines and bit lines in the selected block are kept within certain limits, more stages of classification are required, not only multi-stage partitioning is required in the transverse direction, but also multi-stage partitioning is required in the longitudinal direction, so that a series of problems caused by excessive bit line load can be avoided, and more decoding circuits and control circuits need to be added, that is, area needs to be sacrificed to achieve balance between speed and power consumption.

Disclosure of Invention

The invention provides a memory array circuit structure, aiming at the problems of large power consumption and long conduction time of the memory array circuit structure in the prior art.

The invention is realized by the following technical scheme:

a memory array circuit structure is characterized by comprising an upper memory array and a lower memory array;

the two ends of the upper storage array and the lower storage array which are relatively far away from each other are sequentially provided with a sensitive amplifier, a read-write driving module and a column address decoding circuit which are used for respectively meeting the signal SA logical operation of the upper storage array and the lower storage array, and the read-write driving module is connected with a data unit;

the same side of the upper storage array and the lower storage array is respectively connected with a row address decoding circuit.

Further, the row address decoding circuit is used for decoding an input row address signal and selecting the upper memory array or the lower memory array for input.

Furthermore, the intersection points of the bit lines and the word lines of the upper memory array and the lower memory array respectively form memory cells.

Further, the upper and lower memory arrays have an array height equal to their respective bitline lengths.

Further, the row address decoding circuit includes a high order address signal of a one-bit address signal.

Furthermore, the one-bit address signal is connected with the sensitive amplifiers on two sides of the upper storage array or the lower storage array through the phase inverter.

A large storage array fast reading circuit structure is characterized by comprising a plurality of storage array circuit structures;

the plurality of memory array fast reading circuit structures are connected through a hierarchical word line structure and a multi-path selection bit line technology.

Furthermore, the system also comprises a preselected reading operation module, a time sequence control module, an X address buffer, a Y address buffer and an IO buffer;

the output end of the X address buffer is respectively connected with a time sequence control module and a pre-decoding circuit of a pre-selection reading operation module;

the input end of the Y address buffer is connected with a column address decoding circuit of the preselection reading operation module, and the output end of the Y address buffer is connected with the time sequence control module;

the output end of the time sequence control module is connected with a sensitive amplifier of a preselection reading operation module;

the IO buffer is connected with all the sensitive amplifiers in a bidirectional mode.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention relates to a memory array circuit structure, wherein a memory array is divided into an upper memory array and a lower memory array, the ends of the upper memory array and the lower memory array are respectively connected with a sensitive amplifier, a read-write driving module and a column address decoding circuit, a memory unit of the upper memory array is read by the sensitive amplifier on the upper side, and the lower memory array is read by the sensitive amplifier on the lower side, so that the stage number of block design is reduced, the introduction of redundant peripheral circuits is avoided, the layout area of a memory is reduced, and the layout density is increased; the memory array can be divided into an upper memory array and a lower memory array by one bit of address signal in the row decoding address circuit, so that the length of a bit line can be shortened, the load capacitance of the bit line is reduced, the access speed of the static memory is improved, and the power consumption is reduced. Compared with the structure of the traditional block design, the bit line discharge amplitude is reduced, the worst path delay and the power consumption of the memory are reduced, and the purpose of improving the reading speed of the whole memory is achieved; finally, the method provided by the invention is suitable for the circuit architecture design of various memories, and has good application prospect and economic benefit.

Furthermore, the one-bit address signal selects a high-bit address signal in the row decoding address, so that the continuity of a low-bit address can be ensured, and the load of the memory array circuit is reduced.

Furthermore, the one-bit address signal is an address signal for selecting the upper memory array and the lower memory array in the row decoding address circuit, so that the upper and lower division can be realized, the address and the enable signal SA of the sense amplifier are subjected to logical operation, namely NAND operation and NOR operation, batch processing of signals by the upper memory array and the lower memory array can be met, the overall operation efficiency is improved, and the operation energy consumption is reduced.

According to the large-scale storage array circuit structure, the plurality of storage array quick reading circuit structures are connected through the hierarchical word line structure and the multi-path bit line selection technology, so that the purposes of quicker operation and lower operation energy consumption can be achieved.

Drawings

FIG. 1 is a diagram of a conventional memory circuit architecture;

FIG. 2 is a schematic diagram of a conventional memory circuit;

FIG. 3 is a circuit diagram of a conventional super-large capacity memory multi-level block design;

FIG. 4 is a schematic diagram of a memory array circuit according to an embodiment of the present invention;

FIG. 5 shows a 1Mbit memory circuit according to an embodiment of the present invention.

In the figure: the memory array comprises an upper memory array 1, a lower memory array 2, a sensitive amplifier 3, a read-write driving module 4, a column address decoding circuit 5, a data unit 6, a row address decoding circuit 7, an address signal 8 and a memory unit 9.

Detailed Description

The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.

The invention relates to a memory array circuit structure, as shown in fig. 4, which specifically comprises an upper memory array 1 and a lower memory array 2 through the optimized design of the whole framework of the existing static memory;

the two ends of the upper storage array 1 and the lower storage array 2 which are relatively far away are respectively provided with a sensitive amplifier 3, a read-write driving module 4 and a column address decoding circuit 5 in sequence, and the two ends are used for respectively meeting the signal SA logical operation of the upper storage array 1 and the lower storage array 2;

the read-write driving module 4 is connected with the data unit 6; the same sides of the upper storage array 1 and the lower storage array 2 are respectively connected with a row address decoding circuit 7, so that the design can reduce the stage number of the block design, avoid introducing redundant peripheral circuits, further reduce the layout area of the memory and increase the layout density;

further, the row address decoding circuit 7 is configured to decode an input row address signal, and select the upper memory array 1 or the lower memory array 2 for input, thereby implementing signal storage.

Furthermore, the intersections of the bit lines and the word lines of the upper memory array 1 and the lower memory array 2 respectively form memory cells 9; meanwhile, the array heights of the upper storage array 1 and the lower storage array 2 are equal to the lengths of the bit lines of the upper storage array and the lower storage array, so that compared with the traditional storage array circuit structure, the bit line length can be shortened, the load capacitance of the bit line is reduced, and the access speed of the static memory is improved and the power consumption is reduced.

In a preferred embodiment of the present invention, the one-bit address signal 8 is a high-bit address signal 8 in a row decoding address, so that continuity of a low-bit address can be ensured, and a load of a memory array circuit is reduced;

further, the one-bit address signal 8 is connected with the sense amplifiers 3 on both sides of the upper memory array 1 or the lower memory array 2 through a phase inverter, specifically, the one-bit address signal 8 is an address signal for selecting the upper memory array 1 and the lower memory array 2 in the row decoding address circuit 7, so that the upper and lower division can be realized, the address and the enable signal SA of the sense amplifier 3 are subjected to logical operation, namely nand or nor operation, and simultaneously, batch processing of the signals by the upper memory array 1 and the lower memory array 2 can be satisfied, the overall operation efficiency is improved, and the operation energy consumption is reduced.

Further, in a preferred embodiment of the present invention, the sense amplifier 3 on one side of the lower memory array 2 is selected by a one-bit address signal 8, and the determining and selecting processes are as follows: if the one-bit address signal 8 is 1, it is output to the upper memory array 1, if the one-bit address signal 8 is 0, it is output to the sense amplifier 3 at one side of the lower memory array 2, specifically, it is read by the column address decoding circuit 5 and the sense amplifier 3 at the lower end of the memory array, the invention can reduce the length of the bit line by half, so that the load of the bit line is reduced, meanwhile, when the one-bit address signal 8 is selected to be connected with the upper memory array 1, the judgment and selection process is opposite to the above result, specifically, there is a practical situation to decide when the inverter is connected with the upper memory array 1 or the lower memory array 2, the invention is not limited.

The invention relates to a large-scale storage array rapid reading circuit structure, which comprises a plurality of storage array circuit structures;

the plurality of memory array fast reading circuit structures are connected through a hierarchical word line structure and a multi-path selection bit line technology.

The circuit structure comprises a preselection reading operation module, a time sequence control module, an X address buffer, a Y address buffer and an IO buffer;

the output end of the X address buffer is respectively connected with a time sequence control module and a pre-decoding circuit of a pre-selection reading operation module;

the input end of the Y address buffer is connected with a column address decoding circuit 5 of the preselection reading operation module, and the output end of the Y address buffer is connected with the time sequence control module;

the output end of the time sequence control module is connected with a sensitive amplifier 3 of a preselection reading operation module;

the IO buffer is bidirectionally connected to all sense amplifiers 3.

In another preferred embodiment of the present invention, as shown in FIG. 5, a 1Mbit memory circuit formed by using a memory array circuit structure of the present invention,

the memory array is divided into 4 memory cell arrays, the capacity of each memory array is 256Kbit, the memory array comprises 512 rows and 512 columns, each memory array module is provided with circuits consisting of a column address decoding circuit 5, a sensitive amplifier 3 and a read-write driving module 4 at the upper side and the lower side, when the address is effective, block selection is carried out by one address, a specific working block in the four memory arrays is determined, then upper and lower bit lines are selected in the selected block by one address signal 8, if the selected bit line is an upper bit line, data are read through the sensitive amplifier 3 at the upper part, otherwise, the data are read through the sensitive amplifier 3 at the lower part, and then the data are transmitted to an IO end.

If the conventional design architecture is used, there are 512 word lines and 512 bit lines in each memory array module, i.e., 512 memory cells on each bit line. If the physical size of a memory cell in the layout design is W (word line direction) × L (bit line direction). The load length of one bit line is 512L, if the lumped method is adopted for calculation, the load resistance is R, and the load capacitance is C.

By adopting the architecture design circuit, the memory array is designed by dividing the bit lines, so that the number of the cells on one bit line is reduced by half, namely, only 256 memory cells are arranged on one bit line, the load length is reduced to 256L, which is 1/2 originally, and because the load resistance and the load capacitance are both in direct proportion to the length of the load line, the load resistance is R1-R/2, and the load capacitance is C1-C/2. When the memory is read, one of the two bit lines is discharged, the other bit line is kept at the precharge value VDD, and when the voltage V (t) on the discharged bit line is reduced from VDD to 80% VDD, the following formula is satisfied according to the inherent response of the RC circuit:

v(t)＝V0×e^^(-t/RC)(where V0 is the supply voltage VDD).

From this can be derived

From the above equation, it can be calculated that when the load resistance R and the load capacitance C are both reduced to 1/2, the time t required for the voltage to be reduced to the same magnitude can be reduced to 1/4.

Therefore, compared with the common architecture, the circuit structure can shorten the length of the bit line to half of the original length, reduce the load of the bit line to half of the original load, accelerate the data access speed of the memory, and simultaneously reduce the discharge amplitude of the bit line, thereby reducing the power consumption; compared with a circuit architecture of multi-level partitioning, the circuit architecture saves area.