阅读说明：本技术 Adc抗干扰性能提升系统及方法 (ADC anti-interference performance improving system and method ) 是由 袁少华 杨磊 蔡占成 于 2021-08-26 设计创作，主要内容包括：本发明提供一种ADC抗干扰性能提升系统及方法,该提升系统包括：ADC接地端、ADC模块和N阱,ADC接地端为ADC模块提供独立接地端；N阱将ADC接地端和ADC模块进行物理隔离。本发明通过提供ADC独立接地端控制ADC模块接地端电压,同时采用N阱进行物理隔离,从而提升ADC抗干扰性能。(The invention provides a system and a method for improving the anti-interference performance of an ADC (analog to digital converter), wherein the system for improving the anti-interference performance of the ADC comprises: the ADC grounding end provides an independent grounding end for the ADC module; the N-well physically isolates the ADC ground from the ADC module. The invention controls the voltage of the ADC module ground terminal by providing the independent ADC ground terminal, and simultaneously adopts the N-well for physical isolation, thereby improving the anti-interference performance of the ADC.)

1. An ADC anti-interference performance improving system, comprising: an ADC ground terminal, an ADC module and an N-well,

the ADC grounding end is used for providing an independent grounding end for the ADC module;

the N trap is used for physically isolating the ADC grounding end and the ADC module.

2. The lift system of claim 1, wherein the ADC ground, the ADC module, and the N-well are internal to an MCU, the MCU further comprising an IO module and an RC module.

3. The lift system of claim 1, further comprising: an IO module and an RC module.

4. The lift system of claim 2, further comprising:

and separately packaging the ADC grounding end to the MCU external grounding end.

5. The hoisting system of any one of claims 2 or 3,

the ADC grounding end is respectively physically isolated from the IO module and the RC module by the N well;

the N-well physically isolates the ADC module from the IO module and the RC module respectively.

6. The lift system of claim 5, wherein the ADC ground is connected to a ground of the ADC module.

7. The hoisting system of claim 5,

the IO module and the RC module are connected with a first grounding end, and the ADC grounding end and the first grounding end are positioned in two network layers.

8. The boost system of claim 6, wherein a parasitic resistance is included between the ADC ground and the ground of the ADC module, and wherein a voltage difference exists between the ground of the ADC module and the ADC ground.

9. The lift system of claim 1, wherein the N-well is on a wafer P-substrate.

10. An ADC anti-interference performance improving method is characterized by comprising the following steps:

providing an independent ground terminal for the ADC module;

physically isolating an ADC ground from the ADC module.

Technical Field

The invention relates to the technical field of electronic circuits, in particular to an ADC anti-interference improving system and method.

Background

The MCU (Microcontroller Unit, microcontrol Unit) chip includes an ADC (Analog-to-Digital Converter) module, an RC (Resistor-capacitor) module and an IO (Input-Output) module inside, the RC module and the IO module have relatively large interference to the ADC module, wherein the IO module often has a relatively strong current Output capability, that is, the NMOS transistor of the IO module has a relatively large current to the ground terminal of the MCU chip. If the ground terminal resistance is 0 and the IO module output current is large, the ground terminal of the ADC module is not at zero potential but has a voltage of tens of millivolts or even hundreds of millivolts, which greatly affects the accuracy of the ADC module. Therefore, the voltage at the ground terminal of the ADC module is controlled, and meanwhile, the improvement of the ADC anti-interference performance becomes a technical problem to be solved at present.

Disclosure of Invention

The invention provides an ADC anti-interference performance improving system and method, which are used for solving the problems that the voltage of an ADC module ground terminal cannot be accurately controlled and the ADC anti-interference performance is low in the prior art.

In a first aspect, the present invention provides a system for improving the anti-interference performance of an ADC, including: an ADC ground terminal, an ADC module and an N-well,

the ADC grounding end is used for providing an independent grounding end for the ADC module;

and the N trap is used for physically isolating the ADC grounding end from the ADC module.

Optionally, the ADC ground, the ADC module, and the N-well are located inside the MCU, and the MCU further includes an IO module and an RC module.

Optionally, the ADC interference rejection performance improving system further includes: an IO module and an RC module.

Optionally, the ADC ground is separately packaged to the MCU external ground.

Optionally, the N-well physically isolates the ADC ground terminal from the IO module and the RC module, respectively; the N-well physically isolates the ADC module from the IO module and the RC module respectively.

Optionally, the ADC ground terminal is connected to the ground terminal of the ADC module.

Optionally, the IO module and the RC module are connected to a first ground terminal, and the ADC ground terminal and the first ground terminal are located in two network layers.

Optionally, a parasitic resistor is included between the ADC ground and the ground of the ADC module, and a voltage difference exists between the ground of the ADC module and the ADC ground.

Optionally, the N-well is on a wafer P-substrate.

On the other hand, the invention provides a method for improving the anti-interference performance of an ADC, which comprises the following steps: providing an independent ground terminal for the ADC module; the ADC ground is physically isolated from the ADC block.

According to the technical scheme, the invention comprises the following steps: the ADC grounding end is used for providing an independent grounding end for the ADC module; and the N trap is used for physically isolating the ADC grounding end from the ADC module. The invention controls the voltage of the ADC module ground terminal by providing the independent ADC ground terminal, and simultaneously adopts the N-well for physical isolation, thereby improving the anti-interference performance of the ADC.

Drawings

Fig. 1 is a schematic structural diagram of an ADC anti-interference performance improving system according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of an MCU internal module according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of an ADC anti-interference performance improving system according to an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of a physical isolation provided in accordance with an embodiment of the present invention;

fig. 5 is a schematic flowchart of a method for improving the anti-interference performance of an ADC according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 shows a schematic structural diagram of an ADC anti-interference performance improving system according to an embodiment of the present invention, and as shown in fig. 1, the improving system according to this embodiment includes: ADC ground, ADC module and N-well.

In a specific embodiment, the ADC ground terminal 11 is used to provide an independent ground terminal for the ADC block 12, and the N-well 13 is used to physically isolate the ADC ground terminal 11 from the ADC block 12. The ADC ground terminal 11 is connected to the ground terminal of the ADC module 12, the parasitic resistance between the two ground terminals is small, there is no shared parasitic resistance with other modules, and the ADC ground terminal 11 is directly connected to the external ground, thereby ensuring that the ground terminal voltage of the ADC module 12 is small, and improving the accuracy of the ADC. Meanwhile, the ADC grounding end 11 and the ADC module 12 are surrounded by the N-well, and the ADC grounding end 11 and the ADC module 12 are physically isolated from interference of other modules, so that the anti-interference performance of the ADC is improved.

In a specific embodiment, the ADC anti-interference performance improving system may be located inside the MCU and used as an internal module of the MCU chip, and may also be used as a part of an electronic circuit design separately, for example, in a layout design, the solder plate includes an IO module and an RC module, the ADC module 12 is connected to the IO module and the RC module, in order to reduce interference of the IO module and the RC module to the ADC module 12, the ADC ground terminal 11 may be added in the layout design to provide an independent ground terminal for the ADC module 12, and the N-well 13 is added to physically isolate the ADC ground terminal 11 and the ADC module 12 from the IO module and the RC module, respectively.

In MCU chip domain design, ADC earthing terminal 11 connects the earthing terminal of ADC module 12, provide independent earthing terminal for ADC module 12, encapsulate ADC earthing terminal 11 alone to the outside earthing terminal of MCU, the inside IO module of MCU chip and the inside earthing terminal of RC module sharing MCU, ADC earthing terminal 11 and the inside earthing terminal of MCU are in two network layers, ADC earthing terminal 11 and IO module and RC module have not shared parasitic resistance promptly, even IO module and RC module have the heavy current, also can not lift the electric potential of ADC module 12 earthing terminal, can improve ADC module 12's precision.

In the layout design, the N well 12 surrounds the ADC grounding end 11 and the ADC module 12, the ADC grounding end 11 and the ADC module 12 are physically isolated from the IO module and the RC module respectively, the influence of the IO module and the RC module on the ADC module is isolated, and the anti-interference performance of the ADC module can be improved.

Fig. 2 shows a circuit schematic diagram of an MCU internal module according to an embodiment of the present invention, and as shown in fig. 2, the MCU internal module of this embodiment includes an ADC module, an IO module, and an RC module.

In a specific embodiment, the ADC module, the IO module and the RC module are connected to a common ground GND, the resistors R1, R2 and R3 are parasitic resistors of the conductive wires, and the ADC module has a current I to GND₁The RC module has current I to GND₂Because the IO module has stronger current output capability, namely, the NMOS tube of the IO module has larger current I to GND₃The IO block and the ADC block have a common parasitic resistance R3. Assuming that GND is zero potential, the far end potential of R3 is (I)₁+I₂+I₃)*R3，I₃If it is notThe GND of the ADC module is not zero potential but has voltage of dozens of millivolts or even hundreds of millivolts, so that the precision of the ADC module is greatly influenced, and the anti-interference performance of the ADC is poor.

Fig. 3 is a schematic circuit diagram of an ADC anti-interference performance improving system according to an embodiment of the present invention, and as shown in fig. 3, the ADC anti-interference performance improving system according to this embodiment includes an ADC ground terminal, an N well, an ADC module, an IO module, and an RC module.

In one embodiment, the ADC ground GND provides an independent ground for the ADC module, and the GNDA is connected to the ground GND of the ADC module. A parasitic resistor R1 is included between GNDA and ground GND of ADC module, and the ADC module has current I to GNDA₁The RC module pair GND1 has current I₂Because the IO module has stronger current output capability, namely, the NMOS tube of the IO module has larger current I to GND1₃。

When the anti-interference performance improving system is arranged inside the MCU, a GNDA pad can be additionally arranged in the MCU layout design, the ADC grounding end is independently packaged to the external grounding end of the MCU, and when the anti-interference performance improving system is part of circuit design, the ADC grounding end is independently connected to the external grounding end of the layout design, namely, the GNDA is ensured to be at zero potential.

The difference I between the ground GND and GNDA of the ADC module₁The R1, the IO module and the RC module are connected with a first grounding end GND1, the GNDA and the GND1 are not connected together, no parasitic resistor is shared, and the GNDA and the GND1 are located in two network layers of the layout design. High current I of IO module₃The grounding end of the ADC module is not affected, the precision of the ADC module is not affected by the IO module and the RC module, and the anti-interference performance of the ADC module is favorably improved.

The N-well physically isolates the ADC grounding end and the ADC module from the IO module and the RC module respectively, namely the ADC grounding end and the ADC module are surrounded by the N-well respectively, so that the ADC module is physically isolated from other modules, the ADC module is not influenced by the IO module and the RC module, and the anti-interference performance of the ADC module is further improved.

Fig. 4 is a schematic cross-sectional view illustrating physical isolation provided by an embodiment of the invention, as shown in fig. 4, the physical isolation of the embodiment includes an N-well and a P-substrate.

In a specific embodiment, a lightly doped P-type silicon wafer is used as a substrate, an N-well is formed on the substrate, namely the N-well is positioned on a P-substrate of the wafer, the ADC ground terminal and the ADC module are placed in the N-well to isolate noise of the P-substrate, and the ADC ground terminal and the ADC module are surrounded by the N-well to be physically isolated from other modules on a layout, so that influence of other modules on the ADC module is reduced, and therefore anti-interference performance of the ADC module is improved.

Fig. 5 is a schematic flowchart illustrating an ADC anti-interference performance improving method according to an embodiment of the present invention, and as shown in fig. 5, the improving method according to the embodiment includes:

501. providing an independent ground terminal for the ADC module;

502. the ADC block is physically isolated from the ADC ground.

Because the method is based on the lifting system, the working principle of the method is the same as that of the lifting system, and the detailed description is omitted here.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Those of ordinary skill in the art will understand that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions and scope of the present invention as defined in the appended claims.