阅读说明：本技术 一种实现可靠性测试及阻值偏差补偿的压阻式传感器 (Piezoresistive sensor for realizing reliability test and resistance value deviation compensation ) 是由 黄晓东 张鹏飞 王广猛 熊强 李宇翱 张志强 于 2021-10-27 设计创作，主要内容包括：本发明公开了一种实现可靠性测试及阻值偏差补偿的压阻式传感器,包括压力敏感薄膜、压敏电阻、隧穿层,电荷存储层设置在隧穿层的上表面,并位于压敏电阻的上方,且部分覆盖压敏电阻；阻挡层完全覆盖隧穿层和电荷存储层的上表面；压阻电极设置在阻挡层的上表面,并穿过隧穿层和阻挡层上的通孔与压敏电阻电连接；调控电极设置在阻挡层的上表面,与压阻电极相间隔,并部分覆盖电荷存储层。其中,压敏电阻、隧穿层、电荷存储层、阻挡层与调控电极构成电荷型非易失性存储器结构,该结构能够实现定量调控电荷存储层中的俘获电荷数目以及通过俘获的电荷调控压敏电阻的载流子浓度进而调整压敏电阻的阻值,从而实现压敏电阻的有效修正与补偿。(The invention discloses a piezoresistive sensor for realizing reliability test and resistance value deviation compensation, which comprises a pressure sensitive film, a piezoresistor and a tunneling layer, wherein a charge storage layer is arranged on the upper surface of the tunneling layer, is positioned above the piezoresistor and partially covers the piezoresistor; the blocking layer completely covers the upper surfaces of the tunneling layer and the charge storage layer; the piezoresistive electrode is arranged on the upper surface of the blocking layer and penetrates through the tunneling layer and the through hole in the blocking layer to be electrically connected with the piezoresistor; the regulating electrode is arranged on the upper surface of the barrier layer, is spaced from the piezoresistive electrode and partially covers the charge storage layer. The structure can realize quantitative regulation of the number of trapped charges in the charge storage layer and regulation of the carrier concentration of the piezoresistor through the trapped charges so as to adjust the resistance value of the piezoresistor, thereby realizing effective correction and compensation of the piezoresistor.)

1. A piezoresistive sensor for realizing reliability test and resistance value deviation compensation is characterized by comprising a substrate (1), a piezoresistor (2), a tunneling layer (3), a charge storage layer (4), a barrier layer (5), a piezoresistive electrode (6), a regulation electrode (7) and a pressure sensitive film (8); forming the pressure sensitive film (8) after processing a cavity on the back of the substrate (1); the piezoresistor (2) is arranged in the center of the pressure sensitive film (8); the tunneling layer (3) completely covers the substrate (1) and the upper surface of the piezoresistor (2); the charge storage layer (4) is arranged on the upper surface of the tunneling layer (3), is positioned above the piezoresistor (2), and partially covers the piezoresistor (2); the blocking layer (5) completely covers the upper surfaces of the tunneling layer (3) and the charge storage layer (4); the piezoresistive electrode (6) is arranged on the upper surface of the blocking layer (5) and penetrates through the tunneling layer (3) and the through hole in the blocking layer (5) to be electrically connected with the piezoresistor (2); the regulating electrode (7) is arranged on the upper surface of the blocking layer (5), is spaced from the piezoresistive electrode (6) and covers the charge storage layer (4); the piezoresistor (2), the tunneling layer (3), the charge storage layer (4), the blocking layer (5) and the regulating electrode (7) form a charge type nonvolatile memory structure.

2. Piezoresistive sensor for reliability testing and resistance deviation compensation according to claim 1, characterized in that the tunneling layer (3) is SiO grown by thermal oxidation₂The thickness is 3-10 nm.

3. The piezoresistive sensor for realizing reliability testing and resistance value deviation compensation according to claim 1, wherein the charge storage layer (4) is a charge storage thin film grown by physical vapor deposition or chemical vapor deposition, and the thickness is 10-50 nm.

4. Piezoresistive sensor for implementing a reliability test and a resistance variation compensation according to claim 1 or 2, characterized in that the barrier layer (5) is Al grown by atomic layer deposition₂O₃The thickness is 10-50 nm.

Technical Field

The invention relates to a piezoresistive sensor and a preparation method thereof.

Background

MEMS piezoresistive sensors include various types such as piezoresistive pressure sensors, piezoresistive inertial sensors, piezoresistive flow sensors, etc., and are widely used in the fields of industrial production, aerospace, power machinery, biomedical, etc., and in order to know the state and life of the sensor, the reliability of the sensor needs to be evaluated. The reliability of piezoresistive sensors can generally be divided into mechanical and electrical reliability. Conventionally, the reliability of piezoresistive sensors has been focused on the mechanical reliability such as stress, strain, and strength of the structure, and the electrical reliability has been paid little attention. In fact, charge defects exist in the passivation layer of the sensor generally, the defects can trap charges, the charges trapped in the passivation layer can affect the carrier concentration of the piezoresistor, and then the performance of the sensor drifts, and on the other hand, the charge defects in the passivation layer and the number of the charges trapped by the charge defects are difficult to regulate and measure, so that the problem of the electrical reliability of the sensor caused by the charge defects and the number of the charges trapped by the charge defects are difficult to quantitatively study. In addition, after the piezoresistor of the traditional MEMS piezoresistive sensor is manufactured, the resistance value of the piezoresistor is difficult to change, so that it is difficult to correct and compensate for the deviation between the actual resistance value and the designed resistance value of the piezoresistor.

Disclosure of Invention

The purpose of the invention is as follows: aiming at the prior art, the piezoresistive sensor for realizing reliability test and resistance deviation compensation is provided, and the problems that the electrical reliability of the piezoresistive sensor is difficult to quantitatively research and the resistance deviation generated in the preparation process of the piezoresistor is difficult to compensate are solved.

The technical scheme is as follows: a piezoresistive sensor for realizing reliability test and resistance value deviation compensation comprises a substrate, a piezoresistor, a tunneling layer, a charge storage layer, a barrier layer, a piezoresistive electrode, a regulating electrode and a pressure sensitive film; forming the pressure sensitive film after processing a cavity on the back of the substrate; the piezoresistor is arranged in the center of the pressure sensitive film; the tunneling layer completely covers the substrate and the upper surface of the piezoresistor; the charge storage layer is arranged on the upper surface of the tunneling layer, is positioned above the piezoresistor and partially covers the piezoresistor; the blocking layer completely covers the upper surfaces of the tunneling layer and the charge storage layer; the piezoresistive electrode is arranged on the upper surface of the blocking layer and penetrates through the tunneling layer and the through hole in the blocking layer to be electrically connected with the piezoresistor; the control electrode is arranged on the upper surface of the blocking layer, is spaced from the piezoresistive electrode and covers the charge storage layer; the piezoresistor, the tunneling layer, the charge storage layer, the blocking layer and the regulating electrode form a charge type nonvolatile memory structure.

Further, the tunneling layer is SiO grown by thermal oxidation₂The thickness is 3-10 nm.

Furthermore, the charge storage layer is a charge storage thin film grown by physical vapor deposition or chemical vapor deposition, and the thickness of the charge storage thin film is 10-50 nm.

Further, the barrier layer is Al grown by means of atomic layer deposition₂O₃The thickness is 10-50 nm.

Has the advantages that: compared with the prior art, the invention has the following advantages:

1. the structure of the invention can quantitatively regulate and control the number of trapped charges in the charge storage layer, and provides a premise and guarantee for quantitatively researching the influence of the trapped charges on the electrical reliability of the piezoresistive sensor.

2. The structure of the invention can adjust the carrier concentration of the piezoresistor through the trapped charges even after the preparation is finished, so as to adjust the resistance value of the piezoresistor, thereby realizing the effective correction and compensation of the piezoresistor.

3. The structure of the invention can be prepared by MEMS process with high precision, high consistency and low cost, can be applied to various piezoresistive sensors and has wide application.

Drawings

FIG. 1 is a schematic cross-sectional view of a piezoresistive sensor according to the present invention;

FIG. 2 is a schematic structural view after step 1 of the structure preparation method of the present invention;

FIG. 3 is a schematic structural view after step 2 of the structure preparation method of the present invention;

FIG. 4 is a schematic structural view after step 3 of the structure preparation method of the present invention;

FIG. 5 is a schematic view of the structure after step 4 of the structure preparation method of the present invention;

FIG. 6 is a schematic diagram of the structure after step 5 of the structure fabrication method of the present invention;

FIG. 7 is a schematic view of the structure after step 6 of the structure preparation method of the present invention;

fig. 8 is a schematic structural view after step 7 of the structure preparation method of the present invention.

Detailed Description

The invention is further explained below with reference to the drawings.

As shown in fig. 1, a piezoresistive sensor for implementing reliability test and resistance value deviation compensation includes a substrate 1, a piezoresistor 2, a tunneling layer 3, a charge storage layer 4, a blocking layer 5, a piezoresistive electrode 6, a control electrode 7, and a pressure sensitive film 8.

Forming a pressure sensitive film 8 after processing a cavity on the back of the substrate 1; the piezoresistor 2 is arranged in the center of the pressure sensitive film 8; the tunneling layer 3 completely covers the substrate 1 and the upper surface of the piezoresistor 2; the charge storage layer 4 is arranged on the upper surface of the tunneling layer 3, is positioned above the piezoresistor 2 and partially covers the piezoresistor 2; the blocking layer 5 completely covers the upper surfaces of the tunneling layer 3 and the charge storage layer 4; the piezoresistive electrode 6 is arranged on the upper surface of the barrier layer 5 and penetrates through the tunneling layer 3 and the through hole in the barrier layer 5 to be electrically connected with the piezoresistor 2; the regulating electrode 7 is arranged on the upper surface of the barrier layer 5, is spaced from the piezoresistive electrode 6 and covers the charge storage layer 4; the piezoresistor 2, the tunneling layer 3, the charge storage layer 4, the blocking layer 5 and the regulation electrode 7 form a charge type nonvolatile memory structure.

Wherein, the material of the substrate 1 is monocrystalline silicon, and the thickness is 200-2000 μm. The thickness of the pressure-sensitive film 8 is 5 to 20 μm. The tunneling layer 3 is SiO grown by thermal oxidation₂To reduce the charge defects in the tunneling layer, with a thickness of 3-10 nm. The material of the charge storage layer 4 comprises a polycrystalSilicon, Si₃N₄、HfO₂、ZrO₂Etc., preferably by physical vapor deposition or chemical vapor deposition, which is advantageous in increasing the number of charge defects of the charge storage layer and thus increasing the number of charge storages, with a thickness of 10-50 nm. The barrier layer 5 is Al grown by Atomic Layer Deposition (ALD)₂O₃So as to ensure that a high-quality barrier layer with less charge defects grows at low temperature, and the thickness is 10-50 nm. The piezoresistive electrode 6 and the control electrode 7 are made of metal, preferably at least one of Al, Ti, Au, Cu and Pt, and have a thickness of 100-500 nm.

In the structure, the composite structure of the tunneling layer 3 and the blocking layer 5 forms the passivation layer of the piezoresistor 2, the passivation layer has few charge defects, and the influence of the charge defects in the passivation layer on the electrical reliability of the piezoresistor 2 can be effectively inhibited.

The working principle of the piezoresistive sensor for realizing reliability test and resistance value deviation compensation is as follows:

the piezoresistor 2, the tunneling layer 3, the charge storage layer 4, the blocking layer 5 and the regulating electrode 7 form a charge type nonvolatile memory structure, the number of trapped charges in the charge storage layer 4 can be regulated by applying voltage on the regulating electrode 7, and the tunneling layer 3 and the blocking layer 5 prevent the charges trapped in the charge storage layer 4 from losing. The number of charges trapped in the charge storage layer 4 can be regulated and controlled by the voltage and the polarity applied to the regulating and controlling electrode 7, and can be quantitatively obtained according to the capacitor flat band voltage drift formed by the charge type nonvolatile memory structure, so that the structure provides a premise and guarantee for quantitatively researching the influence of the trapped charges on the electrical reliability of the piezoresistive sensor.

In addition, the charges trapped in the charge storage layer 4 are not lost, so that the charge storage layer can be used as a built-in power supply, and the number of the charges trapped in the charge storage layer 4 can be dynamically adjusted according to the deviation between the actual resistance value and the designed resistance value of the piezoresistor. The charge trapped in the charge storage layer 4 is used as a built-in power supply to regulate the carrier concentration of the piezoresistor 2 so as to regulate the resistance of the piezoresistor 2, thereby realizing the correction and compensation of the resistance deviation of the piezoresistor 2.

The preparation method of the hair structure comprises the following steps:

step 1: an N-type (100) silicon wafer with the thickness of 300 microns is selected as a substrate 1, as shown in FIG. 2;

step 2: preparing a P-type piezoresistor 2 on a substrate 1 by photoetching and ion implantation, as shown in FIG. 3;

and step 3: growing a layer of SiO with the thickness of 5nm on the upper surface of the substrate 1 by means of thermal oxidation₂As a tunneling layer 3, as shown in fig. 4;

and 4, step 4: si with a thickness of 10nm is prepared on the upper surface of the tunneling layer 3 by PECVD (Plasma Enhanced Chemical Vapor Deposition) and photolithography₃N₄As the charge storage layer 4, as shown in fig. 5;

and 5: preparation of Al with a thickness of 50nm on the upper surfaces of the tunneling layer 3 and the charge storage layer 4 by ALD₂O₃As a barrier layer 5, as shown in fig. 6;

step 6: forming via holes in the tunneling layer 3 and the blocking layer 5 by photolithography and RIE (Reactive Ion Etching), as shown in fig. 7;

and 7: preparing aluminum with the thickness of 200nm on the upper surface of the barrier layer 5 as a piezoresistive electrode 6 and a control electrode 7 by electron beam evaporation and photoetching stripping, as shown in fig. 8;

and 8: the back of the substrate 1 is etched back by KOH to form an open cavity and a pressure sensitive film 8 with a thickness of 10mm, and the device is fabricated as shown in fig. 1.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.