阅读说明：本技术 显示装置 (Display device ) 是由 车娜贤 孙宣权 于 2021-04-22 设计创作，主要内容包括：一种显示装置,包括：基板；被布置在基板上并且在第一方向上延伸的栅线；被布置在栅线上的栅绝缘层；被布置在栅绝缘层上并且在与第一方向交叉的第二方向上延伸的数据线；被布置在栅绝缘层上并且在第二方向上延伸的栅电压供应线,该栅电压供应线连接到栅线；被布置在数据线和栅电压供应线上的钝化层；被布置在钝化层上的屏蔽电极；被布置在屏蔽电极上的绝缘层；以及被布置在绝缘层上并且与屏蔽电极重叠的像素电极。(A display device, comprising: a substrate; a gate line disposed on the substrate and extending in a first direction; a gate insulating layer disposed on the gate line; a data line disposed on the gate insulating layer and extending in a second direction crossing the first direction; a gate voltage supply line disposed on the gate insulating layer and extending in the second direction, the gate voltage supply line being connected to the gate line; a passivation layer disposed on the data line and the gate voltage supply line; a shield electrode disposed on the passivation layer; an insulating layer disposed on the shielding electrode; and a pixel electrode disposed on the insulating layer and overlapping the shielding electrode.)

1. A display device, comprising:

a substrate;

a gate line disposed on the substrate and extending in a first direction;

a gate insulating layer disposed on the gate line;

a data line disposed on the gate insulating layer and extending in a second direction crossing the first direction;

A gate voltage supply line disposed on the gate insulating layer and extending in the second direction, the gate voltage supply line being connected to the gate line;

a passivation layer disposed on the data line and the gate voltage supply line;

a shield electrode disposed on the passivation layer;

an insulating layer disposed on the shielding electrode; and

a pixel electrode disposed on the insulating layer and overlapping the shielding electrode.

2. The display device according to claim 1,

the gate voltage supply line and the data line are disposed on the same layer.

3. The display device according to claim 1, further comprising:

a liquid crystal layer disposed on the pixel electrode; and

a common electrode disposed above or below the liquid crystal layer,

wherein the same common voltage is applied to the common electrode and the shield electrode.

4. The display device according to claim 1,

the shield electrode includes:

a main electrode portion overlapping the pixel electrode; and

a bridge portion disposed between adjacent main electrode portions and extending from the main electrode portions.

5. The display device according to claim 4,

the main electrode portion further overlaps the data line and does not overlap the gate voltage supply line.

6. The display device according to claim 5,

the bridge portion overlaps the gate voltage supply line.

7. The display device according to claim 6,

the bridge portion extends in the first direction, and

the bridge portion has a width narrower than a width of the gate voltage supply line.

8. The display device according to claim 6,

the bridge portion does not overlap with the pixel electrode.

9. The display device according to claim 4, further comprising:

pixels arranged in a matrix along the first and second directions to be connected to the gate and data lines,

wherein three pixel columns in which the pixels are arranged along the second direction are arranged between adjacent gate voltage supply lines, and

the main electrode portion overlaps with three pixel electrodes of the three pixel columns.

10. The display device according to claim 9,

the gate voltage supply line is connected to two gate lines,

One of the three pixel columns is connected to two data lines to which data voltages of different polarities are applied, and

the main electrode portion overlaps six data lines to which the three pixel columns are connected.

Technical Field

The present disclosure relates to a display device.

Background

The display device is a device for displaying an image, and includes a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, and the like. Display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, electronic books, portable game machines, and various terminals.

The display device may include pixels arranged in a row direction and a column direction. Various elements such as a transistor and a capacitor may be arranged in each pixel, and various wirings capable of supplying a signal to each pixel may be arranged in the display device. The wiring may be connected to the driver to receive the signal, and the driver may be disposed at an edge of the display panel.

In order to reduce the area of the bezel that is a portion of the screen that is not displayed on the edge of the display device, it may be considered to move the drivers and the like disposed on the left and right sides of the display device to another position. For example, the driver may not be disposed at the left and right sides of the display device, but the driver may be disposed at the upper side of the display device. In this case, a voltage supply wiring for connecting the driver and a wiring connected to each pixel may be arranged between the pixels, which may have an electrical effect on the display device.

The above information disclosed in the background section is only for enhancement of understanding of the background of the technology and, therefore, it may contain information that does not form the prior art that is known to those of ordinary skill in the art in this country.

Disclosure of Invention

The technology has been made in an effort to provide a display device that can prevent an electrical effect caused by additional wiring while reducing a bezel area.

An embodiment provides a display device including: a substrate; a gate line disposed on the substrate and extending in a first direction; a gate insulating layer disposed on the gate line; a data line disposed on the gate insulating layer and extending in a second direction crossing the first direction; a gate voltage supply line disposed on the gate insulating layer and extending in the second direction, the gate voltage supply line being connected to the gate line; a passivation layer disposed on the data line and the gate voltage supply line; a shield electrode disposed on the passivation layer; an insulating layer disposed on the shielding electrode; and a pixel electrode disposed on the insulating layer and overlapping the shielding electrode.

The gate voltage supply line may be disposed on the same layer as the data line.

The display device may further include: a liquid crystal layer disposed on the pixel electrode; and a common electrode disposed above or below the liquid crystal layer, wherein the same common voltage may be applied to the common electrode and the shield electrode.

The shielding electrode may include: a main electrode portion overlapping the pixel electrode; and a bridge portion disposed between adjacent main electrode portions and extending from the main electrode portions.

The main electrode portion may further overlap the data line and not overlap the gate voltage supply line.

The bridge portion may overlap the gate voltage supply line.

The bridge portion may extend in the first direction, and a width of the bridge portion may be narrower than a width of the gate voltage supply line.

The bridge portion may not overlap the pixel electrode.

The display device may further include: and pixels arranged in a matrix along a first direction and a second direction to be connected to the gate lines and the data lines, wherein three pixel columns, in which the pixels may be arranged along the second direction, are disposed between adjacent gate voltage supply lines, and the main electrode portions may overlap with three pixel electrodes of the three pixel columns.

The gate voltage supply line may be connected to two gate lines, one of the three pixel columns may be connected to two data lines to which data voltages of different polarities are applied, and the main electrode portion may overlap six data lines to which the three pixel columns are connected.

The display device may further include: and pixels arranged in a matrix along a first direction and a second direction to be connected to the gate lines and the data lines, wherein one pixel column in which the pixels are arranged along the second direction may be disposed between adjacent gate voltage supply lines, and the main electrode portion may overlap one pixel electrode of the one pixel column.

The gate voltage supply line may be connected to two gate lines, one pixel column may be connected to two data lines to which data voltages of different polarities are applied, and the main electrode portion may overlap the two data lines to which the one pixel column is connected.

The display device may further include: a thin film transistor connected to the gate and data lines; and an opening in the shield electrode so as to overlap with the thin film transistor.

The thin film transistor may include: a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode, and may further include: a pixel opening in the passivation layer and the insulating layer to overlap the drain electrode and the pixel electrode, wherein the pixel electrode may be connected to the drain electrode through the pixel opening, and the opening may overlap the pixel opening.

The opening may surround the pixel opening.

The shielding electrode may include a transparent metal oxide.

An embodiment provides a display device including: a substrate; gate and data lines disposed on the substrate and crossing each other; a gate voltage supply line disposed on the same layer as the data line and connected to the gate line; a thin film transistor connected to the gate and data lines; a pixel electrode connected to the thin film transistor; and a shielding electrode disposed between the data line and the pixel electrode.

The shielding electrode may include: a main electrode portion overlapping the pixel electrode; and a bridge portion disposed between adjacent main electrode portions and extending from the main electrode portions.

The main electrode portion may further overlap the data line, and may not overlap the gate voltage supply line.

The bridge portion may overlap the gate voltage supply line and may not overlap the pixel electrode, and a width of the bridge portion may be narrower than a width of the gate voltage supply line.

According to the embodiment, an electrical effect due to additional wiring may be prevented while reducing a bezel area.

Drawings

Fig. 1 illustrates a layout of a display device according to an embodiment.

Fig. 2 illustrates an equivalent circuit diagram of two adjacent pixels of the display device of fig. 1 according to an embodiment.

Fig. 3 illustrates a top view of a portion of a display device according to an embodiment.

Fig. 4 illustrates a sectional view taken along line IV-IV of fig. 3.

Fig. 5 illustrates a sectional view taken along line V-V of fig. 3.

Fig. 6, 7 and 8 illustrate sequential top views of a manufacturing sequence of a display device according to an embodiment.

Fig. 9 illustrates a top view of a portion of a display device according to an embodiment.

Fig. 10 illustrates a layout of a display device according to an embodiment.

Fig. 11 illustrates a layout of a display device according to an embodiment.

Fig. 12 illustrates a top view of a portion of the display device of fig. 11, in accordance with an embodiment.

Fig. 13 illustrates a sectional view taken along line XIII-XIII of fig. 12.

Fig. 14 illustrates a top view of a portion of a display device according to an embodiment.

Fig. 15 illustrates a sectional view taken along line XV-XV of fig. 14.

Fig. 16 illustrates a cross-sectional view of a portion of a display device according to an embodiment.

Detailed Description

The inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

Parts irrelevant to the description will be omitted to clearly describe the present disclosure, and like reference numerals denote like elements throughout the specification.

Further, in the drawings, the size and thickness of each element are arbitrarily illustrated for convenience of description, and the present disclosure is not necessarily limited to those illustrated in the drawings. In the drawings, the thickness of layers, films, panels, regions, and other features are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for convenience of description.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Further, in the specification, the word "on" or "above" means on or disposed over the target portion, and does not necessarily mean on or disposed on the upper side of the target portion based on the direction of gravity.

Furthermore, unless explicitly described to the contrary, the word "comprise", and variations such as "comprises" or "comprising", will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, throughout the specification, the phrase "in a plan view" or "on a plane" means to view the target portion from the top, and the phrase "in a cross section" or "on a cross section" means to view a cross section formed by cutting the target portion perpendicularly from the side.

First, a display device according to an embodiment will be described with reference to fig. 1 and 2.

Fig. 1 illustrates a layout of a display device according to an embodiment. Fig. 2 illustrates an equivalent circuit diagram of two adjacent pixels of the display device of fig. 1 according to an embodiment.

As shown in fig. 1, the display device according to the embodiment includes a first substrate 110, pixels PX arranged on the first substrate 110, and a gate driver 500 and a data driver 600 generating signals for driving the pixels PX.

The pixels PX may be arranged in a matrix form along a row direction and a column direction. However, the structural form of the pixel PX is only an example, and may be variously changed. The pixel PX is a unit for displaying an image. One pixel PX uniquely displays one of the primary colors, or the pixels PX alternately display the primary colors according to time, and thus a desired color can be displayed by a spatial or temporal sum of the primary colors.

The display device according to the embodiment may further include a gate line 121 and a data line 171 disposed on the first substrate 110. Each pixel PX is connected to the gate line 121 and the data line 171. The gate lines 121 may mainly extend in a first direction (e.g., a row direction), and the data lines 171 may extend in a second direction (e.g., a column direction) crossing the first direction. The gate lines 121 and the data lines 171 may be orthogonal to each other. The gate line 121 may transmit a gate signal (also referred to as a "scan signal") including a gate-on voltage to turn on a transistor as a switching element and a gate-off voltage to turn off the transistor. The data lines 171 may transmit data voltages corresponding to image signals. When the transistor is turned on, the pixel PX may receive the data voltage from the data line 171.

Although not shown, the display device may further include a signal controller. The signal controller may control the gate driver 500 and the data driver 600. The signal controller receives an image signal and a control signal for the image signal from an external graphic processor (not shown). The control signal includes, for example, a horizontal synchronization signal, a vertical synchronization signal, a clock signal, a data enable signal, and the like. The signal controller may process the image signal according to an operating condition of the display device based on the image signal and the control signal, and then may generate and output image data, a gate control signal, a data control signal, and a clock signal.

The gate driver 500 may receive a gate control signal from the signal controller, generate a gate signal including a gate-on voltage and a gate-off voltage, and apply the generated gate signal to the gate line 121. The display device according to the embodiment may further include a gate voltage supply line 127 disposed on the first substrate 110. The gate voltage supply line 127 may mainly extend in the second direction (e.g., the column direction). The gate voltage supply line 127 may extend in a direction parallel to the data line 171 and may cross the gate line 121. The gate voltage supply line 127 may be connected to the gate driver 500 to receive a gate signal from the gate driver 500. A gate voltage supply line 127 may be connected to the gate line 121 to transmit a gate signal to the gate line 121. That is, the gate voltage supply line 127 is connected between the gate driver 500 and the gate line 121. The gate voltage supply lines 127 may extend parallel to each other, and one gate voltage supply line 127 may be connected to one or more gate lines 121. For example, each gate voltage supply line 127 may be connected to two gate lines 121. However, one gate voltage supply line 127 may be connected to one gate line 121 or three or more gate lines 121.

The data driver 600 receives a data control signal and image data from the signal controller, converts the image data into a data signal (e.g., a data voltage) by using a gray voltage generated by a gray voltage generator (not shown), and applies the converted data signal to the data lines 171. Two data lines 171 may pass between two adjacent pixels PX in the row direction. Further, the data lines 171 may be arranged at both sides on a pixel column basis. Some of the pixels PX included in one pixel column may be connected to the data line 171 arranged at the left side of the pixel column, and the remaining pixels PX included in the pixels PX in the pixel column may be connected to the data line 171 arranged at the right side of the pixel column. For example, the pixels PX arranged in the first pixel row may be connected to the data lines 171 arranged at the left side of the corresponding pixels PX, and the pixels PX arranged in the second pixel row may be connected to the data lines 171 arranged at the right side of the corresponding pixels PX. In this case, the pixels PX arranged at the first pixel row and the second pixel row may receive the same gate signal from the same gate voltage supply line 127. The pixels PX arranged in the third pixel row may be connected to the data lines 171 arranged at the right side of the corresponding pixels PX, and the pixels PX arranged in the fourth pixel row may be connected to the data lines 171 arranged at the left side of the corresponding pixels PX. In this case, the pixels PX arranged at the third pixel row and the fourth pixel row may receive the same gate signal from the same gate voltage supply line 127.

The data voltage of the positive polarity may be applied to some data lines 171, and the data voltage of the negative polarity may be applied to some other data lines 171. Data voltages of different polarities may be applied to two data lines 171 connected to one pixel column. Further, data voltages having the same polarity may be applied to two data lines 171 arranged between two adjacent pixels in the row direction. For example, a data voltage of a positive polarity may be applied to the data lines 171 arranged at the left side of the two data lines 171 connected to the first pixel column, and a data voltage of a negative polarity may be applied to the data lines 171 arranged at the right side of the two data lines 171 connected to the first pixel column. Further, a data voltage of a negative polarity may be applied to the data lines 171 arranged at the left side of the two data lines 171 connected to the second pixel column, and a data voltage of a positive polarity may be applied to the data lines 171 arranged at the right side of the two data lines 171 connected to the second pixel column. Further, a data voltage of a positive polarity may be applied to the data lines 171 arranged at the left side of the two data lines 171 connected to the third pixel column, and a data voltage of a negative polarity may be applied to the data lines 171 arranged at the right side of the two data lines 171 connected to the third pixel column.

Three pixel columns may be disposed between adjacent gate voltage supply lines 127. However, the number of pixel columns disposed between the adjacent gate voltage supply lines 127 may be variously changed. For example, one pixel column may be disposed between adjacent gate voltage supply lines 127, or two pixel columns may be disposed between adjacent gate voltage supply lines 127. The gate voltage supply line 127 may be disposed between two adjacent pixels PX, and the data line 171 may be disposed between the gate voltage supply line 127 and the pixels PX. The gate voltage supply line 127 may be disposed between two adjacent data lines 171.

As shown in fig. 2, each pixel PX includes a thin film transistor Q connected to the gate line 121 and the data line 171, and a liquid crystal capacitor Clc connected to the thin film transistor Q. A control terminal of the thin film transistor Q may be connected to the gate line 121, an input terminal of the thin film transistor Q may be connected to the data line 171, and an output terminal of the thin film transistor Q may be connected to the liquid crystal capacitor Clc. Although not shown, each pixel PX may further include a storage capacitor connected to the thin film transistor Q. Two adjacent gate lines 121 may be connected to the same gate voltage supply line 127.

When a gate-on voltage is applied to the gate voltage supply line 127, the gate-on voltage is transmitted to the two gate lines 121 connected to the gate voltage supply line 127, and all the thin film transistors Q connected to the two gate lines 121 are turned on. Accordingly, the data voltage transmitted through the data line 171 may be transmitted to each pixel PX through the turned-on thin film transistor Q to charge the liquid crystal capacitor Clc. In this case, the thin film transistors Q of two vertically adjacent pixels PX are simultaneously turned on by receiving the same gate signal from the same gate voltage supply line 127. However, the thin film transistors Q of the two vertically adjacent pixels PX receive different data voltages from different data lines 171, and thus the voltages charged in the capacitors Clc may be different.

The overall configuration of the display device according to the embodiment has been described above. Hereinafter, three adjacent pixels of the display device according to the embodiment will be further described with reference to fig. 3 to 8.

Fig. 3 illustrates a top view of a portion of a display device according to an embodiment. Fig. 4 illustrates a sectional view taken along line IV-IV of fig. 3. Fig. 5 illustrates a sectional view taken along line V-V of fig. 3. Fig. 6 to 8 illustrate sequential top views of a manufacturing sequence of a display device according to an embodiment. Fig. 3 to 8 illustrate three pixels adjacent in the row direction.

As shown in fig. 3 to 8, the display device according to the embodiment includes first and second display panels 100 and 200 facing each other and a liquid crystal layer 3 disposed between the first and second display panels 100 and 200.

First, the first display panel 100 will be described.

A gate conductor including the gate line 121, the gate electrode 124, and the storage electrode line 131 may be disposed on the first substrate 110 made of a transparent insulating material such as glass or plastic. Fig. 6 illustrates a gate conductor. The gate conductor may include a low-resistance metal such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti), or a metal alloy thereof. The gate conductor may be made of a single layer or multiple layers.

The gate line 121 mainly extends in a row direction and transmits a gate signal. Unlike the illustrated embodiment, the gate lines 121 may mainly extend in the column direction. The gate electrode 124 is integrally formed with the gate line 121 and protrudes from the gate line 121. It is to be understood that integrally formed means that they are formed of the same material and connected to each other in the same process. The gate electrode 124 may receive a gate signal from the gate line 121. A pair of gate lines 121 are illustrated extending side by side and a gate electrode 124 is connected to the pair of gate lines 121. However, the gate electrode 124 may be connected to a single gate line 121. In the display device according to the embodiment, since the pair of gate lines 121 is connected to the gate electrode 124, even if one of the pair of gate lines 121 is cut off and shorted during a repair process, a gate signal may be transmitted through the other gate line 121.

The storage electrode line 131 may include a first portion 131a and a second portion 131 b. The first portion 131a of the storage electrode line 131 may be adjacent to the gate line 121, and it may extend in a row direction parallel to the gate line 121 to be connected to the pixel PX adjacent to the first portion 131 a. The first portion 131a of the storage electrode line 131 may have a portion having a wide width in a portion adjacent to the gate electrode 124, and the portion may overlap the drain electrode 175. The second portion 131b of the storage electrode line 131 may protrude from the first portion 131 a. The second portions 131b of the storage electrode lines 131 may mainly extend in a column direction parallel to the data lines 171 to be arranged between adjacent pixels. However, the shape and position of the storage electrode lines 131 may be variously changed. A constant voltage may be applied to the storage electrode lines 131.

The gate conductor may further include an auxiliary electrode 129. The auxiliary electrode 129 may mainly extend in a column direction parallel to the second portion 131b of the storage electrode line 131. The auxiliary electrode 129 may extend in a direction parallel to the data line 171. The auxiliary electrode 129 may be disposed between adjacent pixels. The auxiliary electrode 129 may be disposed between the second portions 131b of the adjacent storage electrode lines 131. Three pixels may be disposed between the adjacent auxiliary electrodes 129.

The gate insulating layer 140 may be disposed on the gate conductor. The gate insulating layer 140 may include, for example, silicon nitride (SiN)_x) And silicon oxide (SiO)_x) The inorganic insulating material of (1).

The semiconductor 154 may be disposed on the gate insulating layer 140. The semiconductor 154 may include semiconductor materials such as amorphous silicon, polysilicon, and metal oxides. The semiconductor 154 may overlap the gate electrode 124.

A data conductor including a data line 171, a source electrode 173, a drain electrode 175, and a gate voltage supply line 127 may be disposed on the semiconductor 154. Fig. 7 illustrates the gate conductor and the data conductor together. The data conductor may include a low resistance metal such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta), or a metal alloy thereof. The data conductor may be made of a single layer or multiple layers.

The data lines 171 mainly extend in the column direction and transmit data voltages. Unlike the illustrated embodiment, the data lines 171 may mainly extend in the row direction. The data lines 171 may cross the gate lines 121.

The source electrodes 173 are integrally formed with the data lines 171 and protrude from the data lines 171. Unlike the illustrated embodiment, a portion of the data line 171 may form the source electrode 173. The source electrode 173 may have a U-shaped bent shape. The drain electrodes 175 are spaced apart from the source electrodes 173 at a predetermined interval. One end of the drain electrode 175 may be surrounded by the source electrode 173. The other end of the drain electrode 175 may have a wide width and may overlap the first portion 131a of the storage electrode line 131. The source electrode 173 and the drain electrode 175 may overlap the gate electrode 124. The source electrode 173 and the drain electrode 175 are spaced apart from each other on the gate electrode 124. The shape of the source electrode 173 and the shape of the drain electrode 175 may be variously changed.

Although not shown, an ohmic contact layer may be further disposed between the semiconductor 154 and the source electrode 173 and between the semiconductor 154 and the drain electrode 175. The ohmic contact layer may be made of a material such as n + hydrogenated amorphous silicon doped with a high concentration silicide or an n-type impurity.

The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor Q together with the semiconductor 154 (for example, see fig. 2). The channel of the thin film transistor Q may be formed on the semiconductor 154 between the source electrode 173 and the drain electrode 175.

The gate voltage supply line 127 may be disposed on the same layer as the data line 171. That is, the gate voltage supply line 127 may be formed of the same material as the data line 171 through the same process. The gate voltage supply line 127 may mainly extend in a column direction parallel to the data line 171. The gate voltage supply line 127 may cross the gate line 121, and may overlap the gate line 121. An opening 183 overlapping the gate voltage supply line 127 and the gate line 121 may be formed in the gate insulating layer 140. The opening 183 of the gate insulating layer 140 may be disposed on the gate line 121 and extend to the gate line 121. The gate voltage supply line 127 may be disposed in the opening 183 of the gate insulating layer 140 and on the gate insulating layer 140. Accordingly, the gate voltage supply line 127 may be connected to the gate line 121 through the opening 183. The gate line 121 receives a gate signal from the gate voltage supply line 127 to apply it to the gate electrode 124 of the thin film transistor Q.

The gate voltage supply line 127 may extend parallel to the auxiliary electrode 129. The gate voltage supply line 127 may overlap the auxiliary electrode 129. An opening 185 overlapping the gate voltage supply line 127 and the auxiliary electrode 129 may be formed in the gate insulating layer 140. The opening 185 of the gate insulating layer 140 may be disposed on the auxiliary electrode 129 and extend to the auxiliary electrode 129. The gate voltage supply line 127 may be disposed in the opening 185 of the gate insulating layer 140 and on the gate insulating layer 140. Accordingly, the gate voltage supply line 127 may be connected to the auxiliary electrode 129 through the opening 185. Since the gate voltage supply line 127 is connected to the auxiliary electrode 129, the resistance of the gate voltage supply line 127 can be reduced.

The gate voltage supply line 127 may be disposed between adjacent pixels. The gate voltage supply line 127 may be disposed between the adjacent data lines 171. Three pixel columns may be disposed between adjacent gate voltage supply lines 127. Six data lines 171 may be disposed between adjacent gate voltage supply lines 127.

The first passivation layer 160a may be disposed on the data conductor. The first passivation layer 160a may include an inorganic insulating material. However, the first passivation layer 160a may include an organic insulating material.

The color filter 230 may be disposed on the first passivation layer 160 a. The color filter 230 may uniquely display one of the primary colors. The primary colors may include three primary colors such as a red color, a green color, and a blue color. For example, the color filters 230 may include a first color filter 230R displaying red, a second color filter 230G displaying green, and a third color filter 230B displaying blue. However, the color displayed by the color filter 230 may have colors other than the three primary colors of red, green, and blue, and may be, for example, cyan, magenta, and yellow. The color filter 230 may display white or a mixture of primary colors.

The second passivation layer 160b may be disposed on the color filter 230. The second passivation layer 160b may include an inorganic insulating material or an organic insulating material. The second passivation layer 160b may prevent the color filter 230 from rising and other layers from being contaminated by organic materials such as a solvent flowing out from the color filter 230.

At least one of the first and second passivation layers 160a and 160b may be omitted. In addition, the color filter 230 may be disposed on the second display panel 200 instead of the first display panel 100.

The shield electrode 195 may be disposed on the second passivation layer 160 b. Fig. 8 illustrates the gate conductor, the data conductor, and the shield electrode 195 together. The shield electrode 195 may be made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

The shield electrode 195 may include a main electrode portion 195a overlapping the pixel electrode 191 and a bridge portion 195b overlapping a region between the adjacent pixel electrodes 191.

The main electrode portion 195a of the shield electrode 195 mainly extends in the column direction along each pixel column. One main electrode portion 195a may overlap three pixel columns. That is, the main electrode portion 195a may be arranged to cover three pixel electrodes 191 adjacent to each other in the row direction and a region between the pixel electrodes 191. In this case, three pixel columns overlapping with one main electrode portion 195a may be disposed between the adjacent gate voltage supply lines 127. The main electrode portion 195a may also overlap the data line 171. One main electrode portion 195a may overlap six data lines 171. That is, the main electrode portion 195a may be disposed to cover six adjacent data lines 171 and a region between the data lines 171. In this case, six data lines 171 overlapping one main electrode portion 195a may be disposed between adjacent gate voltage supply lines 127. The main electrode portion 195a may not overlap the gate voltage supply line 127.

The bridge portion 195b of the shield electrode 195 is disposed between the adjacent main electrode portions 195a, and extends from the main electrode portions 195 a. That is, the bridge portion 195b may connect adjacent main electrode portions 195 a. Therefore, the main electrode portion 195a is completely connected by the bridge portion 195b so that the same voltage can be applied to the main electrode portion 195 a. A constant common voltage may be applied to the shield electrode 195. The bridge portion 195b may overlap the gate voltage supply line 127. The bridge portion 195b may not overlap the pixel electrode 191. The bridge portion 195b may extend substantially in the row direction to cross the gate voltage supply line 127. In this case, the width of the bridge portion 195b may be narrower than the width of the gate voltage supply line 127. The bridge portion 195b may be electrically connected to the main electrode portion 195a and may be formed to have a narrow width in order to minimize an overlapping region with the gate voltage supply line 127. In the display device according to the embodiment, the RC delay of the gate voltage supply line 127 may be prevented by minimizing an overlapping region between the bridge portion 195b of the shield electrode 195 and the gate voltage supply line 127.

Shield electrode 195 can further include an opening 195 c. The opening 195c is a region in which a part of the main electrode portion 195a of the shield electrode 195 is opened. The opening 195c may overlap the thin film transistor Q. That is, the opening 195c may be formed by removing a portion of the shield electrode 195 that overlaps the thin film transistor Q. The opening 195c may overlap most regions of the gate electrode 124, the source electrode 173, and the drain electrode 175. By forming the opening 195c in the shield electrode 195, a region in which the shield electrode 195 overlaps the thin film transistor Q is minimized, thus preventing an electrical effect that may occur between the shield electrode 195 and the thin film transistor Q.

An insulating layer 180 may be disposed on the shield electrode 195. The insulating layer 180 may include an organic insulating material. The insulating layer 180 may also include a photosensitive material such as photoresist.

The insulating layer 180 may include a pixel opening 181 overlapping the drain electrode 175. The pixel opening 181 may be further formed on the first passivation layer 160a, the color filter 230, and the second passivation layer 160b, and the insulating layer 180. The pixel opening 181 may extend to and expose at least a portion of the upper surface of the drain electrode 175.

The pixel electrode 191 may be disposed on the insulating layer 180. The pixel electrode 191 may be made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The pixel electrode 191 may be made of the same material as the shielding electrode 195, or may be made of a different material. The pixel electrode 191 may be disposed on a different layer from the shield electrode 195 and may be formed by a different process.

The pixel electrode 191 may be approximately rectangular as a whole. The pixel electrode 191 may be formed in a rectangular form having two sides parallel to the gate line 121 and two sides parallel to the data line 171. However, the overall shape of the pixel electrode 191 may be substantially rectangular, and the pixel electrode 191 may include a horizontal trunk portion and a vertical trunk portion, and fine branch portions extending from the horizontal trunk portion and the vertical trunk portion. The horizontal stem portion may extend substantially in a horizontal direction to be parallel to the gate line 121, and the vertical stem portion may extend substantially in a vertical direction to be parallel to the data line 171. The pixel electrode 191 may be divided into four sub-regions by a horizontal stem portion and a vertical stem portion. The minute branch portions may obliquely extend from the horizontal trunk portion and the vertical trunk portion, and the extending direction may form an angle of approximately 45 degrees or 135 degrees with the gate line 121 or the horizontal trunk portion. In addition, the pixel electrode 191 may further include an outer trunk portion connecting ends of the minute branch portions.

The pixel electrode 191 may include a protrusion protruding from a side adjacent to the drain electrode 175, and the protrusion may overlap the drain electrode 175. The pixel electrode 191 may overlap the drain electrode 175 and the pixel opening 181. The pixel electrode 191 may be connected to the drain electrode 175 through the pixel opening 181. In a state in which the thin film transistor Q is turned on, the pixel electrode 191 is applied with a data voltage from the data line 171. The opening 195c of the shield electrode 195 may overlap the pixel opening 181. The opening 195c of the shield electrode 195 may be larger than the pixel opening 181. The opening 195c of the shield electrode 195 may have a shape surrounding the pixel opening 181. The shield electrode 195 is disposed on an upper layer of the drain electrode 175 and a lower layer of the pixel electrode 191. In this case, when the shield electrode 195 overlaps a portion where the drain electrode 175 and the pixel electrode 191 are connected, the shield electrode 195 may be shorted to the drain electrode 175 or the pixel electrode 191. In the shield electrode 195 of the display device according to the embodiment, since the opening 195c is formed at a portion overlapping with the pixel opening 181 in which the drain electrode 175 and the pixel electrode 191 are connected to each other, the shield electrode 195 may be prevented from being shorted to an adjacent metal layer.

The pixel electrode 191 may overlap the shield electrode 195. Most of the pixel electrode 191 may overlap the shield electrode 195. Most of the remaining portion of the pixel electrode 191 may overlap the shield electrode 195 except for a portion connected to the drain electrode 175. The pixel electrode 191 may overlap the data line 171. The shield electrode 195 may be disposed between the pixel electrode 191 and the data line 171. The data line 171 may be disposed on a lower layer of the shield electrode 195, and the pixel electrode 191 may be disposed on an upper layer of the shield electrode 195. One pixel electrode 191 may overlap two data lines 171. A left edge portion of the pixel electrode 191 may overlap one data line 171 of the two data lines 171, and a right edge portion of the pixel electrode 191 may overlap the other data line 171 of the two data lines 171.

One pixel electrode 191 may be adjacent to three data lines 171 or four data lines 171. For example, referring to the middle pixel of three pixels illustrated in fig. 3, the pixel electrodes 191 may be adjacent to four data lines 171. Two data lines 171 overlapping the pixel electrodes 191 and two data lines 171 adjacent to the two data lines 171 overlapping the pixel electrodes 191 may be adjacent to the pixel electrodes 191. In this case, the data voltage of the positive polarity may be applied to two data lines 171 of the four data lines 171, and the data voltage of the negative polarity may be applied to the other two data lines 171. Even if the shield electrode 195 is not disposed between the data line 171 and the pixel electrode 191, since the capacitance formed between the data line 171 to which the data voltage of positive polarity is applied and the pixel electrode 191 and the capacitance formed between the data line 171 to which the data voltage of negative polarity is applied and the pixel electrode 191 are similar, the vertical crosstalk may not occur.

For example, referring to the left pixel of the three pixels illustrated in fig. 3, the pixel electrode 191 may be adjacent to the three data lines 171. Two data lines 171 overlapping the pixel electrodes 191 and one data line 171 arranged adjacent to the right side of the corresponding pixel may be adjacent to the pixel electrodes 191. Since the gate voltage supply line 127 is disposed between the corresponding pixel and the data line 171 disposed in the pixel adjacent to the left side of the corresponding pixel, there is almost no electrical influence. In this case, the data voltage of the positive polarity may be applied to two data lines 171 of the three data lines 171, and the data voltage of the negative polarity may be applied to the other data line 171. Alternatively, the data voltage of the negative polarity may be applied to two data lines 171 of the three data lines 171, and the data voltage of the positive polarity may be applied to the other data line 171. Accordingly, when the shield electrode 195 is not disposed between the data line 171 and the pixel electrode 191, vertical crosstalk may occur due to a difference between a capacitance formed between the data line 171 to which the data voltage of the positive polarity is applied and the pixel electrode 191 and a capacitance formed between the data line 171 to which the data voltage of the negative polarity is applied and the pixel electrode 191. In the display device according to the embodiment, since the shield electrode 195 is disposed between the data line 171 and the pixel electrode 191, an electrical influence between the data line 171 and the pixel electrode 191 may be shielded to prevent a vertical crosstalk from occurring.

Referring to the right pixel of the three pixels illustrated in fig. 3, the pixel electrode 191 may be adjacent to the three data lines 171. Two data lines 171 overlapping the pixel electrodes 191 and one data line 171 arranged adjacent to the left side of the corresponding pixel may be adjacent to the pixel electrodes 191. In this case, the polarity of the data voltage applied to two data lines 171 among the three data lines 171 may be different from the polarity of the data voltage applied to the other data line 171. In the display device according to the embodiment, since the shield electrode 195 is disposed between the data line 171 and the pixel electrode 191, an electrical influence between the data line 171 and the pixel electrode 191 may be shielded to prevent a vertical crosstalk from occurring.

The shield electrode 195 is adjacent to the gate voltage supply line 127 and is disposed on an upper layer of the gate voltage supply line 127. The shield electrode 195 overlaps the pixel electrode 191, and is disposed on a lower layer of the pixel electrode 191. Accordingly, the shielding electrode 195 may be disposed between the gate voltage supply line 127 and the pixel electrode 191. When a gate-on voltage is applied to the gate voltage supply line 127, the gate-on voltage is transmitted to the gate line 121 connected to the gate voltage supply line 127, and a data voltage is applied to the pixel electrode 191 of the pixel connected to the corresponding gate line 121. In this case, a parasitic capacitance may be formed between the pixel electrode 191 to which the data voltage is applied and the gate voltage supply line 127 to which the gate-on voltage is applied, and the kickback voltage may increase. In the display device according to the embodiment, since the shield electrode 195 is disposed between the gate voltage supply line 127 and the pixel electrode 191, electric influence between the gate voltage supply line 127 and the pixel electrode 191 may be shielded to prevent the kickback voltage from increasing.

Hereinafter, the second display panel 200 will be described.

The common electrode 270 is disposed on the second substrate 210 made of a transparent insulating material such as glass or plastic. The common electrode 270 may be made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The common electrode 270 may be formed as a single plate over the pixels PX or over substantially the entire second display panel 200. However, a slit or an opening may be formed in the common electrode 270.

A constant common voltage may be applied to the common electrode 270. The same common voltage may be applied to the shield electrode 195 and the common electrode 270.

Although not shown, a light shielding member may be further disposed between the second substrate 210 and the common electrode 270. The light shielding member may overlap edges of the pixel electrode 191, the thin film transistor Q, the gate line 121, the gate voltage supply line 127, and the data line 171. The light shielding member is also called a black matrix, and may be used to prevent light leakage.

Although not illustrated, an overcoat layer may be further disposed between the light shielding member and the common electrode 270. The overcoat layer planarizes the constituent elements disposed under the overcoat layer and suppresses contamination of the liquid crystal layer 3 by the organic material flowing out from the constituent elements disposed under the overcoat layer, thus preventing defects such as afterimages that may occur when the screen is driven.

Alignment films (not shown) may be disposed on the inner surfaces of the first display panel 100 and the second display panel 200, and these may be vertical alignment films.

Polarizers (not shown) may be disposed on outer surfaces of the two display panels 100 and 200, and transmission axes of the two polarizers may be orthogonal, and one transmission axis may be parallel to the gate line 121. However, the polarizer may be disposed only on an outer surface of one of the two display panels 100 and 200.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 310 of the liquid crystal layer 3 are oriented such that their long axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field. Thus, in the absence of an electric field, incident light does not pass through orthogonal polarizers and is blocked.

At least one of the liquid crystal layer 3 and the alignment film may include a photoactive material, more specifically, a reactive wafer.

Although the case in which the liquid crystal molecules 310 are initially vertically aligned is described above, in an embodiment, the liquid crystal molecules 310 may be horizontally aligned, and an alignment film may be formed as a horizontal alignment film. The common electrode 270 may be disposed on the first display panel 100 instead of the second display panel 200. In the above, the case where the common electrode 270 is disposed above the liquid crystal layer 3 has been described, but the common electrode 270 may be disposed below the liquid crystal layer 3.

In the above, the pixels arranged around the portion where the gate voltage supply line 127 and the gate line 121 of the display device according to the embodiment are connected have been described. Hereinafter, a pixel disposed around a portion where the gate voltage supply line 127 and the gate line 121 of the display device according to the embodiment cross but are not connected will be described with reference to fig. 9.

Fig. 9 illustrates a top view of a portion of a display device according to an embodiment.

As shown in fig. 9, the display device according to the embodiment includes gate and data lines 121 and 171 crossing each other, a thin film transistor Q connected thereto, and a pixel electrode 191 connected to the thin film transistor Q. The display device according to the embodiment further includes a gate voltage supply line 127 crossing the gate line 121 and extending in a direction parallel to the data line 171. The display device according to the embodiment further includes a shield electrode 195 overlapping the data line 171 and the pixel electrode 191 and adjacent to the gate voltage supply line 127.

Fig. 9 illustrates a portion in which the gate voltage supply line 127 is not connected to the gate line 121. When a gate-on voltage is applied to the gate line 121, a data voltage may be applied to the pixel electrode 191 of the pixel connected to the corresponding gate line 121, and a gate-off voltage may be applied to the gate voltage supply line 127 not connected to the gate line 121. In this case, a parasitic capacitance may be formed between the pixel electrode 191 to which the data voltage is applied and the gate voltage supply line 127 to which the gate-off voltage is applied, and the kickback voltage may be reduced. In the display device according to the embodiment, since the shield electrode 195 is disposed between the gate voltage supply line 127 and the pixel electrode 191, electric influence between the gate voltage supply line 127 and the pixel electrode 191 may be shielded to prevent a kickback voltage from being reduced.

As described above, the display device according to the embodiment may be formed as a liquid crystal display device. However, the display device according to the embodiment may be formed as an organic light emitting diode display device, an electrophoretic display device, or an electrowetting display device. In addition, the display device according to the embodiment may be formed as a next generation display device such as a micro LED display device, a quantum dot light emitting diode (QLED) display device, or a quantum dot organic light emitting diode (QD-OLED) display device.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 10.

Since many portions of the display device according to the embodiment of fig. 10 are the same as those of the display device according to the embodiment of fig. 1 to 9, repeated descriptions of these portions will be omitted. The present embodiment is different from the previous embodiments in that one gate voltage supply line 127 is connected to one gate line 121, and one data line 171 is arranged between two adjacent pixels PX in a row direction, which will be further described below.

Fig. 10 illustrates a layout of a display device according to an embodiment.

As shown in fig. 10, the display device according to the embodiment includes a first substrate 110, and a gate line 121, a gate voltage supply line 127, a data line 171, and a pixel PX connected to the gate line 121 and the data line 171, which are disposed on the first substrate 110.

In the previous embodiment, one gate voltage supply line 127 is connected to two gate lines 121, and in the present embodiment, one gate voltage supply line 127 is connected to one gate line 121. In the previous embodiment, the same gate signal is applied to two gate lines 121 connected to the same gate voltage supply line 127. In the present embodiment, since each gate line 121 is connected to a different gate voltage supply line 127, different gate signals are respectively applied to the gate lines 121.

In the previous embodiment, two data lines 171 are arranged between two adjacent pixels PX in the row direction, whereas in the present embodiment, one data line 171 is arranged between two adjacent pixels PX in the row direction. In the previous embodiment, the pixels PX included in one pixel column are alternately connected to the two data lines 171. That is, two pixels PX, to which the same gate signal is applied, among the pixels PX included in one pixel column are connected to different data lines 171. In the present embodiment, the pixels PX included in one pixel column are connected to the same data line 171.

However, the connection relationship between the pixels PX and the gate and data lines 121 and 171 may be variously changed. For example, one data line 171 may be disposed between two adjacent pixels PX in the row direction, and the pixels PX included in one pixel column may be alternately connected to the data lines 171 disposed at both sides of the corresponding pixel column.

In the previous embodiment and the present embodiment, since the shield electrode 195 is disposed between the data line 171 and the pixel electrode 191, electrical influence between the data line 171 and the pixel electrode 191 may be prevented. Further, since the shield electrode 195 is disposed between the gate voltage supply line 127 and the pixel electrode 191, electrical influence between the gate voltage supply line 127 and the pixel electrode 191 can be prevented.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 11 to 13.

Since many portions of the display device according to the embodiment of fig. 11 to 13 are the same as those of the display device according to the embodiment of fig. 1 to 9, repeated descriptions of these portions will be omitted. The present embodiment is different from the previous embodiments in that one pixel column is disposed between adjacent gate voltage supply lines 127, which will be described further below.

Fig. 11 illustrates a layout of a display device according to an embodiment. Fig. 12 illustrates a top view of a portion of the display device of fig. 11, in accordance with an embodiment. Fig. 13 illustrates a sectional view taken along line XIII-XIII of fig. 12.

As shown in fig. 11 to 13, the display device according to the embodiment includes a first substrate 110, and a gate line 121, a gate voltage supply line 127, a data line 171, and a pixel PX connected to the gate line 121 and the data line 171, which are disposed on the first substrate 110.

In the previous embodiment, three pixel columns are disposed between the adjacent gate voltage supply lines 127, whereas in the present embodiment, one pixel column is disposed between the adjacent gate voltage supply lines 127. Therefore, in the present embodiment, the gate voltage supply lines 127 are arranged at both sides of each pixel PX. That is, the gate voltage supply line 127 may be disposed at a left side of each pixel PX, and the gate voltage supply line 127 may be disposed at a right side of each pixel PX. The gate voltage supply line 127 may be disposed between two adjacent pixels PX, and the data line 171 may be disposed between the gate voltage supply line 127 and the pixels PX. The gate voltage supply line 127 may be disposed between two adjacent data lines 171. Some of the pixels PX included in one pixel column may be connected to the data line 171 arranged at the left side of the pixel column, and the remaining pixels PX included in the pixels PX in the pixel column may be connected to the data line 171 arranged at the right side of the pixel column. Data voltages of different polarities may be applied to two data lines 171 connected to one pixel column.

In the previous embodiment, each main electrode portion 195a of the shield electrode 195 overlaps three pixel electrodes 191, whereas in the present embodiment, each main electrode portion 195a of the shield electrode 195 overlaps one pixel electrode 191. In the previous embodiment, each main electrode portion 195a of the shield electrode 195 overlaps six data lines 171, whereas in the present embodiment, each main electrode portion 195a of the shield electrode 195 overlaps two data lines 171.

In the present embodiment, the number of gate voltage supply lines 127 may be greater than the number of gate voltage supply lines 127 in the previous embodiment. Some of the gate voltage supply lines 127 may not be connected to the gate line 121.

In the previous embodiment and the present embodiment, since the shield electrode 195 is disposed between the data line 171 and the pixel electrode 191, electrical influence between the data line 171 and the pixel electrode 191 may be prevented. Further, since the shield electrode 195 is disposed between the gate voltage supply line 127 and the pixel electrode 191, electrical influence between the gate voltage supply line 127 and the pixel electrode 191 can be prevented.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 14 and 15.

Since many portions of the display device according to the embodiment of fig. 14 and 15 are the same as those of the display device according to the embodiment of fig. 1 to 9, repeated descriptions of these portions will be omitted. This embodiment is different from the previous embodiments in that the shield electrode overlaps with the gate electrode and the source electrode of the thin film transistor, which will be described further below.

Fig. 14 illustrates a top view of a portion of a display device according to an embodiment. Fig. 15 illustrates a sectional view taken along line XV-XV of fig. 14.

The display device according to the embodiment includes a first substrate 110, and a gate line 121, a gate voltage supply line 127, a data line 171, a thin film transistor Q, a shield electrode 195, and a pixel electrode 191 disposed on the first substrate 110.

The opening 195c may be formed in the shield electrode 195, and the pixel opening 181 may be formed in the insulating layer 180 disposed between the shield electrode 195 and the pixel electrode 191. The opening 195c of the shield electrode 195 may overlap the pixel opening 181. The opening 195c of the shield electrode 195 may be larger than the pixel opening 181. The opening 195c of the shield electrode 195 may have a shape surrounding the pixel opening 181.

In the previous embodiment, the opening 195c of the shield electrode 195 overlaps most of the area of the thin film transistor Q, whereas in the present embodiment, the opening 195c of the shield electrode 195 overlaps only some of the area of the thin film transistor Q. In the present embodiment, the opening 195c of the shield electrode 195 may overlap with a portion in which the drain electrode 175 of the thin film transistor Q and the pixel electrode 191 are connected and a peripheral portion of the portion in which the drain electrode 175 of the thin film transistor Q and the pixel electrode 191 are connected, but not overlap with the remaining portion other than these portions. That is, the shield electrode 195 may overlap the gate electrode 124 and the source electrode 173 of the thin film transistor Q.

In the previous embodiment and the present embodiment, since the shield electrode 195 is disposed between the data line 171 and the pixel electrode 191, electrical influence between the data line 171 and the pixel electrode 191 may be prevented. Further, since the shield electrode 195 is disposed between the gate voltage supply line 127 and the pixel electrode 191, electrical influence between the gate voltage supply line 127 and the pixel electrode 191 can be prevented.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 16.

Since many portions of the display device according to the embodiment of fig. 16 are the same as those of the display device according to the embodiment of fig. 1 to 9, repeated descriptions of these portions will be omitted. The present embodiment differs from the previous embodiments in that the color filters are arranged on the second display panel instead of on the first display panel, which will be described further below.

Fig. 16 illustrates a cross-sectional view of a portion of a display device according to an embodiment.

The display device according to the embodiment includes a first substrate 110, and a gate line 121, a gate voltage supply line 127, a data line 171, a thin film transistor Q, a shield electrode 195, and a pixel electrode 191 disposed on the first substrate 110.

In the previous embodiment, the first passivation layer 160a, the color filter 230, and the second passivation layer 160b are disposed between the data line 171 and the shield electrode 195, whereas in the present embodiment, the first passivation layer 160a and the second passivation layer 160b are disposed between the data line 171 and the shield electrode 195.

In the present embodiment, the second display panel 200 may include a color filter 230 disposed on the second substrate 210. The color filters 230 may include a first color filter 230R, a second color filter 230G, and a third color filter 230B. Although not illustrated, the light blocking member may be disposed at a boundary between the first color filter 230R and the second color filter 230G, at a boundary between the second color filter 230G and the third color filter 230B, and at a boundary between the third color filter 230B and the first color filter 230R. The common electrode 270 may be disposed on the color filter 230. The overcoat layer 240 may be further disposed between the color filter 230 and the common electrode 270.

In the previous embodiment and the present embodiment, since the shield electrode 195 is disposed between the data line 171 and the pixel electrode 191, electrical influence between the data line 171 and the pixel electrode 191 may be prevented. Further, since the shield electrode 195 is disposed between the gate voltage supply line 127 and the pixel electrode 191, electrical influence between the gate voltage supply line 127 and the pixel electrode 191 can be prevented.

While the disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the inventive concept is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

< description of symbols >

Q: the thin film transistor 110: first substrate

121: gate line 124: gate electrode

127: gate voltage supply line 131: storage electrode line

140: the gate insulating layer 154: semiconductor device and method for manufacturing the same

171: data line 173: source electrode

175: drain electrode 195: shielding electrode

195 a: main electrode portion of shield electrode

195 b: bridging part of shielding electrode

195 c: opening of shielding electrode

160 a: first passivation layer 160 b: second passivation layer

180: insulating layer 181: pixel aperture

183. 185 of: opening 191: pixel electrode

210: second substrate 230: color filter

270: common electrode