阅读说明：本技术 存储器器件、存储器集成电路及其制造方法 (Memory device, memory integrated circuit and manufacturing method thereof ) 是由 宋福庭 于 2021-02-08 设计创作，主要内容包括：提供一种存储器器件、一种存储器集成电路及一种存储器器件的制造方法。存储器器件包括复合底部电极、顶部电极及设置在复合底部电极与顶部电极之间的电阻可变层。复合底部电极包括第一底部电极及设置在第一底部电极之上的第二底部电极。第二底部电极的侧壁在侧向上相对于第一底部电极层的侧壁及电阻可变层的侧壁凹陷。(A memory device, a memory integrated circuit and a method of manufacturing a memory device are provided. The memory device includes a composite bottom electrode, a top electrode, and a resistance variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. The sidewalls of the second bottom electrode are recessed in a lateral direction with respect to the sidewalls of the first bottom electrode layer and the sidewalls of the resistance variable layer.)

1. A memory device, comprising:

a composite bottom electrode;

a top electrode; and

a resistance variable layer disposed between the composite bottom electrode and the top electrode,

wherein the composite bottom electrode comprises a first bottom electrode and a second bottom electrode disposed over the first bottom electrode, and sidewalls of the second bottom electrode are laterally recessed relative to sidewalls of the first bottom electrode and sidewalls of the resistance variable layer.

2. The memory device of claim 1, further comprising:

a hard mask disposed over the top electrode.

3. The memory device of claim 1, further comprising:

a passivation layer covering the composite bottom electrode, the resistance variable layer, and the top electrode.

4. The memory device of claim 3, wherein the passivation layer is in physical contact with the sidewall of the second bottom electrode of the composite bottom electrode.

5. The memory device of claim 3, wherein an air gap is located between the sidewall of the second bottom electrode and the passivation layer.

6. The memory device of claim 1, wherein the sidewall of the second bottom electrode has a curved surface, and a most concave portion of the sidewall of the second bottom electrode is located at a bottom surface of the resistance variable layer.

7. The memory device of claim 1, wherein the sidewall of the second bottom electrode has a curved surface, and a most concave portion of the sidewall of the second bottom electrode is located at about half the thickness of the second bottom electrode.

8. A memory integrated circuit, comprising:

a plurality of memory cells arranged in an array, wherein each of the plurality of memory cells comprises a memory device, and the memory device comprises a composite bottom electrode, a top electrode, a resistance variable layer between the composite bottom electrode and the top electrode, and a passivation layer covering the top electrode, the resistance variable layer, and the composite bottom electrode, wherein the composite bottom electrode comprises a first bottom electrode and a second bottom electrode disposed over the first bottom electrode, and a sidewall of the second bottom electrode is recessed laterally with respect to a sidewall of the first bottom electrode and a sidewall of the resistance variable layer;

a plurality of bit lines extending along a first direction; and

a plurality of word lines extending along a second direction crossing the first direction, wherein each of the memory devices is electrically connected between one of the plurality of bit lines and one of the plurality of word lines.

9. A method of manufacturing a memory device, comprising:

sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistance variable material layer, a top electrode layer and a hard mask layer on the device substrate;

patterning the hard mask layer to form a hard mask;

patterning the top electrode layer using the hard mask as a mask, patterning the resistance variable material layer, patterning the second bottom electrode layer, and patterning the first bottom electrode layer; and

recessing the second bottom electrode layer laterally relative to the patterned layer of resistance variable material.

10. The method of manufacturing a memory device according to claim 9, wherein after patterning the resistance variable material layer and before patterning the first bottom electrode layer, one single etching process is performed using the hard mask as the mask to pattern the second bottom electrode layer and recess the second bottom electrode layer in a lateral direction.

11. The manufacturing method of the memory device according to claim 9, wherein a first etching process is performed to pattern the second bottom electrode layer using the hard mask as the mask, and a second etching process is performed to recess the second bottom electrode layer in a lateral direction, and the first etching process and the second etching process are different etching processes.

12. The manufacturing method of the memory device according to claim 11, wherein the second etching process for recessing the second bottom electrode layer in a lateral direction is performed before patterning the first bottom electrode layer.

13. The manufacturing method of the memory device according to claim 11, wherein the second etching process for recessing the second bottom electrode layer in a lateral direction is performed after patterning the first bottom electrode layer.

Technical Field

The present disclosure relates to a memory device, a memory integrated circuit, and a method of manufacturing the same.

Background

Many modern electronic devices contain electronic memory configured to store data. The electronic memory may be a volatile memory or a non-volatile memory. Volatile memories store data when powered, while non-volatile memories can store data even when power is removed. Resistive Random Access Memory (RRAM) is a potential candidate for the next generation of non-volatile memory technology due to its simple structure and its compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) logic circuit fabrication processes.

Disclosure of Invention

In an aspect of the present disclosure, a memory device is provided. The memory device includes a composite bottom electrode, a top electrode, and a resistance variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. Sidewalls of the second bottom electrode are recessed laterally with respect to sidewalls of the first bottom electrode layer and sidewalls of the resistance variable layer.

In another aspect of the present disclosure, a memory integrated circuit is provided. The memory integrated circuit comprises a plurality of memory cells, a plurality of bit lines and a plurality of word lines. The plurality of memory cells are arranged in an array. Each of the plurality of memory cells comprises a memory device, and the memory device comprises a composite bottom electrode, a top electrode, a resistance variable layer between the composite bottom electrode and the top electrode, and a passivation layer covering the top electrode, the resistance variable layer, and the composite bottom electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. Sidewalls of the second bottom electrode are recessed laterally with respect to sidewalls of the first bottom electrode and sidewalls of the resistance variable layer. The plurality of bit lines extend along a first direction. The plurality of word lines extend along a second direction crossing the first direction. Each of the memory devices is electrically connected between one of the plurality of bit lines and one of the plurality of word lines.

In yet another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method comprises the following steps: sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistance variable material layer, a top electrode layer and a hard mask layer on the device substrate; patterning the hard mask layer to form a hard mask; patterning the top electrode layer using the hard mask as a mask, patterning the resistance variable material layer, patterning the second bottom electrode layer, and patterning the first bottom electrode layer; and recessing the second bottom electrode layer laterally with respect to the patterned resistance variable material layer.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a flow chart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure.

Fig. 2A through 2I are schematic cross-sectional views of structures at various stages during a method of manufacturing the memory device shown in fig. 1.

Fig. 3A is an equivalent circuit diagram illustrating a memory integrated circuit according to some embodiments of the present disclosure.

FIG. 3B is a schematic diagram illustrating one of the memory cells shown in FIG. 3A.

Fig. 4A-4C are schematic cross-sectional views of structures at various stages during methods of fabrication of memory devices according to some embodiments of the present disclosure.

Fig. 5A and 5B are schematic cross-sectional views of the structure at various stages during the method of manufacturing the memory cell shown in fig. 4C.

Fig. 6A and 6B are schematic cross-sectional views illustrating memory devices according to some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "below …", "below …", "lower", "above …", "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be appreciated that the following embodiments of the present disclosure provide applicable concepts that can be embodied in a wide variety of specific contexts. The examples are intended to provide further explanation and are not intended to limit the scope of the present disclosure.

Fig. 1 is a flow chart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure. Fig. 2A through 2I are schematic cross-sectional views of structures at various stages during a method of manufacturing the memory device shown in fig. 1. In some embodiments, a method of manufacturing a memory device includes the following steps.

Referring to fig. 1 and 2A, step S100 is performed, and a device substrate 100 is provided. In some embodiments, the device substrate 100 is a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer, and the device substrate 100 is pre-formed with a plurality of electronic devices (not shown) and interconnect structures (partially shown in fig. 2A) located over the electronic devices. It should be noted that only the top portion of the interconnect structure including the conductive trace 102 is illustrated in fig. 2A, and other portions of the interconnect structure and electronic devices are omitted for simplicity. The electronic devices may include active devices and/or passive devices. For example, the active devices may include field effect transistors, diodes, similar devices, or combinations thereof, while the passive devices may include resistors, capacitors, similar devices, or combinations thereof. In addition, the interconnect structure may include a combination of conductive traces and vias. The electronic devices and interconnect structures formed in the device substrate 100, together with the structures to be formed over the device substrate 100 in the following steps, constitute an integrated circuit, such as a memory integrated circuit. In some embodiments, the memory integrated circuit is a Resistive Random Access Memory (RRAM) integrated circuit. As shown in fig. 2A, the top portion of the interconnect structure includes conductive traces 102, the conductive traces 102 being laterally spaced apart from one another. The material of the conductive trace 102 may include Al, Cu, Ti, TiN, Ta, TaN, W, similar materials, or combinations thereof. Additionally, the conductive traces 102 may be formed in the dielectric layer 104. The material of the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material (e.g., a dielectric material having a dielectric constant of about 1.5 or less than 1.5), the like, or combinations thereof. In some embodiments, the top surfaces of the conductive traces 102 are substantially coplanar with the top surface of the dielectric layer 104. In addition, a passivation pattern 106 may be disposed over the conductive traces 102 and the dielectric layer 104. The passivation pattern 106 has openings 106a that respectively expose a portion of the underlying conductive traces 102. Memory units MU (as shown in fig. 2G) to be formed in the following steps may extend into these openings 106a to be electrically connected with the conductive traces 102. The material of the passivation layer pattern 106 may include silicon carbide, silicon oxynitride, silicon oxycarbide, silicon nitride, similar materials, or a combination thereof.

Referring to fig. 1 and 2B, step S102 is performed, and a stack of a bottom electrode layer 108 and a bottom electrode layer 110, a resistance variable material layer 112, and a top electrode layer 114 is sequentially formed over the device substrate 100. In some embodiments, the bottom electrode layers 108 and 110, the resistance variable material layer 112, and the top electrode layer 114 are conformally formed over the device substrate 100. As such, at least the bottom electrode layer 108 and the bottom electrode layer 110 extend into the opening 106a (as shown in fig. 2A), and the top surfaces of the bottom electrode layer 108 and the bottom electrode layer 110, the top surface of the resistance variable layer 112, and the top surface of the top electrode layer 114 may be recessed at locations corresponding to the opening 106 a. Additionally, in some embodiments, the bottom electrode layer 110 is opposite to the resistance variable materialThe material layer 112 and the top electrode layer 114 have sufficient etch selectivity, and the patterning of the bottom electrode layer 110 and the patterning of the resistance variable material layer 112 and the top electrode layer 114 (as shown in fig. 2E and 2F) may be performed in different steps by selecting appropriate etchants. Similarly, the bottom electrode layer 110 may also have sufficient etch selectivity with respect to the bottom electrode layer 108, and the bottom electrode layer 108 and the bottom electrode layer 110 may be patterned in different etching steps by selecting appropriate etchants (as shown in fig. 2F and 2G). For example, the material of the bottom electrode layer 108 may include titanium nitride, tantalum nitride, tungsten, titanium, tantalum, similar materials, or combinations thereof. On the other hand, the material of the bottom electrode layer 110 may include ruthenium, iridium, platinum, or a combination thereof. In addition, the material of the resistance variable material layer 112 may include tantalum oxide, hafnium oxide, tantalum aluminum oxide (TaAlO), similar materials, or a combination thereof, and the material of the top electrode layer 114 may include titanium nitride, tantalum nitride, tungsten, titanium, tantalum, similar materials, or a combination thereof. Further, the thickness of the bottom electrode layer 108 may be atToWithin the range. The thickness of the bottom electrode layer 110 may be atToWithin the range. The thickness of the resistance variable material layer 112 may be inToWithin the range. The thickness of the top electrode layer 114 may be atToWithin the range. In addition, the formation methods of the bottom electrode layers 108 and 110 and the formation method of the top electrode layer 114 may respectively include a deposition process, such as an Atomic Layer Deposition (ALD) process. In addition, the formation method of the resistance variable material layer 112 may include a Chemical Vapor Deposition (CVD) process.

Referring to fig. 1 and 2C, step S104 is performed, and a hard mask layer 116 and a photoresist pattern 118 are sequentially formed on the top electrode layer 114. In some embodiments, the hard mask layer 116 is formed globally over the structure shown in figure 2B. The hard mask layer 116 may protect underlying layers (e.g., the top electrode layer 114) from damage during the following patterning process (as shown in figure 2D). In some embodiments, the hard mask layer 116 is formed with a thickness large enough so that the hard mask layer 116 may have a substantially flat top surface. In alternative embodiments, a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process, an etching process, a grinding process, or a combination thereof) may be performed on the initially formed hard mask layer to form the hard mask layer 116 having a substantially planar top surface. Furthermore, in some embodiments, the bottom portion of the hard mask layer 116 may protrude down into a recess of the top surface of the top electrode layer 114. The material of the hard mask layer 116 may include silicon carbide, silicon oxynitride, silicon oxycarbide, silicon nitride, similar materials, or combinations thereof, and the thickness of the hard mask layer 116 may be atToWithin the range. In addition, the hard mask layer 116 may be formed by a CVD process or a solution process (e.g., a spin-on process). On the other hand, the photoresist pattern 118 defines the position, size, and shape of a hard mask 120 (as shown in fig. 2D) to be formed in the following steps. The photoresist pattern 118 may be made of a photosensitive materialIs made of, and can have atToA thickness within the range. In addition, the formation method of the photoresist pattern 118 may include a solution process (e.g., a spin coating process) and a photolithography process.

As will be described with reference to fig. 2D through 2G, in some embodiments, the hard mask layer 116, the top electrode layer 114, the resistance variable material layer 112, and the bottom electrode layer 110 and the bottom electrode layer 108 are patterned by a plurality of steps.

Referring to fig. 1 and 2D, step S106 is performed, and the hard mask layer 116 is patterned by using the photoresist pattern 118 as a mask to form a hard mask 120. The hard mask 120 stands on the top electrode layer 114 and may also be used as a mask to pattern the underlying top electrode layer 114, resistance variable material layer 112, and bottom electrode layer 110 and 108 in the following steps, as shown in fig. 2E-2G. In some embodiments, the patterning process used to form the hard mask 120 comprises an anisotropic etch process. In these embodiments, the width of the hard mask 120 may gradually increase toward the underlying top electrode layer 114. In addition, the hard mask 120 may have sufficient etch selectivity relative to the underlying top electrode layer 114, and the top electrode layer 114 may serve as an etch stop layer during formation of the hard mask 120. With respect to the top view of the hard mask, as depicted in the area surrounded by the dashed lines in fig. 2D, the top view shape of the hard mask 120 is substantially rectangular or elliptical, and the hard mask 120 is arranged in an array. However, the top view shape and arrangement of the hard mask 120 may be modified by those skilled in the art according to design requirements, and the present disclosure is not limited thereto. In some embodiments, after the hard mask 120 is formed, the photoresist pattern 108 is removed through, for example, an ashing process or a stripping process.

Referring to fig. 1 and 2E, step S108 is performed, and the top electrode layer 114 and the resistance variable material layer 112 are patterned to form a top electrode 122 and a resistance variable layer 124.In some embodiments, the patterning process used to form the top electrode 122 and the resistance variable layer 124 uses the overlying hard mask 120 as a mask rather than using a photoresist pattern defined by a photolithography process. In these embodiments, such a patterning process may be considered a self-aligned patterning process. The resulting stack, comprising the hard mask 120 and the underlying one of the top electrode 122 and the resistance variable layer 124, respectively, stands on the bottom electrode layer 110, and may also be used as a mask for patterning the bottom electrode layer 110 and the bottom electrode layer 108 in the following steps, as shown in fig. 2F and 2G. In some embodiments, the patterning process used to form the top electrode 122 and the resistance variable layer 124 includes an anisotropic etching process. In these embodiments, the width of the stack may gradually increase toward the underlying bottom electrode layer 110. In addition, the bottom electrode layer 110 may have sufficient etch selectivity with respect to the resistance variable layer 124 and the top electrode 122, and the bottom electrode layer 110 may serve as an etch stop layer when forming the top electrode 122 and the resistance variable layer 124. In some embodiments, the hard mask 120 may be thinned during the formation of the top electrode 122 and the resistance variable layer 124. For example, the thinned hard mask 120 has a first portion atToA thickness within the range.

Referring to fig. 1 and 2F, step S110 is performed, and the bottom electrode layer 110 is patterned to form a bottom electrode 126. Each of the bottom electrodes 126 is located between one of the bottom electrode layers 108 and the overlying resistance variable layer 124, and the sidewalls 126S of the bottom electrodes 126 are recessed and recessed (cove) laterally from the sidewalls 124S of the resistance variable layer 124. In some embodiments, the patterning of the bottom electrode layer 110 to form the bottom electrode 126 is performed using an isotropic etching process. In those embodiments where the bottom electrode layer 108 has sufficient etch selectivity relative to the bottom electrode 126 (or the bottom electrode layer 110 as shown in FIG. 2E), the bottom electrode layer 108 may be in the isotropic stateWhich acts as an etch stop layer during the sexual etch process. In addition, the stack, which includes the hard mask 120 and one of the underlying top electrode 122 and resistance variable layer 124, respectively, is used as a mask during the isotropic etch process so that portions of the bottom electrode layer 110 not covered by the stack are removed. In addition, during the isotropic etching process, the portion of the bottom electrode layer 110 covered by the above-described stack is further etched along the lateral direction, so that the formed bottom electrode 126 is recessed in the lateral direction and becomes smaller in size compared to the pattern of the overlying stack. As shown in the enlarged view illustrating one of the sidewalls 126S of the bottom electrode 126 and the overlying sidewalls 124S of the resistance variable layer 124 (i.e., the region surrounded by the dashed line in fig. 2F), the sidewalls 126S are recessed from the sidewalls 124S (from the sidewalls of the overlying stack), and the sidewalls 126S have curved surfaces. From an enlarged view, the most concave portion (most recessed portion) of the concave sidewall 126S of the bottom electrode 126 is close to the bottom surface of the resistance variable layer 124 because a portion (i.e., an upper portion) of the bottom electrode layer 110 closer to the bottom surface of the resistance variable layer 124 may be exposed to an etchant for a longer time than a portion (i.e., a lower portion) of the bottom electrode layer 110 farther from the bottom surface of the resistance variable layer 124 during the isotropic etching process. Since the bottom electrode 126 has its most recessed portion (i.e., the portion that is etched the most in the lateral direction) near the resistance variable layer 124, it is ensured that possible leakage paths along the sidewalls of the top electrode 122 and the resistance variable layer 124 do not extend to the sidewalls of the bottom electrode 126. In some embodiments, where the recess depth RD of the bottom electrode 126 is measured laterally from an extension line (dotted line) along the sidewalls of the overlying stack to the curved surface of the sidewall 126S, the recess depth RD may taper from the top surface of the bottom electrode 126 to the bottom surface of the bottom electrode 126. Alternatively, the sidewall 126S of the bottom electrode 126 may be a sloped sidewall. The sidewalls 126S of the bottom electrode 126 may be adjusted by tuning process parameters of the isotropic etching process, and the disclosure is not limited thereto. In some embodiments, the recess depth RD of the bottom electrode 126 may be atToIn the range, and the thickness T of the bottom electrode 126₁₂₆Can be atToWithin the range. In such embodiments where the depression depth RD decreases downward, the maximum value of the depression depth RD may beToWithin a range, and the minimum value of the depression depth RD may beToWithin the range. In addition, in some embodiments, the etchant of the isotropic etch process used to form the bottom electrode 126 is different from the etchant of the anisotropic etch process used to form the hard mask 120, the top electrode 122, and the resistance variable layer 124 (as described with reference to fig. 2D and 2E). For example, when the material of the bottom electrode 126 comprises ruthenium, the etchant of the isotropic etching process may comprise oxygen. On the other hand, the etchant for the anisotropic etching process for forming the hard mask 120 may include fluorine, fluorocarbon (e.g., CH)₂F₂、CF₄、CHF₃Etc.), carbon sulfur compounds (e.g., SF₆Etc.), similar etchant, or a combination thereof, and the etchant for the anisotropic etching process for forming the hard mask 120, the top electrode 122, and the resistance variable layer 124 may include a chlorine compound or a bromine compound (e.g., Cl)₂、HBr、BCl₃Etc.).

Referring to fig. 1 and 2G, step S112 is performed, and the bottom electrode layer 108 is patterned to form the bottom electrode 128. Each bottom electrode 128 and the overlying bottom electrode 126 may be collectively considered a composite bottom electrode 130. The composite bottom electrode 130 is electrically connected to an electronic device (not shown) through an interconnect structure (e.g., including conductive trace 102) formed in the device substrate 100. In some embodiments, the patterning process used to form the bottom electrode 128 includes an anisotropic etch process that uses the overlying stack as a mask. In these embodiments, the patterning process for forming the bottom electrode 128 may be considered a self-aligned process. In addition, the stack used as a mask may include a resistance variable layer 124, a top electrode 122, and a hard mask 120, respectively. The sidewalls 128S of each bottom electrode 128 may extend along the extending direction of the sidewalls of the overlying one of the stacks. Since the sidewalls 126S of the bottom electrode 126 are recessed laterally from the sidewalls of these overlying stacks, the sidewalls 126S of the bottom electrode 126 may now be recessed and recessed laterally from the sidewalls 128S of the underlying bottom electrode 128 that was patterned using these stacks as masks. In addition, as shown in the enlarged view illustrating the top view of one of the bottom electrodes 126 and the underlying bottom electrode 128 (i.e., the region surrounded by the dashed line in fig. 2G), in such embodiments where the recess depth of the bottom electrode 126 decreases downward, the area of the top surface of each bottom electrode 126 may be less than the area of the underlying bottom electrode 128, while the area of the bottom surface of each bottom electrode 126 may be close to or substantially the same as the area of the underlying bottom electrode 128. In some embodiments, the etchant for the anisotropic etch process used to form the bottom electrode 128 is different from the etchant for the isotropic etch process used to form the bottom electrode 126 (as described with reference to fig. 2F). For example, the etchant used for the anisotropic etch to form the bottom electrode 128 may include a halogen chemistry (e.g., CF)₄、Cl₂、BCl₃HBr, etc.), while the etchant used to form the isotropic etch of the bottom electrode 126 may include oxygen when the material of the bottom electrode 126 includes ruthenium. In some embodiments, the portions of the passivation pattern 106 not covered by the stack are thinned,while the thickness of other portions of the passivation pattern 106 underlying the stacks may remain unchanged. In these embodiments, the step height H between different portions of the passivation pattern 106₁₀₆Can be atToWithin the range. Furthermore, in some embodiments, the hard mask 120 is also thinned during the formation of the bottom electrode 128. One skilled in the art can adjust the amount of thickness reduction of the hard mask 120 by tuning the process parameters of the anisotropic etch process as long as the thinned hard mask 120 still covers the underlying top electrode 122. The present disclosure is not limited to only the thickness reduction of the hard mask 120.

To this end, a plurality of memory units MU are formed over the device substrate 100. Each memory cell MU includes a top electrode 122, a composite bottom electrode 130, and a resistance variable layer 124 between the top electrode 122 and the composite bottom electrode 130. In addition, each memory unit MU may also include a hard mask 120 disposed over the top electrode 122. In some embodiments, the memory units MU are disposed over the passivation pattern 106 and may be considered to penetrate through the passivation pattern 106 and to be in electrical contact with the conductive traces 102.

Referring to fig. 1 and 2H, step S114 is performed, and a passivation layer 132, and a dielectric layer 134 and a dielectric layer 136 are sequentially formed on the device substrate 100 and the memory unit MU. In some embodiments, the passivation layer 132 is conformally formed over the device substrate 100 and the memory units MU. As such, the exposed surface of the passivation pattern 106 and the exposed surface of the memory unit MU are currently covered by the passivation layer 132. In some embodiments, the passivation layer 132 is not in physical contact with the bottom electrode 126. In these embodiments, air gaps AG may be formed between each bottom electrode 126 and the passivation layer 132. Air gaps AG may surround the bottom electrodes 126, respectively. A dielectric layer 134 is formed over the passivation layer 132. In some embodiments, the recesses respectively defined between the adjacent memory units MU are filled with the dielectric layer 134, and the portions of the passivation layer 132 above the memory units MU may be covered by the dielectric layer 134. Additionally, in some embodiments, a planarization process may be performed on the dielectric layer 134 such that the dielectric layer 134 may have a substantially planar top surface. A dielectric layer 136 is formed over the dielectric layer 134, and the dielectric layer 136 may also have a substantially planar top surface. The passivation layer 132 may comprise silicon carbide, silicon oxynitride, silicon oxycarbide, silicon nitride, the like, or combinations thereof, and the dielectric layers 134 and 136 may comprise silicon oxide, low-k dielectric materials (e.g., dielectric materials having a dielectric constant of about 1.5 or less than 1.5), the like, or combinations thereof. In addition, the method for forming the passivation layer 132 may include a CVD process, and the method for forming the dielectric layers 134 and 136 may include a CVD process or a solution process (e.g., a spin-on process).

Referring to fig. 1 and fig. 2I, step S116 is performed, and the via hole 138 and the conductive trace 140 are formed. The via 138 penetrates through the dielectric layer 134, the passivation layer 132 and the hard mask 120 to electrically connect with the top electrode 122. In some embodiments, the bottom surface of the via 138 may protrude down into a recess at the top surface of the top electrode 122. Conductive traces 140 are formed in the dielectric layer 136, and the conductive traces 140 are respectively in electrical contact with the underlying vias 138. In some embodiments, conductive trace 140 is used as a bit line in the memory integrated circuit exemplarily shown in fig. 3A. In some embodiments, the material of the vias 138 and conductive traces 140 may include copper, aluminum-copper alloy, similar materials, or combinations thereof. Additionally, in some embodiments, the vias 138 and conductive traces 140 may be formed by a dual damascene process. In these embodiments, vias and trenches are formed in dielectric layers 134 and 136 by various photolithography and etching processes, and then conductive material is formed in these vias and trenches by a deposition process (e.g., a PVD process), a plating process (e.g., an electroplating or electroless plating process), or a combination thereof to form vias 138 and conductive traces 140.

To this end, a plurality of memory devices 10 are formed. Each memory device 10 includes one of the storage units MU, and may also include a via 138 electrically connected to such storage unit MU, and conductive traces 102 and 140. During a set operation (or referred to as a forming process), a conductive filament (not shown) is formed through the resistance variable layer 124, leaving the resistance variable layer 124 in a low resistance state (or referred to as an on state). On the other hand, during the reset operation, the conductive filament is cut or the conductive filament is not present in the resistance variable layer 124, so that the resistance variable layer 124 is in a high resistance state (or referred to as an off state). In some embodiments, conductive traces 102 and 140 are configured to receive a voltage and provide a bias across the bottom and top ends of resistance variable layer 124 to perform the set and reset operations described above.

As described above, the memory device 10 includes the memory unit MU including the composite bottom electrode 130, the top electrode 122, and the resistance variable layer 124 interposed between the composite bottom electrode 130 and the top electrode 122. The composite bottom electrode 130 includes a bottom electrode 128 and a bottom electrode 126 disposed above the bottom electrode 128. The sidewalls 126S of the bottom electrode 126 are recessed and recessed in the lateral direction from the sidewalls of the other portions of the memory unit MU. Thus, the isolation distance from the top electrode 122 to the composite bottom electrode 130 along the sidewalls of the memory cells MU increases. In addition, during recessing of the bottom electrode 126 in the lateral direction, conductive material that may remain between the top electrode 122 and the composite bottom electrode 130 may be removed. Thus, the isolation between the top electrode 122 and the composite bottom electrode 130 is improved. The composite bottom electrode 130 may have a smaller footprint than if a spacer surrounding the top electrode 122 were provided (the pattern of the composite bottom electrode 130 would be defined by the outer contour of the surrounding spacer), since the composite bottom electrode 130 according to embodiments of the present disclosure is patterned using a smaller mask without the surrounding spacer. In this way, the isolation between the top electrode 122 and the composite bottom electrode 130 can be ensured without reducing the interval between the laterally adjacent memory units MU (i.e., the interval between the laterally adjacent composite bottom electrodes 130), and therefore the isolation between the laterally adjacent memory units MU can also be improved. Furthermore, by omitting the formation of the above-described spacers, at least one deposition step and at least one etching step may be saved. Therefore, the manufacturing cost is reduced.

Fig. 3A is an equivalent circuit diagram illustrating a memory integrated circuit according to some embodiments of the present disclosure.

Referring to fig. 3A, in some embodiments, each resistive memory RM constitutes a memory cell MC in common with a transistor T connected in series to the resistive memory RM. The plurality of memory cells MC may be arranged in an array and constitute a memory integrated circuit 20, such as an RRAM integrated circuit. The resistive memory RM shown in fig. 3A may be implemented by the memory device 10 shown in fig. 2I, and the memory unit MU of the memory device 10 shown in fig. 2I is depicted as a variable resistor in fig. 3A. The transistors T may be some of the electronic devices formed in the device substrate 100 shown in fig. 2A to 2I. A gate terminal of each transistor T is electrically connected to a word line WL, for example, extending in the direction X, and a source terminal and a drain terminal of each transistor T are electrically connected to a memory cell MU, for example, one of a source line SL and a resistive memory RM, extending in the direction X, respectively. A row of transistors T may share one of the word lines WL and one of the source lines SL. In addition, the electrical connection between the drain terminal and the memory unit MU may be achieved by interconnect structures formed in the device substrate 100 shown in fig. 2A-2I, and such interconnect structures may include the conductive traces 102. Furthermore, the memory units MU are also electrically connected to bit lines BL extending, for example, in the direction Y, such that each memory unit MU is electrically connected between one of the transistors T and one of the bit lines BL. A column of memory units MU may share one of the bit lines BL. In some embodiments, the bit line BL may be implemented as the conductive trace 140 shown in fig. 2I.

As described above, since each transistor T is electrically connected to one of the resistive memories RM. The memory integrated circuit 20 thus has a "1T 1R" configuration. However, the memory integrated circuit of the present disclosure may be formed in other configurations, including a "1 TNR" configuration (i.e., each transistor T is electrically connected to a plurality of resistive memories RM), an "intersection" configuration (i.e., no transistor is present in each memory cell), and the like. Those skilled in the art can modify the configuration of the memory integrated circuit according to design requirements, and the present disclosure is not limited thereto.

Fig. 3B is a schematic diagram illustrating one of the memory cells MC shown in fig. 3A. As shown in fig. 3B, each memory cell MC includes one of the transistors T and one of the resistive memories RM. The transistor T is formed in the device substrate 100, and the resistive memory RM is formed over the device substrate 100. The device substrate 100 may include a semiconductor substrate W. The gate terminal G of the transistor T is formed over a semiconductor substrate W. In some embodiments, the source terminal S and the drain terminal D of the transistor T are embedded in the semiconductor substrate W. On the other hand, the interconnect structure of the device substrate 100 is formed over a semiconductor substrate W, and may include a contact plug CP standing on a source terminal S and a drain terminal D, and includes a plurality of metallization layers. The metallization layer may include conductive trace M1, conductive trace M2, conductive trace M3, and conductive trace M4, and include via V1 and via V2. The conductive trace M1, the conductive trace M2, the conductive trace M3, and the conductive trace M4 extend in a direction substantially parallel to the top surface of the semiconductor substrate W, and are stacked over the semiconductor substrate W in numerical order. Each of the via V1 and the via V2 is electrically connected between vertically adjacent conductive traces (e.g., conductive trace M1 and conductive trace M2). In some embodiments, the resistive memory RM is electrically connected between conductive trace M3 and conductive trace M4. In these embodiments, conductive trace M4 may serve as the bit line BL, as shown in fig. 3A. In addition, conductive trace M3 and conductive trace M4 may be implemented as conductive trace 102 and conductive trace 140, respectively, shown in fig. 2I, and via 138 shown in fig. 2I is omitted in fig. 3B.

Fig. 4A-4C are schematic cross-sectional views of structures at various stages during methods of fabrication of memory devices according to some embodiments of the present disclosure. The embodiment to be described with reference to fig. 4A to 4C is similar to the embodiment detailed with reference to fig. 1 and 2A to 2I. Only the differences between the two will be explained and the same or similar parts will not be described again.

Referring to fig. 1, 2D and 4A, after performing steps S100, S102, S104 and S106, the top electrode layer 114, the resistance variable material layer 112 and the bottom electrode layer 110 shown in fig. 2D are patterned to form a top electrode 122, a resistance variable layer 124 and an initial bottom electrode 126'. In some embodiments, the patterning process used to form the top electrode 122, the resistance variable layer 124, and the initial bottom electrode 126' includes an anisotropic etching process. The hard mask 120 may be used as a mask during this anisotropic etching process. As such, portions of the top electrode layer 114, the resistance variable material layer 112, and the bottom electrode layer 110 not covered by the hard mask 120 may be removed, while portions of these layers covered by the hard mask 120 may remain. In some embodiments, the underlying bottom electrode layer 108 may serve as an etch stop layer during this anisotropic etch process, and may be exposed when this anisotropic etch process is complete. Since an anisotropic etching process is used to form the top electrode 122, the resistance variable layer 124, and the initial bottom electrode 126', the sidewalls of these layers may not be recessed or protruded from each other. In some embodiments, the sidewalls of the top electrode 122, the resistance variable layer 124, and the initial bottom electrode 126' are substantially coplanar with one another. The etchant used in this anisotropic etching process may be capable of removing the material of the top electrode layer 114, the material of the resistance variable material layer 112, and the material of the bottom electrode layer 110. For example, the etchant used in the anisotropic etching process may include an argon-based etchant, an oxygen-based etchant, and a fluorine-chlorine mixture-based etchant.

Referring to fig. 4A and 4B, the sidewalls of the initial bottom electrode 126' are recessed and recessed laterally relative to the sidewalls of the overlying layers to form a bottom electrode 126 a. In some embodiments, the bottom electrode 126a is formed using an isotropic etching process, while the peripheral region of the initial bottom electrode 126' is removed. The recess depth RD of the sidewall 126aS of the bottom electrode 126a can be controlled by adjusting the process time of the isotropic etching process. aS shown in the enlarged view illustrating the sidewall 126aS of one of the bottom electrodes 126a (i.e., the region surrounded by the dashed line in fig. 4B), the recess depth RD of the recessed sidewall 126aS of each bottom electrode 126a may not be greatest at the topmost portion of the bottom electrode 126a (aS described with reference to fig. 2F) because substantially the entire sidewall of the bottom electrode 126aAnd is exposed to the etchant. In some embodiments, the recess depth RD may be greatest at about half the thickness of the bottom electrode 126a and smallest near the top and bottom surfaces of the bottom electrode 126 a. In other words, the most concave portion of the sidewall 126aS of each bottom electrode 126a may be located at about half the thickness of the bottom electrode 126 a. For example, the sidewall 126aS of the bottom electrode 126a may present a substantially parabolic concave surface. Additionally, this parabolic concave surface may be symmetrical about a substantially horizontal axis. In some embodiments, the maximum value of the depression depth RD may be atToWithin a range, and the minimum value of the depression depth RD may beToWithin the range.

Subsequently, referring to fig. 1 and 4C, step S112, step S114, and step S116 are performed, and the memory device 10a is formed. The memory device 10a shown in fig. 4C is similar to the memory device 10 shown in fig. 2I, but the shape of the sidewall 126aS of each bottom electrode 126a shown in fig. 4C is different from the shape of the sidewall 126S of each bottom electrode 126 shown in fig. 2I. In some embodiments, the passivation layer 132 is not in physical contact with the bottom electrode 126a, and an air gap AG' is formed between the passivation layer 132 and the bottom electrode 126 a. aS such, the inner contour of each air gap AG' is defined by the sidewalls 126aS of the corresponding bottom electrode 126a, which sidewalls 126aS are recessed the most at about half the thickness of the bottom electrode 126 a.

Fig. 5A and 5B are schematic cross-sectional views of the structure at various stages during the method of manufacturing the memory cell shown in fig. 4C. The embodiment to be described with reference to fig. 5A and 5B is similar to the embodiment detailed with reference to fig. 4A to 4C. Only the differences between the two will be explained and the same or similar parts will not be described again.

Referring to fig. 1 and 5A, after performing steps S100, S102, S104 and S106, the top electrode layer 114, the resistance variable material layer 112, the bottom electrode layer 110 and the bottom electrode layer 108 are patterned to form a top electrode 122, a resistance variable layer 124, an initial bottom electrode 126' and a bottom electrode 128. In some embodiments, the patterning process used to form the top electrode 122, the resistance variable layer 124, the initial bottom electrode 126', and the bottom electrode 128 includes an anisotropic etching process. The hard mask 120 may be used as a mask during this anisotropic etching process. As such, portions of the top electrode layer 114, the resistance variable material layer 112, the bottom electrode layer 110, and the bottom electrode layer 108 not covered by the hard mask 120 may be removed, while portions of these layers covered by the hard mask 120 may remain. In some embodiments, this anisotropic etch process stops at the passivation pattern 106. In some embodiments, portions of the passivation pattern 106 not covered by the hard mask 120 are thinned, and the thickness of other portions of the passivation pattern 106 under the hard mask 120 may remain unchanged. Since the top electrode 122, the resistance variable layer 124, the initial bottom electrode 126', and the bottom electrode 128 are formed using an anisotropic etching process, sidewalls of these layers may not be recessed or protruded from each other. In some embodiments, the sidewalls of the top electrode 122, the resistance variable layer 124, the initial bottom electrode 126', and the bottom electrode 128 are substantially coplanar with one another. The etchant used in this anisotropic etching process may be capable of removing the material of the top electrode layer 114, the material of the resistance variable material layer 112, the material of the bottom electrode layer 110, and the material of the bottom electrode layer 108. For example, the etchant used in the anisotropic etching process may include an argon-based etchant, an oxygen-based etchant, and a mixture-based etchant of fluorine and chlorine.

Referring to fig. 5A and 5B, the sidewalls of the initial bottom electrode 126' are recessed and recessed laterally relative to the sidewalls of the overlying layer and the underlying layer to form a bottom electrode 126 a. The method for forming the bottom electrode 126a shown in FIG. 5B is similar to the method for forming the bottom electrode 126a shown in FIG. 4B, but the bottom electrode 126a shown in FIG. 5B is formed after the underlying bottom electrode 128 is formed. Thus, the sidewall 126aS of the bottom electrode 126a shown in fig. 5B is similar to the sidewall 126aS of the bottom electrode 126a shown in fig. 4B in that it is recessed most at about half the thickness of the bottom electrode 126 a.

Subsequently, referring to fig. 1 and 4C, steps S114 and S116 are performed, and the memory device 10a is formed.

Fig. 6A and 6B are schematic cross-sectional views illustrating a memory device 10B and a memory device 10c according to some embodiments of the present disclosure. The memory devices 10B and 10C shown in fig. 6A and 6B are similar to the memory devices 10 and 10a shown in fig. 2I and 4C. Only the differences between the two will be explained and the same or similar components will not be described again.

Referring to fig. 2I and 6A, the memory device 10b shown in fig. 6A is similar to the memory device 10 shown in fig. 2I, but there is no air gap between the passivation layer 132a and the bottom electrode 126 shown in fig. 6A. In some embodiments, the passivation layer 132a fills the cavity defined by the bottom electrode 126, the overlying resistance variable layer 124, and the underlying bottom electrode 128, and is in physical contact with the sidewalls 126S of the bottom electrode 126. In these embodiments, the surface of the passivation layer 132a may also have recesses corresponding to these currently filled cavities. The method for forming the passivation layer 132a shown in fig. 6A may include an ALD process.

Referring to fig. 4C and 6B, similarly, the difference between the memory device 10C shown in fig. 6B and the memory device 10a shown in fig. 4C is that there is no air gap between the passivation layer 132a and the bottom electrode 126a shown in fig. 6B. In some embodiments, the passivation layer 132a fills the cavity defined by the bottom electrode 126a, the overlying resistance variable layer 124, and the underlying bottom electrode 128, and the passivation layer 132a is in physical contact with the sidewalls 126aS of the bottom electrode 126 a. Additionally, the surface of the passivation layer 132a may be recessed at the corresponding locations of these currently filled cavities. The method for forming the passivation layer 132a shown in fig. 6B may include an ALD process.

As described above, a memory device according to an embodiment of the present disclosure includes a memory cell including a composite bottom electrode, a top electrode, and a resistance variable layer interposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. The sidewalls of the second bottom electrode are recessed and recessed in a lateral direction from other portions of the memory cell. Thus, the isolation distance from the top electrode to the composite bottom electrode along the sidewalls of the memory cell increases. In addition, during recessing the bottom electrode in the lateral direction, possible remnants of conductive material remaining between the top electrode and the composite bottom electrode may be removed. Thus, the isolation between the top electrode and the composite bottom electrode is improved. The composite bottom electrode according to embodiments of the present disclosure may have a smaller footprint due to the use of a smaller mask without the surrounding spacers to pattern the composite bottom electrode, as compared to providing a spacer surrounding the top electrode (the pattern of the composite bottom electrode would be defined by the outer contours of the surrounding spacer). In this way, the isolation between the top electrode and the composite bottom electrode can be ensured without reducing the spacing between the laterally adjacent memory cells (i.e., the spacing between the laterally adjacent composite bottom electrodes), and therefore the isolation between the laterally adjacent memory cells can also be improved. Furthermore, by omitting the formation of the above-described spacers, at least one deposition step and at least one etching step may be saved. Therefore, the manufacturing cost is reduced.

In an aspect of the present disclosure, a memory device is provided. The memory device includes a composite bottom electrode, a top electrode, and a resistance variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. Sidewalls of the second bottom electrode are recessed laterally with respect to sidewalls of the first bottom electrode layer and sidewalls of the resistance variable layer.

In some embodiments, the memory device further comprises: a hard mask disposed over the top electrode. In some embodiments, wherein a sidewall of the hard mask is substantially coplanar with a sidewall of the top electrode, the sidewall of the resistance variable layer, and the sidewall of the first bottom electrode. In some embodiments, the memory device further comprises: a passivation layer covering the composite bottom electrode, the resistance variable layer, and the top electrode. In some embodiments, wherein the passivation layer is in physical contact with a sidewall of the top electrode. In some embodiments, wherein the passivation layer is in physical contact with the sidewall of the second bottom electrode of the composite bottom electrode. In some embodiments, wherein an air gap is located between the sidewall of the second bottom electrode and the passivation layer. In some embodiments, wherein the second bottom electrode is surrounded by the air gap. In some embodiments, wherein the sidewall of the second bottom electrode has a curved surface, and a most concave portion of the sidewall of the second bottom electrode is located at a bottom surface of the resistance variable layer. In some embodiments, wherein the sidewall of the second bottom electrode has a curved surface, and a most concave portion of the sidewall of the second bottom electrode is located at about half the thickness of the second bottom electrode.

In another aspect of the present disclosure, a memory integrated circuit is provided. The memory integrated circuit comprises a plurality of memory cells, a plurality of bit lines and a plurality of word lines. The plurality of memory cells are arranged in an array. Each of the plurality of memory cells comprises a memory device, and the memory device comprises a composite bottom electrode, a top electrode, a resistance variable layer between the composite bottom electrode and the top electrode, and a passivation layer covering the top electrode, the resistance variable layer, and the composite bottom electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. Sidewalls of the second bottom electrode are recessed laterally with respect to sidewalls of the first bottom electrode and sidewalls of the resistance variable layer. The plurality of bit lines extend along a first direction. The plurality of word lines extend along a second direction crossing the first direction. Each of the memory devices is electrically connected between one of the plurality of bit lines and one of the plurality of word lines.

In some embodiments, wherein the passivation layer is in physical contact with the sidewall of the second bottom electrode of the composite bottom electrode. In some embodiments, wherein an air gap is located between the sidewall of the second bottom electrode and the passivation layer. In some embodiments, wherein an air gap surrounding the second bottom electrode is located between the sidewall of the second bottom electrode and the passivation layer. In some embodiments, wherein each of the plurality of memory cells further comprises a transistor, one of a source terminal and a drain terminal of the transistor is electrically connected to the memory device, the other of the source terminal and the drain terminal is electrically connected to a source line, and a gate terminal of the transistor is connected to one of the plurality of word lines.

In yet another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method comprises the following steps: sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistance variable material layer, a top electrode layer and a hard mask layer on the device substrate; patterning the hard mask layer to form a hard mask; patterning the top electrode layer using the hard mask as a mask, patterning the resistance variable material layer, patterning the second bottom electrode layer, and patterning the first bottom electrode layer; and recessing the second bottom electrode layer laterally with respect to the patterned resistance variable material layer.

In some embodiments, wherein after patterning the resistance variable material layer and before patterning the first bottom electrode layer, a single etch process is performed using the hard mask as the mask to pattern the second bottom electrode layer and recess the second bottom electrode layer in a lateral direction. In some embodiments, wherein a first etching process is performed to pattern the second bottom electrode layer using the hard mask as the mask, and a second etching process is performed to recess the second bottom electrode layer in a lateral direction, and the first etching process and the second etching process are different etching processes. In some embodiments, the second etching process for recessing the second bottom electrode layer in a lateral direction is performed before patterning the first bottom electrode layer. In some embodiments, the second etching process for recessing the second bottom electrode layer in the lateral direction is performed after patterning the first bottom electrode layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.