阅读说明：本技术 一种超晶格结构薄膜及其应用 (Superlattice structure film and application thereof ) 是由 彭悦 韩根全 张悦媛 肖文武 刘艳 郝跃 于 2021-08-09 设计创作，主要内容包括：本发明公开了一种超晶格结构薄膜及其应用。本发明的超晶格结构薄膜为多层膜结构,由HfO-(2)和ZrO-(2)周期性交替叠加形成,总厚度为6-20nm；一个周期里所述HfO-(2)和ZrO-(2)的层数相同。本发明的超晶格结构薄膜铁电特性优异,可作为铁电栅介质层替代传统铁电场效应晶体管中的铁电栅介质层,极大地降低栅泄漏电流,优化介质层的介电常数,在提升铁电极化的同时提高器件的抗疲劳特性。(The invention discloses a superlattice structure film and application thereof. The superlattice structure film of the invention is a multilayer film structure and is made of HfO 2 And ZrO 2 Periodically and alternately stacked to form the composite material, and the total thickness is 6-20 nm; said HfO during one cycle 2 And ZrO 2 The number of layers is the same. The superlattice structure film disclosed by the invention has excellent ferroelectric property, can be used as a ferroelectric gate dielectric layer to replace a ferroelectric gate dielectric layer in a traditional ferroelectric field effect transistor, greatly reduces gate leakage current, optimizes the dielectric constant of the dielectric layer, and improves the anti-fatigue property of a device while improving ferroelectric polarization.)

1. The superlattice structure film is a multilayer film structure and is characterized by comprising multiple layers of HfO₂And multi-layered ZrO₂Alternately stacked to form the composite material with the total thickness of 6-20 nm;

said HfO during one cycle₂And ZrO₂The number of layers is the same.

2. The superlattice structure thin film as claimed in claim 1,

said HfO during one cycle₂And ZrO₂The number of layers is 5-15 respectively; preferably 5, 10 or 15 layers;

said HfO during one cycle₂And ZrO₂The total thicknesses were 4.16 angstroms, 8.33 angstroms, and 12.5 angstroms, respectively.

3. The method for producing a superlattice structure thin film as claimed in claim 1 or 2, wherein the HfO is formed by atomic layer deposition, magnetron sputtering, or pulsed laser deposition using TDMAHf and TDMAZr as a hafnium source and a zirconium source₂And ZrO₂And alternately overlapping after being respectively overlapped.

4. Use of the superlattice structure thin film as claimed in claim 1 or 2 in a ferroelectric field effect transistor or a ferroelectric capacitor.

5. A ferroelectric field effect transistor, wherein the superlattice structured thin film as claimed in claim 1 or 2 is used as a ferroelectric gate dielectric layer.

6. The ferroelectric field effect transistor as claimed in claim 5, wherein the ferroelectric field effect transistor comprises: the transistor comprises a substrate (1), a source region (2), a drain region (3), a channel (4), a ferroelectric gate dielectric layer (5), a gate electrode (6), a drain electrode (7) and a source electrode (8); the channel (4) is positioned in the center above the substrate (1), the source region (2) and the drain region (3) are distributed on two sides of the channel (4), the drain electrode (7) and the source electrode (8) are respectively distributed above the drain region (3) and the source region (2), and the ferroelectric gate dielectric layer (5) and the gate electrode (6) are sequentially and vertically distributed above the channel (4) from bottom to top;

the substrate is made of a semiconductor or a metal.

7. A method of manufacturing a ferroelectric field effect transistor as claimed in claim 5 or 6, characterized by comprising the steps of:

(1) depositing a superlattice structure film on a substrate (1) to form a ferroelectric gate dielectric layer (5);

(2) depositing TaN on the ferroelectric gate dielectric layer obtained in the step (1) by utilizing a magnetron sputtering process to form a gate electrode (6);

(3) calibrating a source region, a gate region and a drain region on the gate electrode by using a photoetching process;

(4) etching redundant parts around the source electrode area and the drain electrode area to the surface of the substrate by using an etching process, and etching the source electrode area and the drain electrode area on two sides of the grid electrode area to the surface of the substrate;

(5) performing ion implantation on the substrate of the etched source electrode region and drain electrode region to form a source electrode region (2) and a drain electrode region (3), wherein the substrate of the region which is at the same horizontal height and is not subjected to the ion implantation is a channel (4);

(6) activating the source region and the drain region in the step (5) by using an annealing process;

(7) and (5) depositing metal on the upper surfaces of the source region and the drain region in the step (6) by using an electron beam process to form a source electrode (8) and a drain electrode (7), so as to obtain the ferroelectric field effect transistor.

8. A method of manufacturing a ferroelectric field effect transistor as claimed in claim 7, characterized by comprising the steps of:

the deposition method in the step (1) is atomic layer deposition, magnetron sputtering or pulsed laser deposition;

the magnetron sputtering process in the step (2) comprises the following steps: under nitrogen and argon atmosphere, with solid Ta as the sputtering target, 1X 10^-7-1.5×10^-7Growing TaN under pa pressure;

the thickness of the TaN in the step (2) is 50-100 nm;

the etching in the step (4) is carried out under the masking action of the photoresist by taking chlorine radical as an etching agent;

the ion implantation process in the step (5) comprises the following steps: the implantation energy is 20-30keV, and the ion dose is 1 × 10¹⁵-2×10¹⁵cm^-3；

The ion implanted in the step (5) is: BF implantation in P-type transistor preparation₂ ⁺Ion implantation of P in N-type transistor fabrication⁺Ions;

the annealing process in the step (6) comprises the following steps: thermally annealing the source and the drain for 2-5min at the temperature of 400-900 ℃;

the process for depositing the metal in the step (7) comprises the following steps: taking solid Ni as a source, and depositing Ni on the upper surfaces of the source region and the drain region;

the thickness of the metal in the step (7) is 20-100 nm;

the sequence of the steps in the preparation method of the ferroelectric field effect transistor can be adjusted according to the substrate: firstly, carrying out ion implantation on a source electrode region and a drain electrode region, annealing, then depositing a superlattice structure film, sputtering TaN, and depositing Ni.

9. A ferroelectric capacitor, comprising an upper electrode (1), a ferroelectric gate dielectric layer (2), and a substrate (3), wherein the ferroelectric gate dielectric layer is the superlattice structure thin film as claimed in claim 1 or 2;

the substrate is made of a semiconductor or a metal.

10. A method for manufacturing a ferroelectric capacitor as defined in claim 9, comprising the steps of: depositing a ferroelectric gate dielectric layer on a substrate, forming an upper electrode on the ferroelectric gate dielectric layer by adopting a photoetching stripping process, or depositing TaN on the ferroelectric gate dielectric layer by adopting atomic layer deposition or magnetron sputtering, and photoetching and etching to form the upper electrode to obtain a ferroelectric capacitor;

the deposition method is atomic layer deposition, magnetron sputtering or pulsed laser deposition;

the deposition of TaN is carried out in a nitrogen or argon environment;

the pressure for depositing TaN is 1 × 10^-7-1.5×10^-7pa；

The thickness of the deposited TaN is 50-100 nm;

the etching is carried out under the masking action of the photoresist by adopting a chlorine radical as an etching agent;

and the ferroelectric capacitor is activated by thermal annealing for 30-60s in a nitrogen atmosphere.

Technical Field

The invention relates to the technical field of electronics, in particular to a superlattice structure film and application thereof.

Background

The semiconductor memory is used as a device for storing information of an electronic system, is a core component for ensuring the normal operation of the system, and has the requirements of high storage density, high writing speed, low power consumption, multiple erasable times, stable storage state and the like. Under such circumstances, new low-power-consumption and nonvolatile memory technologies including Resistive Random Access Memories (RRAMs), Phase Change Memories (PCMs), magnetic memories (MRAMs), and ferroelectric memories have become important for the research of microelectronic devices. Ferroelectric field effect transistors (fefets) have many significant advantages in ferroelectric memories, including non-volatile data storage, program/erase times in the nanosecond range, low operating voltages, virtually unlimited endurance, and lossless read-out.

Based on HfO₂Thin film ferroelectric field effect transistors are receiving attention as emerging nonvolatile memories due to their expandability and CMOS compatibility, however, their fatigue resistance is far from the conventional perovskite ferroelectric materials, and thus cannot meet the application requirements of high performance devices.

Atomic Layer Deposition (ALD) is the preferred method for preparing gate dielectric thin films due to its precise thickness control, excellent three-dimensional conformability, and uniform large-area film formation.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a superlattice structure thin film.

The invention also aims to provide a preparation method of the superlattice structure thin film.

It is still another object of the present invention to provide the use of the above superlattice structure thin film in a ferroelectric field effect transistor.

The purpose of the invention is realized by the following technical scheme: a superlattice structure film with a multilayer film structure and multiple layers of HfO₂And multi-layered ZrO₂Alternately stacked to form the composite material with the total thickness of 6-20 nm.

Preferably, the HfO is present in one cycle₂And ZrO₂The number of layers is the same; more preferably, the number of layers is 5 to 15, respectively; most preferably, the number of layers is 5, 10 or 15 layers, respectively.

Preferably, the HfO is present in one cycle₂And ZrO₂The total thicknesses were 4.16 angstroms, 8.33 angstroms, and 12.5 angstroms, respectively.

The HfO₂And ZrO₂The period length is several times or more larger than the lattice constant of the single crystal of each layer.

The preparation method of the superlattice structure film adopts the Atomic Layer Deposition (ALD), magnetron sputtering or pulse laser deposition method, adopts TDMAHf and TDMAZr as a hafnium source and a zirconium source, and uses HfO₂And ZrO₂And alternately overlapping after being respectively overlapped.

The superlattice structure thin film is applied to ferroelectric field effect transistors and ferroelectric (MFM) capacitors.

The superlattice structure film is used as a ferroelectric gate dielectric layer.

The ferroelectric field effect transistor includes: the transistor comprises a substrate (1), a source region (2), a drain region (3), a channel (4), a ferroelectric gate dielectric layer (5), a gate electrode (6), a drain electrode (7) and a source electrode (8); the channel (4) is located in the center above the substrate (1), the source region (2) and the drain region (3) are distributed on two sides of the channel (4), the drain electrode (7) and the source electrode (8) are respectively distributed above the drain region (3) and the source region (2), and the ferroelectric gate dielectric layer (5) and the gate electrode (6) are sequentially and vertically distributed above the channel (4) from bottom to top.

Preferably, the material of the substrate is a semiconductor or a metal; more preferably Ge, Si_0.55Ge_0.45Or Si.

The preparation method of the ferroelectric field effect transistor comprises the following steps:

(1) depositing a superlattice structure film on a substrate (1) to form a ferroelectric gate dielectric layer (5);

(2) depositing TaN on the ferroelectric gate dielectric layer obtained in the step (1) by utilizing a magnetron sputtering process to form a gate electrode (6);

(3) calibrating a source region, a gate region and a drain region on the gate electrode by using a photoetching process;

(4) etching redundant parts around the source electrode area and the drain electrode area to the surface of the substrate by using an etching process, and etching the source electrode area and the drain electrode area on two sides of the grid electrode area to the surface of the substrate;

(5) performing ion implantation on the substrate of the etched source electrode region and drain electrode region to form a source electrode region (2) and a drain electrode region (3), wherein the substrate of the region which is at the same horizontal height and is not subjected to the ion implantation is a channel (4);

(6) activating the source region and the drain region in the step (5) by using an annealing process;

(7) and (5) depositing metal on the upper surfaces of the source region and the drain region in the step (6) by using an electron beam process to form a source electrode (8) and a drain electrode (7), so as to obtain the ferroelectric field effect transistor.

Preferably, the order of steps in the method for manufacturing the ferroelectric field effect transistor can be adjusted according to the substrate: firstly, carrying out ion implantation on a source electrode region and a drain electrode region, annealing, then depositing a superlattice structure film, sputtering TaN, and depositing Ni.

Preferably, the deposition method in step (1) is atomic layer deposition, magnetron sputtering or pulsed laser deposition.

Preferably, the magnetron sputtering process in the step (2) is as follows: under nitrogen and argon atmosphere, with solid Ta as the sputtering target, 1X 10^-7-1.5×10^-7Growing TaN under pa pressure;

preferably, the thickness of the TaN in the step (2) is 50-100 nm; more preferably, the thickness is 80 nm.

Preferably, the etching in step (4) is performed under the masking action of the photoresist by using chlorine-based radicals as an etchant.

Preferably, the ion implantation process in step (5) is as follows: the implantation energy is 20-30keV, and the ion dose is 1 × 10¹⁵-2×10¹⁵cm^-3。

Preferably, the ion implanted ions of step (5)Comprises the following steps: BF implantation in P-type transistor preparation₂ ⁺Ion implantation of P in N-type transistor fabrication⁺Ions.

Preferably, the annealing process of step (6) is: and thermally annealing the source and the drain for 2-5min at the temperature of 400-900 ℃.

Preferably, the process for depositing the metal in the step (7) is as follows: and taking solid Ni as a source, and depositing Ni on the upper surfaces of the source region and the drain region.

Preferably, the thickness of the metal in the step (7) is 20-100 nm; more preferably, the thickness is 30 nm.

A ferroelectric capacitor comprises an upper electrode (1), a ferroelectric gate dielectric layer (2) and a substrate (3), wherein the ferroelectric gate dielectric layer is the superlattice structure film.

Preferably, the material of the substrate is a semiconductor or a metal; more preferably Ge, Si_0.55Ge_0.45Or Si.

The preparation method of the ferroelectric capacitor comprises the following steps: depositing a ferroelectric gate dielectric layer on a substrate, forming an upper electrode on the ferroelectric gate dielectric layer by adopting a photoetching stripping process, or depositing TaN on the ferroelectric gate dielectric layer by adopting atomic layer deposition or magnetron sputtering, and photoetching and etching to form the upper electrode to obtain the ferroelectric capacitor.

Preferably, the deposition method is atomic layer deposition, magnetron sputtering or pulsed laser deposition.

Preferably, the deposition of TaN is performed under a nitrogen or argon atmosphere.

Preferably, the pressure for depositing TaN is 1 × 10^-7-1.5×10^-7pa。

Preferably, the thickness of the deposited TaN is 50-100 nm.

Preferably, the etching is performed under the masking action of the photoresist using chlorine-based radicals as an etchant.

Preferably, the ferroelectric capacitor is activated by thermal annealing in a nitrogen atmosphere for 30-60 s.

Compared with the prior art, the invention has the following beneficial effects:

the superlattice structure film disclosed by the invention has excellent ferroelectric properties, can be used as a ferroelectric gate dielectric layer to replace the ferroelectric gate dielectric layer in the traditional ferroelectric field effect transistor and ferroelectric capacitor, greatly reduces gate leakage current, optimizes the dielectric constant of the dielectric layer, and improves the fatigue resistance of a device while improving ferroelectric polarization.

Drawings

FIG. 1 is a schematic cross-sectional view of a ferroelectric field effect transistor fabricated using a superlattice structure thin film as a ferroelectric gate dielectric layer in accordance with example 3; wherein, 1 is a substrate, 2 is a source region, 3 is a drain region, 4 is a channel, 5 is a ferroelectric gate dielectric layer, 6 is a gate electrode, 7 is a drain electrode, and 8 is a source electrode.

FIG. 2 shows an HfO of an MFM (Metal-Ferroelectric-Metal) capacitor₂-ZrO₂TEM schematic diagram and element analysis diagram of the superlattice structure film; wherein a is a TEM schematic diagram; b is an element analysis diagram, and DF4, Hf, Zr, O and Si are arranged from top to bottom in sequence.

FIG. 3 is a view showing a conventional HfZrO_xTEM schematic and elemental analysis of the film; wherein a is a TEM schematic diagram; b is an element analysis diagram, and DF4, Hf, Zr, O and Si are arranged from top to bottom in sequence.

FIG. 4 is a schematic structural diagram of a ferroelectric capacitor fabricated by using the superlattice structure thin film as a dielectric layer in example 4; wherein, 1 is an upper electrode, 2 is a dielectric layer, and 3 is a substrate.

FIG. 5 shows HfO-based sample of example 4₂-ZrO₂Ferroelectric capacitor of superlattice structure film and conventional HfZrO based ferroelectric capacitor_xP-V comparison plot of MFM capacitance for thin films; wherein (a) and (c) are based on conventional HfZrO_xThe MFM capacitance of the film is shown in P-V diagram at different annealing times, (b) and (d) are based on HfO₂-ZrO₂P-V diagram of MFM capacitance of the superlattice structure film at different annealing times; the abscissa represents applied voltage, and the ordinate represents polarization intensity, which characterizes the polarization degree of the material.

FIG. 6 is based on HfO₂-ZrO₂+ -P of ferroelectric gate dielectric field effect transistor with superlattice structure film and conventional ferroelectric gate dielectric field effect transistor_rThe plots are compared as the cycles increase.

FIG. 7 is based on HfO₂-ZrO₂+ -V of ferroelectric gate dielectric field effect transistor with superlattice structure and conventional ferroelectric gate dielectric field effect transistor_cThe plots are compared as the cycles increase.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

EXAMPLE 1 fabrication of Ge-based p-type field Effect transistor

Step 1: depositing a 15-layer HfO layer on a Ge substrate for one period by using an atomic layer deposition process₂+15 layers of ZrO₂Forming a ferroelectric gate dielectric layer with a superlattice structure and a thickness of 15 nm;

step 2: by utilizing a sputtering process, on a ferroelectric gate dielectric film with a superlattice structure, solid Ta is used as a sputtering target at room temperature, and the pressure is 1 multiplied by 10 under the environment of nitrogen and argon^-7Growing TaN with the thickness of 80nm under pa to form a gate electrode;

and step 3: calibrating a source electrode area, a grid electrode area and a drain electrode area on the grid electrode layer by utilizing a photoetching process;

and 4, step 4: etching the redundant parts around the source electrode area and the drain electrode area to the surface of the substrate by using an etching process and adopting chlorine radical as an etching agent under the masking action of photoresist, and etching the source electrode area and the drain electrode area to the surface of the substrate;

and 5: performing ion implantation on the substrate of the etched source electrode region and drain electrode region:

the substrate implantation energy in the source region is 20keV and the dose is 1 × 10¹⁵cm^-3BF of₂ ⁺Ions to form a P + doped source region;

the substrate implantation energy in the drain region is 20keV and the dose is 1X 10¹⁵cm^-3BF of₂ ⁺Ions to form a P + doped drain region;

step 6: performing thermal annealing on the source electrode and the drain electrode for 5min at the temperature of 400 ℃ by using an annealing process to obtain a source electrode region and a drain electrode region;

and 7: and (3) utilizing an electron beam deposition process, taking solid Ni as a source at room temperature, and depositing 30nm of Ni on the upper surfaces of the source region and the drain region to form a source electrode and a drain electrode to obtain the ferroelectric field effect transistor.

Example 2 production of Si_0.55Ge_0.45Base p-type field effect transistor

Step 1: by atomic layer deposition on Si_0.55Ge_0.45Depositing 10 layers of HfO on the substrate in one period₂+10 layers of ZrO₂Forming a ferroelectric gate dielectric layer with a superlattice structure and a thickness of 20 nm;

step 2: depositing TaN on the ferroelectric gate dielectric film with the superlattice structure by using a sputtering process to form a gate electrode, wherein the specific implementation of the step is the same as that of the step 2 in the embodiment 1;

and step 3: calibrating a source region, a gate region and a drain region on the TaN layer by using a photoetching process, wherein the specific implementation of the step is the same as that of the step 3 in the embodiment 1;

and 4, step 4: and etching the source region and the drain region to the surface of the substrate by using an etching process, and etching redundant parts around the gate region, the source region and the drain region to the surface of the substrate, wherein the specific implementation of the step is the same as that of the step 4 in the embodiment 1.

And 5: and performing ion implantation on the substrate of the etched source region and drain region to form a P + doped source region and drain region, wherein the specific implementation of the step is the same as that of step 5 in embodiment 1.

Step 6: and performing thermal annealing on the source electrode and the drain electrode for 5min at 600 ℃ by using an annealing process to obtain a source electrode region and a drain electrode region.

And 7: and (3) depositing 30nm Ni above the source region and the drain region by using an electron beam deposition process and taking solid Ni as a source under a room temperature environment to form a source electrode and a drain electrode to obtain the ferroelectric field effect transistor.

EXAMPLE 3 fabrication of Si-based n-type field Effect transistor

Step 1: and calibrating a source region, a gate region and a drain region on the Si substrate by utilizing a photoetching process.

Step 2: and performing ion implantation on the source region and the drain region after photoetching:

the implantation energy in the source region is 30keV and the dose is 2 × 10¹⁵cm^-3Forming an N + doped source region;

the implantation energy in the drain region is 30keV and the dose is 2X 10¹⁵cm^-3Forming an N + doped source region;

and step 3: and performing thermal annealing on the source electrode and the drain electrode for 2min at 900 ℃ by using an annealing process to obtain a source electrode region and a drain electrode region.

And 4, step 4: depositing 5 layers of HfO in a gate region on a Si substrate by using an atomic layer deposition process₂+5 layers of ZrO₂The ferroelectric gate dielectric with a superlattice structure and a thickness of 10nm is formed on the superlattice structure film;

and 5: by utilizing a sputtering process, on a ferroelectric gate dielectric film with a superlattice structure, at room temperature, solid Ta is used as a sputtering target, and the pressure is 1 multiplied by 10 under the environment of nitrogen and argon^-7And growing TaN under pa to form a gate electrode.

Step 6: and calibrating a source region, a gate region and a drain region on the TaN layer by using a photoetching process and a photoetching process on the gate layer.

And 7: and etching the redundant parts around the source region and the drain region to the surface of the substrate by using an etching process and adopting chlorine-based radicals as an etching agent under the masking action of photoresist, etching the TaN sputtered on the surfaces of the source region and the drain region on two sides of the gate region, and positioning a channel under the ferroelectric gate dielectric film with the superlattice structure.

And 8: and (3) depositing 30nm Ni above the source region and the drain region by using an electron beam deposition process and taking solid Ni as a source under a room temperature environment to form a source electrode and a drain electrode to obtain the ferroelectric field effect transistor. The structure is shown in figure 1.

HfO through multiple cycles in this example₂And ZrO₂Alternating deposition to HfO₂-ZrO₂The result of Transmission Electron Microscopy (TEM) of the superlattice structure thin film is shown in FIG. 1. The superlattice structure of the film keeps strict periodicity, the two atomic layer films are arranged in a periodic alternating mode, and the period length is several times or longer than the lattice constant of each film single crystal, so that complete atomic arrangement in the figure 2a can be obtained, the integrity of the multilayer structure is good, and the situations of aliasing, fusion and the like between layers are avoided. In connection with the elemental analysis shown in fig. 1 (fig. 2b), the Hf element and the Zr element exhibit the same periodic, alternating delamination along the layered structure as atomic layer delamination, illustrating that the periodic alternating layer structure is made of HfO₂And ZrO₂Two materials, thereby demonstrating HfO by multiple cycles₂And ZrO₂The alternately deposited thin film structure is a superlattice structure thin film.

Preparation of HfZrO by using TDMAHf and TDMAZr as hafnium source and zirconium source_xThin film (one period is 1 HfO layer)₂+1 layer of ZrO₂) The HfZrO_xFilm structure referring to fig. 3, the film did not delaminate (fig. 3a), and in conjunction with elemental analysis, although Hf and Zr elements also appeared, the atoms of the different elements were mixed together (fig. 3b) and thus were a single layer film, i.e., not a superlattice structure.

EXAMPLE 4 fabrication of ferroelectric capacitor

Step 1: depositing a superlattice structure film on the Ge substrate by utilizing an atomic layer deposition process to form a ferroelectric gate dielectric layer;

step 2: by utilizing a magnetron sputtering process, in a nitrogen environment, solid Ta is taken as a sputtering target, and the pressure range is 1 multiplied by 10^-7TaN with the thickness of 80nm is grown under pa, and the electrode is used as an upper electrode.

And step 3: calibrating an electrode area on the upper electrode by utilizing a 365nm I-line photoetching process;

and 4, step 4: and etching the redundant part outside the calibration electrode area by using an etching process, etching the areas on two sides of the upper electrode calibration electrode area to the surface of the substrate under the masking action of the photoresist by using chlorine-based radicals as an etching agent, and removing the photoresist.

And 5: the capacitor is thermally annealed for 30s and 60s in a nitrogen atmosphere by an annealing process at 550 ℃ to obtain the ferroelectric capacitor, and the structure of the ferroelectric capacitor is shown in fig. 4.

Effect detection

(1) The polarization of the ferroelectric capacitor was measured by applying a triangular wave to the ferroelectric capacitor of example 4 to read a curve of its polarization as a function of voltage. The results are shown in FIG. 5. Comparing (a) and (b) of FIG. 5, the conventional HfZrO when the applied voltage is zero_xThe residual polarization intensity of the film was 22.87. mu.C/cm²HfO in (b)₂-ZrO₂The residual polarization intensity of the superlattice structure film is 24.29 mu C/cm²(ii) a In addition, the saturation polarization intensity of the ferroelectric thin film and the HfZrO becomes different when the polarization state of the ferroelectric thin film is saturated_xThe saturation polarization of the film was 32.78. mu.C/cm²(c) And HfO₂-ZrO₂The saturation polarization of the superlattice structure film reaches 34.72 mu C/cm²(d) In that respect The same polarization improvement was observed in the capacitors with annealing times of 60s and 30s, demonstrating the prevalence of the superlattice structure film polarization improvement. Therefore, we can conclude that compared to conventional HfZrO_xFilm of HfO₂-ZrO₂The polarization of the superlattice structure film is improved.

(2) The fatigue characteristics of the devices were tested by applying a series of pulses to the ferroelectric gate dielectric field effect transistor of example 3. The fatigue property means that the reversible polarization of the ferroelectric film is reduced after the ferroelectric film is repeatedly turned over, so that the storage function is lost, and therefore, the fatigue resistance is an important index for measuring the storage performance of the device. In FIGS. 6 and 7, the open circular curves indicate curves based on conventional HfZrO_xFerroelectric field effect transistor of thin film with square curve based on HfO₂-ZrO₂Ferroelectric field effect transistor of superlattice structure film; the abscissa is the number of cycles of the pulse, and the ordinate is + -P_r、±V_c，±P_rIs the remanent polarization of the device, but + -V_cThe difference value of the two can be used for characterizing the fatigue resistance of the ferroelectric gate dielectric field effect transistor for the switching voltage of the device. The slower the speed at which the difference between the two parameters becomes smaller as the number of pulse periods increases, indicates the better fatigue resistance of the device. In FIGS. 6 and 7, based on conventional HfZrO_xThin film ferroelectric field effect transistors at 10¹²cycles around + -P_r、±V_cAll the difference values of (A) are less than 1 mu C/cm²And 1V, based on HfO₂-ZrO₂A superlattice structure thin film ferroelectric field effect transistor is at 10¹³cycles are followed by a considerable P_r、±V_cThis description is based on HfO₂-ZrO₂The ferroelectric field effect transistor of the superlattice structure film has fatigue resistance greater than 10¹³cycles. Therefore, it can be concluded that the fatigue resistance of the ferroelectric gate dielectric field effect transistor based on the superlattice structure thin film is better than that of the conventional ferroelectric gate dielectric field effect transistor.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.