阅读说明：本技术 显示面板、其驱动方法及显示装置 (Display panel, driving method thereof and display device ) 是由 秦相磊 林坚 张勇 杨智超 张丽敏 孙泽鹏 唐亮珍 段智龙 金红贵 安亚帅 乜玲 于 2020-02-20 设计创作，主要内容包括：显示面板、其驱动方法及显示装置,其中,显示面板包括：衬底基板(100)；多个子像素,设置于衬底基板(100)上,多个子像素中的至少一个包括反射电极；其中,反射电极至少包括彼此绝缘间隔设置的第一反射电极(110-1)和第二反射电极(110-2),第一反射电极(110-1)设置有第一通孔(111),第二反射电极(110-2)设置有第二通孔(112),第一通孔(111)的面积与第二通孔(112)的面积不同。(A display panel, a driving method thereof and a display device are provided, wherein the display panel comprises: a base substrate (100); a plurality of sub-pixels disposed on the base substrate (100), at least one of the plurality of sub-pixels including a reflective electrode; the reflective electrode at least comprises a first reflective electrode (110-1) and a second reflective electrode (110-2) which are arranged at intervals in an insulating mode, the first reflective electrode (110-1) is provided with a first through hole (111), the second reflective electrode (110-2) is provided with a second through hole (112), and the area of the first through hole (111) is different from the area of the second through hole (112).)

A display panel, comprising:

a substrate base plate;

a plurality of sub-pixels disposed on the substrate, at least one of the plurality of sub-pixels including a reflective electrode;

the reflective electrode at least comprises a first reflective electrode and a second reflective electrode which are insulated from each other and arranged at intervals, the first reflective electrode is provided with a first through hole, the second reflective electrode is provided with a second through hole, and the area of the first through hole is different from that of the second through hole.

The display panel of claim 1, wherein the substrate base has a first partition and a second partition, an orthogonal projection of the first reflective electrode on the substrate base is located within the first partition, and an orthogonal projection of the second reflective electrode on the substrate base is located within the second partition;

the display panel further includes:

an opposite substrate arranged opposite to the substrate;

a color resist layer between the base substrate and the counter substrate, the color resist layer including: a sub-color resist layer located at each of the sub-pixels;

the sub-color-resistance layer is provided with a first sub-color-resistance area and a second sub-color-resistance area, the first sub-color-resistance area is covered by the first sub-area, and the second sub-color-resistance area is covered by the second sub-color-resistance area in the direction perpendicular to the plane of the substrate base plate.

The display panel of claim 2, wherein the first reflective electrode has a first facing area with the sub color resistance layer in the first sub color resistance region;

the second reflecting electrode and the sub color resistance layer positioned in the second sub color resistance area have a second opposite area;

in the same sub-pixel, the first facing area is different from the second facing area.

The display panel according to claim 3, wherein the area of the first reflective electrode and the area of the second reflective electrode are substantially the same in the same sub-pixel, and the area of the first sub-color-resistance region is smaller than the area of the second sub-color-resistance region.

The display panel according to claim 4, wherein the sub color resist layer in the first partition is provided with a first via hole, and the first via hole penetrates through the sub color resist layer;

the orthographic projection of the first through hole on the substrate base plate is not overlapped with the orthographic projection of the first through hole on the substrate base plate.

The display panel of claim 5, wherein the plurality of sub-pixels includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;

the area of the first via hole in the second color sub-pixel is larger than that of the first via hole in the first color sub-pixel; and/or the presence of a gas in the gas,

the area of the first through hole in the first color sub-pixel is larger than that of the first through hole in the third color sub-pixel.

The display panel of claim 6, wherein the first color sub-pixel has opposing first and second sides; wherein the first side and the second side are aligned along a first direction; the first via hole in the first color sub-pixel comprises a first sub-via hole and a second sub-via hole; the first sub-via is located at the first side, and the second sub-via is located at the second side; and/or the presence of a gas in the gas,

the second color sub-pixel has opposing third and fourth sides; wherein the third and fourth sides are aligned along a first direction; a first via within the second color sub-pixel extends from the third side to the fourth side in an orthographic projection of the substrate base plate; and/or the presence of a gas in the gas,

the third color sub-pixel has opposite fifth and sixth sides; wherein the fifth side and the sixth side are aligned along a first direction; the first via hole in the third color sub-pixel comprises a third sub-via hole and a fourth sub-via hole; the third sub-via is located at the fifth side, and the fourth sub-via is located at the sixth side.

The display panel of claim 7, wherein an area of the first sub-via is substantially the same as an area of the second sub-via; and/or the presence of a gas in the gas,

the area of the third sub-via is substantially the same as the area of the fourth sub-via.

The display panel according to claim 7 or 8, wherein centers of the first via holes in the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are arranged on a same straight line along the first direction.

The display panel of claim 3, wherein in the same sub-pixel, the area of the first reflective electrode is smaller than that of the second reflective electrode, and the area of the first sub-color-resistant region is smaller than or substantially equal to that of the second sub-color-resistant region.

The display panel of any one of claims 2-10, wherein the display panel further comprises:

the first planarization layer is positioned between the layer where the reflection electrode is positioned and the substrate base plate;

the source conducting layer is positioned between the first planarization layer and the substrate base plate and comprises a plurality of data lines which are arranged at intervals;

a gate insulating layer between the source conductive layer and the substrate base plate;

the grid conducting layer is positioned between the grid insulating layer and the substrate base plate and comprises a plurality of first grid lines and a plurality of second grid lines which are arranged at intervals;

the display panel further includes: a plurality of first transistors and a plurality of second transistors arranged at intervals; wherein an orthographic projection of one of the first transistors on the substrate base is located within one of the first partitions, and an orthographic projection of one of the second transistors on the substrate base is located within one of the second partitions,

the grid electrodes of the first transistors in one row of sub-pixels are electrically connected with the same first grid line;

the grid electrodes of the second transistors in one row of sub-pixels are electrically connected with the same second grid line;

a first pole of a first transistor and a first pole of a second transistor in a column of sub-pixels are electrically connected with the same data line;

in the same first partition, a second pole of the first transistor is electrically connected with the first reflecting electrode;

in the same second partition, a second pole of the second transistor is electrically connected to the second reflective electrode.

The display panel of claim 11, wherein orthographic projections of the first via holes on the substrate base plate do not overlap with orthographic projections of the source conductive layer and the gate conductive layer on the substrate base plate, respectively;

the orthographic projections of the second through holes on the substrate base plate are not overlapped with the orthographic projections of the source conducting layer and the grid conducting layer on the substrate base plate respectively.

The display panel of claim 11 or 12, wherein the gate conductive layer further comprises a plurality of third gate lines disposed at intervals; the display panel further includes: a plurality of third transistors arranged at intervals; wherein an orthographic projection of one of the third transistors on the substrate base plate is positioned in one of the sub-pixels;

the grid electrodes of the third transistors in one row of sub-pixels are electrically connected with the same third grid line;

in the same sub-pixel, the first transistor and the second transistor are electrically connected to the source connection portion through the third transistor.

The display panel of claim 13, wherein the source conductive layer further comprises: a plurality of source connections;

the source connection portion includes: a first sub-source connection and a second sub-source connection electrically connected to each other; wherein the first sub-source connection extends in a first direction and the second sub-source connection extends in a second direction; the first sub-source connection part is electrically connected to the data line, and the second sub-source connection part is electrically connected to the third transistor.

The display panel of claim 14, wherein an orthographic projection of the first sub-via on the substrate base plate is between an orthographic projection of the first sub-source connection part on the substrate base plate and an orthographic projection of the data line on the substrate base plate, and an orthographic projection of the first sub-via on the substrate base plate is between an orthographic projection of the second sub-source connection part on the substrate base plate and an orthographic projection of the third gate line on the substrate base plate.

The display panel of any one of claims 1-15, wherein the display panel further comprises: the transparent conducting layer is positioned on one side of the reflecting electrode, which is far away from the substrate;

the transparent conducting layer comprises a plurality of first sub transparent conducting parts arranged at intervals; wherein an orthographic projection of one of the first sub-transparent conductive parts on the substrate base plate is positioned in one of the first partitions;

in the same first partition, the orthographic projection of the first sub-transparent conductive part on the substrate covers the orthographic projection of the first through hole on the substrate, and the orthographic projection of the first sub-transparent conductive part on the substrate is located in the orthographic projection of the first reflective electrode on the substrate.

The display panel according to claim 16, wherein the transparent conductive layer includes a plurality of second sub transparent conductive portions arranged at intervals; wherein an orthographic projection of one of the second sub-transparent conductive parts on the substrate base plate is positioned in one of the second subareas;

in the same second partition, the orthographic projection of the second sub transparent conductive part on the substrate base plate covers the orthographic projection of the second through hole on the substrate base plate, and the orthographic projection of the second sub transparent conductive part on the substrate base plate is positioned in the orthographic projection of the second reflection electrode on the substrate base plate.

A display device comprising the display panel according to any one of claims 1 to 17.

A driving method of the display panel according to any one of claims 1 to 17, comprising:

driving a row of sub-pixels in each data input phase of a frame time;

wherein driving a row of sub-pixels in one of said data writing phases comprises:

loading a grid opening signal to a first grid line electrically connected with the row sub-pixels, loading a grid closing signal to a second grid line electrically connected with the row sub-pixels, and loading a data signal to each data line to enable a first reflection electrode in the row sub-pixels to input the data signal;

and loading a grid closing signal to a first grid line electrically connected with the row sub-pixels, loading a grid opening signal to a second grid line electrically connected with the row sub-pixels, and loading a data signal to each data line to enable a second reflection electrode in the row sub-pixels to input the data signal.

The driving method of claim 19, wherein while the first gate line electrically connecting the row of sub-pixels is applied with a gate-on signal, further comprising: loading a grid opening signal to a third grid line electrically connected with the row of sub-pixels; and/or the presence of a gas in the gas,

when the second grid line electrically connected with the sub-pixels in the row is loaded with a grid opening signal, the method further comprises the following steps: and loading a grid opening signal to a third grid line electrically connected with the sub-pixels in the row.