阅读说明：本技术 一种射频功放芯片异构微封装方法 (Heterogeneous micro-packaging method for radio frequency power amplifier chip ) 是由 李镇兵 李泽华 孙浩洋 文光俊 于 2021-07-29 设计创作，主要内容包括：本发明公开一种射频功放芯片异构微封装方法,应用于射频技术领域,针对现有的封装技术在布孔时未考虑期间寿命的问题；本发明通过仿真技术对散热通孔进行优化,使得优化后的散热通孔布局满足芯片封装的相关参数性能,从而有效平衡芯片封装的射频性能与散热问题。(The invention discloses a heterogeneous micro-packaging method of a radio frequency power amplifier chip, which is applied to the technical field of radio frequency and aims at solving the problem that the service life of the existing packaging technology during hole distribution is not considered; according to the invention, the heat dissipation through holes are optimized through a simulation technology, so that the optimized heat dissipation through hole layout meets the related parameter performance of chip packaging, and the radio frequency performance and the heat dissipation problem of the chip packaging are effectively balanced.)

1. A heterogeneous micro-packaging method for a radio frequency power amplifier chip is characterized by comprising a through hole optimization process, and the specific optimization steps are as follows:

s1, modeling the chip package, and performing grid division on the modeling model according to the distribution condition of heat generated when the chip works normally;

s2, determining the highest temperature of each grid by using a thermal analysis tool;

s3, carrying out through hole optimization on grids one by one to obtain a grid layout meeting the working temperature requirement and the device service life requirement corresponding to the grids;

and S4, repeating the step S3 until the optimization of the through holes with more grids is completed.

2. The method for optimizing the heterogeneous micro-packaging hole distribution of the radio frequency power amplifier chip according to claim 1, wherein in the step S1, one grid corresponds to a plurality of heat dissipation through holes.

3. The heterogeneous micro-packaging method of the radio frequency power amplifier chip according to claim 2, wherein the number of the heat dissipation through holes in the grid at the active element position in the chip is larger than the number of the heat dissipation through holes in the grid at the passive element position.

4. The heterogeneous micro-packaging method of the radio frequency power amplifier chip according to claim 1, wherein the step S3 comprises the following sub-steps:

s31, determining the number of the heat dissipation holes in the initial grid layout;

s32, after the heat dissipation holes are distributed according to the number of the current heat dissipation holes, the highest temperature of the grid is obtained again according to the step S2, if the highest temperature meets the temperature of normal work of the chip, the step S33 is executed, otherwise, after the number of the heat dissipation holes is added with 1, the highest temperature of the grid is determined again according to the step S2 until the requirement is met;

s33, calculating the service life of the chip according to the current highest temperature of the grid; if the comparison result of the calculated service life and the reference value is greater than 0, the current heat dissipation hole layout scheme is saved, otherwise, the step S32 is returned.

5. The heterogeneous micro-packaging method for the radio frequency power amplifier chip according to claim 4, wherein the calculation formula of the number of the initial heat dissipation holes in the step S31 is as follows:

the number of vias is (the highest temperature of the grid-the temperature at which the chip operates normally)/the heat dissipation capacity of the thermal vias.

6. The heterogeneous micro-packaging method of the radio frequency power amplifier chip according to claim 5, wherein the heat dissipation through holes are distributed in an array manner.

Technical Field

The invention belongs to the technical field of radio frequency, and particularly relates to a heterogeneous micro-packaging technology of a radio frequency power amplifier chip.

Background

The radio frequency power amplifier is a radio frequency device which can generate power amplification effect on input radio frequency signals and output the amplified signals. With the continuous development of modern wireless communication systems, the rf power amplifier chip also develops toward higher operating frequency and smaller size, and its importance is self-evident as the core component of the wireless transmitter in the modern wireless communication system.

The chip packaging technology plays roles of placing, fixing, sealing, protecting the chip and enhancing the electric heating performance. Since the die of the chip must be isolated from the outside to prevent the electrical performance from being degraded due to the influence and damage to the circuit of the chip in the external environment, on the other hand, the packaged chip is more convenient to mount and transport. Through encapsulation, the influence of external environment on the internal circuit of the chip is avoided, and the chip is protected. Meanwhile, the packaging technology establishes a bridge between the chip and an external circuit through the pins and the wires, so that the packaging technology is very important for manufacturing the chip.

The following two common chip packaging techniques for rf power amplifiers are used:

the QFN package, one of surface mount packages, is a leadless package in a square or rectangular shape, a large-area exposed pad is arranged at the center of the bottom of the package for heat conduction, and a conductive pad for realizing electrical connection is arranged around the periphery of the package surrounding the large pad. The QFN package provides excellent electrical performance due to the short electrical path between the leads and pads within the package, low self-inductance, and low wiring resistance within the package. In addition, excellent heat dissipation is provided by the exposed leadframe pad, which has a direct heat dissipation path for dissipating heat within the package. Heat sink pads are typically soldered directly to the circuit board and heat sink vias in the PCB help to spread excess power dissipation into the copper ground plate, thereby absorbing excess heat.

In summary, the QFN package is characterized by a good heat dissipation characteristic for the radio frequency power amplifier MMIC Die (chip Die). However, QFN packages also have a not negligible disadvantage, and during QFN package processing, the MMIC Die of the chip is directly placed at the bottom center of the QFN package, and the MMIC Die is connected to each pin through a gold wire, which results in that no circuit structure exists inside the QFN package and outside the MMIC Die, and all circuits need to be implemented on the MMIC Die. The disadvantages caused by this are that, due to the problems of process precision, etc., in the design and processing of the rf power amplifier, the quality factor (Q value) of some devices is poor, and the performance of the rf power amplifier chip cannot be guaranteed.

LGA is known as Land Grid Array, i.e., a Grid Array package. Also, it replaces the conventional pin-like pins with metal contact type packages. LGA is characterized by overcoming the defect that no circuit structure exists inside the QFN package and outside the MMIC Die. Inside the LGA package, a small and thin PCB board can be placed, the designed chip MMIC Die is placed on the PCB board, and the PCB is connected with the pins or the chassis of the LGA package through the through holes. The package has the greatest advantage for the radio frequency power amplifier chip that part of the circuit of the power amplifier chip can be designed outside the MMIC Die, i.e. on the PCB board, and can be an input/output matching circuit, a bias circuit, a power detection circuit, and the like. Because the PCB except the MMIC Die has relatively wide circuit design space, a circuit can be built by adopting a separated component with a high Q value, and the LGA package has the advantage of ensuring the radio frequency performance of a radio frequency power amplifier. LGA packages suffer from the disadvantage of not performing as well as QFN packages. The MMIC Die as the main heating source cannot be in direct contact with the packaging bottom plate, and the contact and the heat dissipation with the bottom plate can be realized only through the PCB with poor heat dissipation effect and the through holes, so that the defect cannot be ignored in the design of the radio frequency power amplifier chip with large power capacity and large heat generation.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a heterogeneous micro-packaging method for a radio frequency power amplifier chip, which can effectively balance the radio frequency performance and heat dissipation in the chip.

The specific technical scheme of the invention is as follows: a heterogeneous micro-packaging method for a radio frequency power amplifier chip comprises a through hole optimization process, and comprises the following specific optimization steps:

s1, modeling the chip package, and performing grid division on the modeling model according to the distribution condition of heat generated when the chip works normally;

s2, determining the highest temperature of each grid by using a thermal analysis tool;

s3, carrying out through hole optimization on grids one by one to obtain a grid layout meeting the working temperature requirement and the device service life requirement corresponding to the grids;

and S4, repeating the step S3 until the optimization of the through holes with more grids is completed.

In step S1, one grid corresponds to a plurality of heat dissipation through holes.

The number of the heat dissipation through holes in the grids at the active elements in the chip is larger than that of the heat dissipation through holes in the grids at the passive elements.

Step S3 includes the following substeps:

s31, determining the number of the heat dissipation holes in the initial grid layout;

s32, after the heat dissipation holes are distributed according to the number of the current heat dissipation holes, the highest temperature of the grid is obtained again according to the step S2, if the highest temperature meets the temperature of normal work of the chip, the step S33 is executed, otherwise, after the number of the heat dissipation holes is added with 1, the highest temperature of the grid is determined again according to the step S2 until the requirement is met;

s33, calculating the service life of the chip according to the current highest temperature of the grid; if the comparison result of the calculated service life and the reference value is greater than 0, the current heat dissipation hole layout scheme is saved, otherwise, the step S32 is returned.

The initial number of heat dissipation holes in step S31 is calculated as:

the number of vias is (the highest temperature of the grid-the temperature at which the chip operates normally)/the heat dissipation capacity of the thermal vias.

The heat dissipation through holes are distributed in an array mode.

The invention has the beneficial effects that: the invention adopts a simulation method to optimize the layout of the radiating holes of the existing package, considers the service life of the period, optimizes the number, types and positions of the radiating through holes, and can achieve better radiating performance while ensuring the advantage of the radio frequency performance of the chip.

Drawings

FIG. 1 is a power amplifier heat transfer system;

FIG. 2 is a hole distribution flow chart of the present invention;

FIG. 3 is a diagram of the temperature profile of the PCB in the MMIC Die and LGA packages of the power amplifier.

Detailed Description

In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.

The heat energy of the power amplifier chip shown in fig. 1 is transferred through two ways, one is a secondary way, the heat energy is transferred to the upper surface of the chip through epoxy resin, and then the heat energy is transferred to the air through a natural convection mode; and the second way is that the heat is transferred to a radiator adhered to the bottom of the PCB through the BackVia, the BT substrate via hole and the PCB application via hole, and the heat is dissipated in an air convection mode. The invention thus builds a thermal resistance network for the chip based on these two approaches.

As shown in fig. 2, a flowchart of a heterogeneous micro-packaging method for a radio frequency power amplifier chip according to the present invention includes the following steps:

1. constructing a thermodynamic performance simulation model, setting relevant parameters and the like required in the solving process, and inputting the temperature range required by the normal work of the power amplifier;

the relevant parameters required in step 1 include: load (e.g., heat flow density, etc.), boundary conditions (e.g., convective boundary conditions, fixed in mechanical simulations, displacement, etc.).

2. The partitioning of the computational grid is such that,

21. next, grid division is performed, aiming at the characteristics of the power amplifier chip. More and more dense meshing of the grid at the active part, i.e. at the transistors, should be considered when designing the algorithm.

22. And establishing a three-dimensional coordinate system in space, selecting the edge of the chip as an origin and selecting a proper distance as a division value to establish a space rectangular coordinate system.

3. The highest temperature in each grid is selected using a thermal analysis tool and stored as the temperature for that grid. As shown in fig. 3.

31. From the temperatures as shown in fig. 3, the coordinates and temperatures at the heat source were found and recorded.

32. A first approximation of each grid temperature is set based on the initial value of each grid temperature. The first approximation does not affect the final result of the iteration, but a good first approximation can shorten the computation iteration time.

4. Insert heat dissipation hole

41. Calculating the number of through holes required to be inserted in the current grid area:

the number of through-holes inserted (the highest temperature of the grid-the temperature that meets the design requirements)/the amount of heat dissipated by the thermal through-holes. And if the calculated number of the through holes is not an integer, rounding up. The number of the through holes obtained by the calculation in the step is used as the initial number of the through holes to be inserted into the current grid area; the heat dissipation capacity of the thermal via here is that of a standard via.

42. According to the characteristics of the power amplifier, holes are required to be punched near the heat source preferentially, namely, heat dissipation holes are punched at positions without transistors in the grid. The punctures are distributed in an array around the power amplifier.

43. When the position of the hole distribution is determined, whether the position is located in the range of the QFN package or the LGA package needs to be determined according to the spatial coordinate point.

44. And inserting the through holes in the current grid area, and if the requirement in 5 is not met, increasing the number of the through holes by 1. The upper limit of the number of the through holes is set to be (area of a divided grid-area of an original element in the grid)/area of a single through hole. When the upper limit is exceeded, the cycle is stopped. If the number of the through holes exceeds the upper limit, the design of the corresponding transistor at the grid is unreasonable, and the design of the transistor needs to be modified again, so that the temperature of the grid after hole distribution can meet the requirement within the upper limit range of the number of the through holes of the grid.

5. And (3) comparing the temperature recorded in the previous step with the temperature range in the step (1) and judging whether the design requirements are met.

6. The lifetime of the device is calculated from the current temperature.

And then setting thermal load and boundary conditions, and finally performing simulation calculation, wherein the simulation result comprises the temperature, stress and deformation of each grid of the model, and the simulation result can be subjected to post-processing to analyze whether the highest temperature of the simulation result exceeds the working temperature of the component or the highest bearing temperature of the material.

According to the theorem of energy conservation, namely the increased internal energy and the dissipated heat energy of the object are equal to the energy generated by the heat source, and the heat conduction equation and the convection heat transfer equation are combined to deduce the heat conduction equation of heat energy transmission in the semiconductor structures such as MMIC and the like, which is expressed as

Where ρ and c represent the density and heat capacity of the corresponding material, respectively,represents the transient temperature distribution of the corresponding structure, k (T) represents the thermal conductivity of the material,represents the instantaneous value of the heat source of the corresponding point, including the sum of all the heat quantities including joule heat, complex heat, thomson heat and the like,temperature values representing a first type of boundary condition, corresponding to the boundary temperature of the heat conduction, h represents the thermal convection coefficient of the third type of boundary condition Γ q, and Ta represents the temperature of the external fluid corresponding to the convection surface. According to the equation, the finite element method is combined to perform simulation calculation of the temperature characteristic.

The experimental data or the thermodynamic simulation result is processed by an Arrhenius formula, so that the service life, the reliability and the like of the equipment at normal working temperature can be obtained.

After the Arrhenius formula is rewritten, the formula can be expressed as

Wherein t is_1,2For failure time, T is absolute temperature, E_aThe value of this variable is temperature dependent for the corresponding activation energy value of the transistor. k is Boltzmann constant, and k＝8.6×10^-5eV/° K. During the initial chip mapping, some heat dissipating through holes are inserted, and the design is subjected to a finite element simulation temperature T1. The initial temperature was taken as T1 and the iteration value (the highest temperature of the grid for which the new hole placement scheme was simulated by the thermal analysis tool) was taken as T₂The points within the grid are computed. Obtaining comparison of expected life with reference

7. If it is notIf the distribution mode is larger than 0, the new distribution mode is saved, and the T2 at the moment is used as the T1 in the S6 for iteration. If it is notIf the heat dissipation hole is smaller than 0, the current hole distribution mode is abandoned, a new heat dissipation hole is inserted, and then the step 4 is returned.

8. The calculated result is processedAnd (7) storing.

9. And (4) operation ending conditions: if the calculation result saved in step 8 is less than δ, it can be considered as converging to a value with little change or the solution in the grid is completely traversed. δ may take the value of 0.1.

10. Exporting the existing design and carrying out result post-processing to check the calculation results such as S parameter, field distribution map and the like

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.