阅读说明：本技术 显示装置 (Display device ) 是由 尾关芳孝 尾崎靖尚 于 2019-12-25 设计创作，主要内容包括：本发明的显示装置具备第一基板；以及第二基板,与所述第一基板对置,所述第一基板具备：绝缘基板；开关元件,位于所述绝缘基板上并具有中继电极；有机绝缘膜,将所述开关元件覆盖,并具有贯通至所述中继电极的第一贯通孔；像素电极,在所述第一贯通孔内与所述中继电极相接；第一电容绝缘膜,在所述第一贯通孔内将所述像素电极覆盖；绝缘性的填充部件,至少填充在所述第一贯通孔内,并位于所述像素电极及所述第一电容绝缘膜上；以及共用电极,将所述填充部件覆盖。(The display device of the invention includes a first substrate; and a second substrate facing the first substrate, the first substrate including: an insulating substrate; a switching element located on the insulating substrate and having a relay electrode; an organic insulating film covering the switching element and having a first through hole penetrating to the relay electrode; a pixel electrode connected to the relay electrode in the first through hole; a first capacitor insulating film covering the pixel electrode in the first through hole; an insulating filling member which is filled in at least the first through hole and is located on the pixel electrode and the first capacitor insulating film; and a common electrode covering the filling member.)

1. A display device is provided with:

a first substrate; and

a second substrate opposed to the first substrate,

the first substrate includes:

an insulating substrate;

a switching element located on the insulating substrate and having a relay electrode;

an organic insulating film covering the switching element and having a first through hole penetrating to the relay electrode;

a pixel electrode connected to the relay electrode in the first through hole;

a first capacitor insulating film covering the pixel electrode in the first through hole;

an insulating filling member which is filled in at least the first through hole and is located on the pixel electrode and the first capacitor insulating film; and

a common electrode covering the filling member.

2. The display device according to claim 1,

the display device is provided with a capacitance electrode on the organic insulating film,

the pixel electrode extends over the capacitor electrode,

the capacitor electrode does not overlap with the first through hole.

3. The display device according to claim 1,

the width of the relay electrode is equal to the width of the first through hole.

4. The display device according to claim 1,

the width of the relay electrode is smaller than the width of the first through hole.

5. The display device according to claim 1,

the filling member protrudes toward the second substrate side.

6. The display device according to claim 1,

the second substrate is provided with a spacer protruding toward the first substrate at a position overlapping the filling member,

the filling member contacts the spacer through the common electrode.

7. The display device according to claim 1,

the switching element has a semiconductor layer and a gate electrode located closer to the insulating substrate than the semiconductor layer.

8. The display device according to claim 1,

the switching element includes a semiconductor layer and a gate electrode located closer to the second substrate than the semiconductor layer.

9. The display device according to claim 1,

the display device further comprises an inorganic insulating film in contact with the lower surface of the relay electrode,

a step portion between the relay electrode and the inorganic insulating film is provided in the first through hole.

10. The display device according to claim 1,

the switching element includes a semiconductor layer connected to the relay electrode in the second through hole,

a part of the second through-hole is located in the first through-hole in a plan view.

Technical Field

Embodiments of the present invention relate to a display device.

Background

In the display device, each pixel has a holding capacitance for holding a signal potential applied to the display element. In recent years, with the high definition of display devices, it has been required to reduce the size of pixel electrodes while maintaining the storage capacitance. In order to increase the storage capacitance, a structure including three transparent electrodes formed by stacking pixels is known.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 2009-58913

Disclosure of Invention

Technical problem to be solved by the invention

An object of the present embodiment is to provide a display device capable of suppressing a decrease in display quality with higher definition.

Means for solving the problems

According to the present embodiment, there is provided a display device including a first substrate; and a second substrate facing the first substrate, the first substrate including: an insulating substrate; a switching element located on the insulating substrate and having a relay electrode; an organic insulating film covering the switching element and having a first through hole penetrating to the relay electrode; a pixel electrode connected to the relay electrode in the first through hole; a first capacitor insulating film covering the pixel electrode in the first through hole; an insulating filling member which is filled in at least the first through hole and is located on the pixel electrode and the first capacitor insulating film; and a common electrode covering the filling member.

Drawings

Fig. 1 is a diagram showing a structure and an equivalent circuit of a display device according to the present embodiment.

Fig. 2 is a plan view showing a configuration example of the pixel shown in fig. 1.

Fig. 3 is a sectional view of the display panel taken along line a-B shown in fig. 2.

Fig. 4 is a cross-sectional view of the first substrate taken along line C-D shown in fig. 2.

Fig. 5 is a modification of the cross-sectional view of the first substrate taken along the line C-D shown in fig. 2.

Fig. 6 is a cross-sectional view showing a detailed configuration example of the relay electrode RE shown in fig. 5.

Fig. 7 is a cross-sectional view showing a first modification of the first substrate.

Fig. 8 is a cross-sectional view showing a second modification of the first substrate SUB 1.

Fig. 9 is a cross-sectional view showing a third modification of the first substrate.

Fig. 10 is a cross-sectional view showing a fourth modification of the first substrate.

Fig. 11 is a cross-sectional view showing a fifth modification of the first substrate.

Fig. 12 is a plan view showing a configuration example of the capacitor electrode shown in fig. 3.

Fig. 13 is a plan view showing a configuration example of the common electrode shown in fig. 3.

Detailed Description

The present embodiment will be described below with reference to the drawings. It is to be noted that the disclosure is merely an example, and appropriate modifications that can be easily made by those skilled in the art to maintain the gist of the invention are naturally included in the scope of the invention. In addition, in order to make the description more clear, the width, thickness, shape, and the like of each part in the drawings are schematically shown in some cases as compared with the actual form, and are merely an example, and do not limit the explanation of the present invention. In the present specification and the drawings, the same reference numerals are given to constituent elements that perform the same or similar functions as those described in the already-shown drawings, and overlapping detailed description may be omitted as appropriate.

Fig. 1 is a diagram showing a configuration and an equivalent circuit of a display device DSP according to the present embodiment.

In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to a direction parallel to a main surface of a substrate constituting the display device DSP, and the third direction Z corresponds to a thickness direction of the display device DSP. In the present specification, a direction toward the tip of an arrow indicating the third direction Z is referred to as an upward direction (or simply an upward direction), and a direction opposite from the tip of the arrow is referred to as a downward direction (or simply a downward direction).

The display device DSP includes a display panel PNL and a wiring substrate WB attached to the display panel PNL. The display panel PNL is a liquid crystal display panel, and includes a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1, a sealant SE, a liquid crystal layer LC, signal lines S, scanning lines G, switching elements SW, pixel electrodes PE, a common electrode CE, and the like. The display panel PNL includes a display area DA for displaying an image and a non-display area NDA surrounding the display area DA. The display panel PNL may be a display panel having an electrophoretic element.

The first substrate SUB1 has a mounting portion MA exposed to the outside of the second substrate SUB 2. The seal material SE is located in the non-display area NDA and bonds the first substrate SUB1 and the second substrate SUB 2. In fig. 1, the region where the seal material SE is disposed is indicated by oblique lines. The display area DA is located inside surrounded by the seal material SE. The display panel PNL includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y in the display region DA.

The signal lines S, the scanning lines G, the switching elements SW, the pixel electrodes PE, the common electrodes CE, and the liquid crystal layer LC are located in the display area DA. The signal lines S extend in the second direction Y, and the scan lines G extend in the first direction X. The switching element SW is formed of, for example, a Thin Film Transistor (TFT), and is electrically connected to the scanning line G and the signal line S. The pixel electrode PE is electrically connected to the switching element SW. The pixel electrodes PE face the common electrode CE, respectively, and the liquid crystal layer LC is driven by an electric field generated between the pixel electrodes PE and the common electrode CE. The holding capacitor CS is formed between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE, for example.

The flexible wiring substrate WB is attached to the attachment portion MA. The wiring substrate WB includes a driving IC chip 2 for driving the display panel PNL. The driver IC chip 2 may be mounted on the mounting portion MA.

The display panel PNL of the present embodiment may be either a transmissive type having a transmissive display function of selectively transmitting light from the back surface side of the first substrate SUB1 to display an image, a reflective type having a reflective display function of selectively reflecting light from the front surface side of the second substrate SUB2 to display an image, or a transflective type having a transmissive display function and a reflective display function.

Fig. 2 is a plan view showing a configuration example of the pixel PX shown in fig. 1. In fig. 2, the capacitor electrode and the common electrode CE are not shown. Fig. 10 shows a detailed plan view of the capacitor electrode, and fig. 11 shows a detailed plan view of the common electrode CE.

The scanning lines G1 and G2 extend in the first direction X and are arranged at intervals in the second direction Y. The signal lines S1 and S2 extend in the second direction Y and are arranged at intervals in the first direction X. The pixel PX corresponds to a region partitioned by the scanning lines G1 and G2 and the signal lines S1 and S2.

In one example, the switching element SW is a thin film transistor of a double gate type. The switching element SW includes a relay electrode RE, a semiconductor layer SC, gate electrodes GE1 and GE2, and the like.

The relay electrode RE is located between the signal line S1 and the signal line S2. A part of the relay electrode RE overlaps the scanning line G1. The relay electrode RE has a width W1 in the first direction X. The interval GP1 between the relay electrode RE and the signal line S1 is smaller than the width W1. Likewise, the interval GP2 between the relay electrode RE and the signal line S2 is smaller than the width W1.

The semiconductor layer SC has a first portion SC1, a second portion SC2, and a third portion SC 3. First section SC1 is located directly below signal line S1. The first portion SC1 extends in the second direction Y and intersects the scan line G1. The second portion SC2 is located between the signal line S1 and the signal line S2. The second portion SC2 extends in the second direction Y and intersects the scan line G1. Third portion SC3 extends in first direction X, connecting first portion SC1 with second portion SC 2.

The semiconductor layer SC is connected to the signal line S1 at the through hole CH 1. The signal line S1 functions as a source electrode of the switching element SW. The semiconductor layer SC is connected to the relay electrode RE at the through hole CH 2. The relay electrode RE functions as a drain electrode of the switching element SW. The gate electrode GE1 corresponds to a portion of the scan line G1 that overlaps with the first portion SC 1. The gate electrode GE2 corresponds to a portion of the scan line G1 that overlaps with the second portion SC 2.

The pixel electrode PE is located in a region surrounded by the scanning lines G1 and G2 and the signal lines S1 and S2. The pixel electrode PE overlaps the scanning line G1, the relay electrode RE, and the through hole CH 2. In the illustrated example, the pixel electrode PE has a substantially rectangular shape having long sides extending in the second direction Y, and is formed over substantially the entire pixel PX. The pixel electrode PE is connected to the relay electrode RE at the through hole CH 3. The through hole CH3 overlaps a part of the through hole CH 2. That is, a part of the through hole CH2 is located inside the through hole CH3 in a plan view. In fig. 2, the through holes CH1 to CH3 are illustrated as being rectangular, but may be circular or chamfered at each corner.

The through hole CH3 has end portions EG1 to EG 4. In addition, the relay electrode RE has end portions EG11 to EG 14. The end EG1 overlaps the end EG 11. As shown in fig. 2, the end EG2 overlaps the end EG 12. The end EG3 overlaps the through hole CH 2. The end EG4 overlaps the scan line G1.

Fig. 3 is a sectional view of the display panel PNL taken along line a-B shown in fig. 2. The display panel PNL of the present embodiment has a structure corresponding to a display mode using a lateral electric field along the main surface of the substrate.

The first substrate SUB1 includes an insulating substrate 10, switching elements SW, insulating films 11 to 15, a capacitor electrode CEL, a pixel electrode PE, a filling member 100, a common electrode CE, an alignment film AL1, and the like.

The insulating substrate 10 is a transparent substrate such as a glass substrate or a resin substrate. The switching element SW is located on the insulating substrate 10. The switching element SW includes gate electrodes GE1 and GE2, a semiconductor layer SC, and a relay electrode RE. The gate electrodes GE1 and GE2 are provided on the insulating substrate 10 and covered with the insulating film 11. The semiconductor layer SC is provided on the insulating film 11 and covered with the insulating film 12. The illustrated switching element SW is a bottom-gate thin film transistor in which the gate electrodes GE1 and GE2 are located closer to the insulating substrate 10 than the semiconductor layer SC. The switching element SW may be a top gate thin film transistor as described later. The signal line S1 and the relay electrode RE are disposed on the insulating film 12. The signal line S1 and the relay electrode RE are connected to the semiconductor layer SC through the through holes CH1 and CH2 penetrating the insulating film 12, respectively.

The semiconductor layer SC is formed of, for example, polysilicon. The gate electrodes GE1 and GE2, the relay electrode RE, and the signal line S1 are formed of a metal material such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), or chromium (Cr), or an alloy obtained by combining these metal materials. The gate electrodes GE1 and GE2, the relay electrode RE, and the signal line S1 may have a single-layer structure or a multi-layer structure.

The insulating film 13 covers the switching element SW. The insulating film 13 has a through hole CH3 penetrating to the relay electrode RE. The ends EG3 and EG4 of the through hole CH3 correspond to the ends of the bottom of the through hole CH 3. The end portions EG3 and EG4 do not overlap with the end portions EG13 and EG14 of the relay electrode RE. The end EG3 is located on the end EG14 side with respect to the end EG 13. The end EG4 is located on the end EG13 side with respect to the end EG 14. The capacitor electrode CEL is formed on the insulating film 13. The capacitor electrode CEL is located between the insulating film 13 and the pixel electrode PE. The capacitance electrode CEL does not overlap the through hole CH 3. The insulating film 14 covers the capacitor electrode CEL and is also formed on the insulating film 13. A part of the insulating film 14 extends into the through hole CH 3. The pixel electrode PE is formed on the insulating film 14. The pixel electrode PE is in contact with the relay electrode RE in the through hole CH 3. Thereby, the signal potential supplied to the signal line S1 is supplied to the pixel electrode PE via the relay electrode RE.

The insulating film 15 covers the pixel electrode PE. The insulating film 15 is also provided in the through hole CH3, and covers the pixel electrode PE in the through hole CH 3. In the illustrated example, the insulating film 15 is also formed on the insulating film 14. The filling member 100 is filled in the through hole CH 3. The filling member 100 is in contact with the insulating film 15 in the through hole CH 3. The filling member 100 protrudes toward the second substrate SUB2 side. As described later, the filling member 100 may not protrude toward the second substrate SUB2 side. The filling member 100 is formed by the same process and the same material as the spacer formed on the first substrate SUB1, for example. The common electrode CE is formed on the insulating film 15. In addition, the common electrode CE covers the filling member 100. In addition, in one example, the common electrode CE has a plurality of openings OP. The openings OP are respectively opposed to the pixel electrodes PE. The common electrode CE is covered with an alignment film AL 1. The alignment film AL1 is also provided over the insulating film 15 at the opening OP. In the present embodiment, the relay electrode RE, the pixel electrode PE, the insulating film 15, the filling member 100, the common electrode CE, and the alignment film AL1 are stacked in this order at a position overlapping the through hole CH 3.

The insulating films 11, 12, 14, and 15 are formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating film 13 is formed of an organic insulating material such as polyimide. The capacitor electrode CEL, the pixel electrode PE, and the common electrode CE are formed of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In the present embodiment, the capacitor electrode CEL and the common electrode CE are at the same potential. The pixel electrode PE has a potential different from that of the capacitor electrode CEL and the common electrode CE. In one example, a common potential common to the pixels is supplied to the capacitive electrode CEL and the common electrode CE. The common potential may be a direct current potential or an alternating current potential. The pixel electrode PE is supplied with a signal potential corresponding to each pixel. The fringe field for driving the liquid crystal layer LC is mainly formed by the pixel electrode PE and the common electrode CE which are opposed to each other with the insulating film 15 interposed therebetween. The capacitor for holding the signal potential is formed of the pixel electrode PE and the common electrode CE facing each other with the insulating film 15 interposed therebetween, and is also formed of the capacitor electrode CEL and the pixel electrode PE facing each other with the insulating film 14 interposed therebetween.

The second substrate SUB2 includes an insulating substrate 20, a light-shielding layer 21, a color filter layer 22, an overcoat layer 23, a spacer SP, and an alignment film AL 2.

The insulating substrate 20 is a transparent substrate such as a glass substrate or a resin substrate. The light-shielding layer 21 and the color filter layer 22 are provided on the side of the insulating substrate 20 facing the first substrate SUB 1. The light-shielding layer 21 is made of, for example, a black colored resin, and divides each pixel PX. In the illustrated example, the light shielding layer 21 faces the signal line S1, the switching element SW, the through hole CH3, and the like. The overcoat layer 23 covers the color filter layer 22. The spacer SP is provided on the side of the overcoat 23 facing the first substrate SUB 1. The spacer SP is disposed at a position overlapping the filler member 100. The filling member 100 is in contact with the spacer SP via the common electrode CE, the alignment films AL1, and AL 2. The alignment film AL2 covers the overcoat layer 23 and the spacer SP. Note that the alignment film AL2 may not be disposed on the surface of the spacer SP on the first substrate SUB1 side. Similarly, the alignment film AL1 may not be provided on the second substrate SUB2 side of the filling member 100.

The liquid crystal layer LC is positioned between the first substrate SUB1 and the second substrate SUB 2. The first substrate SUB1 and the second substrate SUB2 are arranged such that the alignment film AL1 faces the alignment film AL 2. A predetermined cell gap (cell gap) is formed between the alignment film AL1 and the alignment film AL2 by a spacer (not shown). The liquid crystal layer LC is filled in the cell gap.

Fig. 4 is a cross-sectional view of the first substrate SUB1 taken along line C-D shown in fig. 2. In fig. 4, the semiconductor layer SC between the insulating substrate 10 and the insulating film 11 is not shown.

The through hole CH3 has a width W11 in the first direction X. The relay electrode RE has a width W12 in the first direction X. In the present embodiment, the width W12 is equal to or less than the width W11. Note that "equal" means that these widths are the same, or that width W12 is slightly larger than width W11 but has slight differences to the extent that they can be considered the same. In the present embodiment, when the difference between these widths is about ± 1 μm, they are considered to be equal. In the illustrated example, the widths W11 and W12 are equal to each other, and the end EG1 overlaps the end EG11, and the end EG2 overlaps the end EG 12. Further, the width W11 of the through hole CH3 is defined by the width of the bottom of the through hole CH 3. In addition, when the through hole CH3 is circular in plan, the diameter thereof is set to the width of the through hole CH 3.

Fig. 5 is a modification of the cross-sectional view of the first substrate SUB1 taken along the line C-D shown in fig. 2. The structure shown in fig. 5 differs from the structure shown in fig. 4 in that the through hole CH3 is offset toward the signal line S1 with respect to the relay electrode RE.

In this modification, not only the relay electrode RE but also the insulating film 12 is located in the through hole CH 3. Therefore, the insulating film 14 is in contact with the insulating film 12 in the through hole CH 3. The end EG1 of the through hole CH3 is located closer to the signal line S1 than the end EG11 of the relay electrode RE. The end EG2 of the through hole CH3 is located closer to the signal line S1 than the end EG12 of the relay electrode RE.

The relay electrode RE has a corner CN1 on the signal line S1 side and a corner CN2 on the signal line S2 side. The corner CN1 is not covered with the insulating film 13 and is located in the through hole CH 3. Corner CN2 is covered with insulating film 13. In addition, the pixel electrode PE covers the corner CN 1. The insulating film 15 is interrupted at a position overlapping the corner CN1, for example. The pixel electrode PE is exposed from the interrupted portion of the insulating film 15. The filling member 100 covers the pixel electrode PE exposed in the corner CN 1.

In the case of a high definition display device, since a certain distance or more is maintained between the relay electrode RE and the signal line S1 and between the relay electrode RE and the signal line S2 to prevent short-circuiting, the width W12 of the relay electrode RE may be equal to or smaller than the width W11 of the through hole CH 3. Therefore, when the position of the relay electrode RE and the through hole CH3 is shifted, the corner CN1, that is, the step between the upper surface of the relay electrode RE and the insulating film 12 is located in the through hole CH3, and the insulating film 15 is broken by the step, and the pixel electrode PE may not be completely covered. This may short-circuit the pixel electrode PE to the common electrode CE formed on the pixel electrode PE via the insulating film 15.

According to the present embodiment, the filling member 100 is interposed between the pixel electrode PE and the common electrode CE at a position overlapping the through hole CH 3. Therefore, even if the pixel electrode PE is exposed at the corner CN1, the insulating state between the pixel electrode PE and the common electrode CE can be maintained by the filling member 100. Therefore, a short circuit between the pixel electrode PE and the common electrode CE can be prevented.

Fig. 6 is a cross-sectional view showing a detailed configuration example of the relay electrode RE shown in fig. 5.

The relay electrode RE has a first layer REA formed of titanium, a second layer REB formed of aluminum, and a third layer REC formed of titanium. Due to the difference in the etching rate of each layer, the second layer REB formed of aluminum is more removed when etching the relay electrode RE than the first layer REA and the third layer REC formed of titanium. Therefore, the third layer REC may protrude from the second layer REB. The protruding portion of the third layer REC corresponds to the corner CN 1. This may deteriorate the coverage of the insulating film 15. In such a case, as described above, the occurrence of short circuit between the pixel electrode PE and the common electrode CE can also be suppressed.

Fig. 7 is a cross-sectional view showing a first modification of the first substrate SUB 1. The configuration shown in fig. 7 differs from the configuration shown in fig. 4 in that the width W12 of the relay electrode RE is smaller than the width W11 of the through hole CH 3.

In this modification, the insulating film 12 is in contact with the insulating film 14 and the pixel electrode PE in the through hole CH3, as well as the relay electrode RE. The end EG1 of the through hole CH3 is located closer to the signal line S1 than the end EG11 of the relay electrode RE. The end EG2 of the through hole CH3 is located closer to the signal line S2 than the end EG12 of the relay electrode RE.

The corner portions CN1 and CN2 are not covered with the insulating film 13, but are located in the through holes CH 3. The pixel electrode PE covers the corner portions CN1 and CN 2. The insulating film 15 may be broken at a position overlapping the corner portions CN1 and CN2 (i.e., stepped portions), for example, but even if the pixel electrode PE is exposed from the broken portion of the insulating film 15, the exposed pixel electrode PE is covered with the filling member 100. Therefore, a short circuit between the pixel electrode PE and the common electrode CE can be prevented.

In the first modification as well, the same effects as those of the above embodiment can be obtained.

Fig. 8 is a cross-sectional view showing a second modification of the first substrate SUB 1. The configuration shown in fig. 8 differs from the configuration shown in fig. 7 in that the relay electrode RE is located on the signal line S2 side.

The end EG1 of the through hole CH3 is located closer to the signal line S1 than the end EG11 of the relay electrode RE. The end EG2 of the through hole CH3 overlaps the end EG12 of the relay electrode RE. The corner CN1 is not covered with the insulating film 13 and is located in the through hole CH 3. The pixel electrode PE covers the corner CN1 and the surface of the insulating film 12 in the through hole CH 3. The other structures are the same as those of fig. 7, and the description thereof is omitted.

In such a second modification, the same effects as those of the above embodiment can be obtained.

Fig. 9 is a cross-sectional view showing a third modification of the first substrate SUB 1. The structure shown in fig. 9 is different from the structure shown in fig. 3 in that the switching element SW is a top gate thin film transistor.

The insulating film 11 covers the insulating substrate 10. The semiconductor layer SC is located above the insulating film 11. The insulating film 11A covers the semiconductor layer SC. The gate electrodes GE1 and GE2 are located on the insulating film 11A. The insulating film 12 covers the gate electrodes GE1 and GE 2. The gate electrodes GE1 and GE2 are located closer to the second substrate SUB2 than the semiconductor layer SC. The through holes CH1 and CH2 penetrate the insulating films 11A and 12 to the semiconductor layer SC.

In such a third modification, the same effects as those of the above embodiment can be obtained.

Fig. 10 is a cross-sectional view showing a fourth modification of the first substrate SUB 1. The structure shown in fig. 10 is different from the structure shown in fig. 3 in that the first substrate SUB1 does not have the capacitor electrode CEL.

The pixel electrode PE is located on the insulating film 13. The pixel electrode PE is in contact with the side surface SS of the through hole CH 3. The insulating film 15 covers the pixel electrode PE and is also in contact with the insulating film 13.

In such a fourth modification, the same effects as those of the above embodiment can be obtained.

Fig. 11 is a cross-sectional view showing a fifth modification of the first substrate SUB 1. The configuration shown in fig. 11 differs from the configuration shown in fig. 3 in that the filling member 100 does not protrude toward the second substrate SUB2 side.

The filling member 100 has an upper surface 100A on the second substrate SUB2 side. Further, a portion of the upper surface of the common electrode CE located between the openings OP is referred to as an upper surface CEA. The upper surface 100A is located closer to the insulating substrate 10 than the upper surface CEA. At this time, the spacer SP of the second substrate SUB2 may be in contact with the first substrate SUB1 at a position overlapping the filler member 100, or may be separated from the first substrate SUB 1.

In the fifth modification, the same effects as those of the above embodiment can be obtained.

Fig. 12 is a plan view showing a configuration example of the capacitive electrode CEL shown in fig. 3. In fig. 12, the pixel electrode PE shown in fig. 2 is not shown. Note that illustration of the common electrode CE shown in fig. 13 is omitted.

The capacitive electrode CEL overlaps a plurality of pixels PX arranged in the first direction X. More specifically, the capacitor electrodes CEL extend in the first direction X and are arranged at intervals in the second direction Y. The capacitor electrode CEL is formed in a band shape having a substantially constant width WE 1. The width WE1 is less than the pitch P1 of adjacent scan lines G1-G3. Here, the width WE1 and the pitch P1 are defined in the second direction Y. The capacitor electrode CEL partially overlaps the scanning lines G1 to G3, the signal lines S1 to S3, the semiconductor layer SC, and the relay electrode RE, respectively, but does not overlap the through hole CH 3. That is, the through holes CH3 aligned in the first direction X are located between the capacitor electrodes CEL adjacent in the second direction Y.

Fig. 13 is a plan view showing a configuration example of the common electrode CE shown in fig. 3. In fig. 13, the pixel electrode PE shown in fig. 2 is not shown. Note that the capacitive electrode CEL shown in fig. 12 is not shown.

The common electrode CE overlaps a plurality of pixels PX arranged in the first direction X and the second direction Y. In one example, the common electrode CE is formed of a single member. The common electrode CE overlaps the relay electrode RE and the through hole CH 3. The common electrode CE has an opening OP in each pixel PX. One opening OP overlaps one pixel electrode. The openings OP are located between the adjacent signal lines S1 to S3 and between the adjacent scan lines G1 to G3. The opening OP does not overlap the relay electrode RE. In the illustrated example, the opening OP has a first portion OPA extending in the second direction Y and a plurality of second portions OPB extending in the first direction X. A plurality of second parts OPB are connected to the first part OPA. Since the common electrode CE has the opening OP, the area where the common electrode CE overlaps the pixel electrode PE is smaller than the area where the capacitor electrode CEL overlaps the pixel electrode PE.

As described above, according to the present embodiment, a display device capable of suppressing the deterioration of display quality with high definition can be obtained.

Although several embodiments of the present invention have been described, these embodiments are merely provided as examples, and are not intended to limit the scope of the present invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.